60 results on '"Debusschere, I."'
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2. Optimization of gate stack parameters towards 3D-SONOS application
3. Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors
4. Ionizing radiation hardening of a CCD technology
5. A 1006 element hybrid silicon pixel detector with strobed binary output
6. Understanding of Trap-Assisted Tunneling Current - Assisted by Oxygen Vacancies in RuOx/SrTiO3/TiN MIM Capacitor for the DRAM Application.
7. Advanced Capacitor Dielectrics: Towards 2x nm DRAM.
8. Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology.
9. High Performance THANVaS Memories for MLC Charge Trap NAND Flash.
10. An Ultra-Thin Hybrid Floating Gate Concept for Sub-20nm NAND Flash Technologies.
11. Investigation of rare-earth aluminates as alternative trapping materials in Flash memories.
12. Optimization of the crystallization phase of Rare-Earth aluminates For blocking dielectric application in TANOS type flash memories.
13. Exploration of rare earth materials for future interpoly dielectric replacement in Flash memory devices.
14. 3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding.
15. O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory.
16. 3D stacked IC demonstration using a through Silicon Via First approach.
17. FUSI Specific Yield Monitoring Enabling Improved Circuit Performance and Fast Feedback to Production.
18. Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics.
19. 90nm RF CMOS technology for low-power 900MHz applications [amplifier example].
20. Thin L-shaped spacers for CMOS devices.
21. Optimisation of a Pre-Metal-Dielectric with a contact etch stop layer for 0.18um and 0.13um technologies.
22. Characterization of the Ionizing Radiation Sensitivity of a CCD Technology.
23. Optimizing and controlling the radiation hardness of a CCD process.
24. Temperature dependent electrical characteristics of through-si-via (TSV) interconnections.
25. Scaling of Floating Gate electrode for sub-40nm flash technologies.
26. Integration of CMOS-electronics and particle detector diodes in high-resistivity silicon-on-insulator wafers.
27. Importance of determining the polysilicon dopant profile during process development.
28. Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology.
29. Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory.
30. Impact of bottom electrode and SrxTiyOz film formation on physical and electrical properties of metal-insulator-metal capacitors.
31. Impact of crystallization behavior of SrxTiyOz films on electrical properties of metal-insulator-metal capacitors with TiN electrodes.
32. Towards 1X DRAM: Improved leakage 0.4 nm EOT STO-based MIMcap and explanation of leakage reduction mechanism showing further potential.
33. Novel dual layer floating gate structure as enabler of fully planar flash memory.
34. Hot-carrier degradation on the analogue/RF performances of a 90nm RF-CMOS technology demonstrated in a 900MHz low-power LNA.
35. A 400mm long linear X-ray sensitive image sensor.
36. Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology.
37. Standard cell level parasitics assessment in 20nm BPL and 14nm BFF.
38. Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology.
39. Ultra thin hybrid floating gate and high-k dielectric as IGD enabler of highly scaled planar NAND flash technology.
40. A 1006 element hybrid silicon pixel detector with strobed binary output.
41. Integration of CMOS-electronics in an SOI layer on high-resistivity silicon substrates.
42. Detector diodes and test devices fabricated in high resistivity SOI wafers.
43. A retinal CCD Sensor for fast 2D shape recognition and tracking
44. Study of different sensor types for high resolution linear CCD-imagers
45. Generation lifetime monitoring on high resistivity silicon using gated diodes
46. Electron detection by means of silicon solid state imagers
47. New concepts for integrated solid state detector electronics
48. Development of test structures for silicon particle detectors
49. Design implications of a p-well CMOS technology for the realization of monolithic integrated pixel arrays
50. Development of silicon micropattern (pixel) detectors
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