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The impact of the interface layer on charge trapping and polarization switching at multiple temperatures is investigated. At high temperatures, a ferroelectric field effect transistor with a metal-ferroelectric-insulator-semiconductor (MFIS) gate-stack shows conventional electron-trapping dominated PBTI (i.e., $\Delta \text{V}_{\mathrm{ t}} > 0$ ), whereas at room temperature, negative threshold voltage shifts ( $\Delta \text{V}_{\mathrm{ t}}$ ) are observed. We demonstrate the relationship between the interface layer and the subsequently deposited ferroelectric layers’ effective permittivity: higher permittivity, consistent with a higher tetragonal phase/lower orthorhombic phase content, is noted when the ferroelectric layer is deposited on hydrogen-terminated silicon. In contrast, an anomalous BTI, consistent with a higher orthorhombic phase content, is observed at lower temperatures when the ferroelectric layer is deposited on oxygen-rich surfaces (SiO2, SiON).

Herein, the line-edge roughness (LER)-induced random performance variation–immune effect of metal–interlayer–semiconductor (MIS) source/drain (S/D) in 7 nm n-type Ge (n-Ge) junctionless field-effect transistors (JLFETs) were investigated by 3-D TCAD simulations. Compared to the device without MIS S/D, the n-Ge JLFET with MIS S/D could effectively reduce the Ge fin doping concentration while maintaining the performance. It was demonstrated analytically that the reduced Ge fin doping concentration of the device with MIS S/D, compared to the device without MIS S/D, decreased the LER-induced random performance variations of the n-Ge JLFET; the standard deviations were reduced to ~0.0318 V for ${V} _{\text {th}}$ (reduced by ~51.6%), $4.89\times 10^{\text {-6}}$ A/ $\mu \text{m}$ for ${I} _{\text {on}}$ (reduced by ~92.1%), $1.44\times 10^{\text {-9}}$ A/ $\mu \text{m}$ for ${I} _{\text {off}}$ (reduced by ~93.7%), 1.27 mV/dec for SS (reduced by ~23.1%), and ~5.40 mV/V for drain-induced barrier lowering (DIBL) (reduced by ~30.8%). In addition, LER-induced random performance variation was investigated in terms of scaling down fin widths. The results provided critical insight into the variability reduction of the 7 nm n-Ge JLFETs.

The OFF-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ ) and threshold voltage ( ${V}_{{\mathrm {T}}}$ ) of a HfO2-based threshold-switching (TS) device for phase-transition fully depleted silicon-on-insulator (FDSOI) device on silicon substrate can be improved, e.g., ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ is increased by implementing a multilayered HfO2/Al2O3 (rather than HfO2 layer only). The HfO2/Al2O3 layer with the atomic layer deposition (ALD) cycle ratio of 3:1 (i.e., Hf:Al = 3:1) shows approximately $3.47\times 10^{11}\,\Omega $ of average ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ and approximately 2.12 V of average ${V}_{{\mathrm {T}}}$ . Next, ${V}_{{\mathrm {T}}}$ can be modulated by adjusting the work function of the bottom electrode. We demonstrate that a high work function of the bottom electrode results in stronger built-in electric-field and tunneling, decreasing ${V}_{{\mathrm {T}}}$ and ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ . The Hf3Al1-based TS device with platinum electrode shows approximately 0.88 V of average ${V}_{{\mathrm {T}}}$ and approximately $2.81\times 10^{9}\,\Omega $ of average ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ . The phase-transition FDSOI device used in this work is fabricated by connecting the optimized TS device in series to the drain electrode of a baseline FDSOI device, whose channel length is 130 nm. The phase-transition FDSOI device shows the minimum subthreshold slope of 9 mV/decade owing to the abrupt resistive switching of the TS device. Additionally, it exhibits an increase in the ON/ OFF-state current ratio by three times because of high ${R}_{ \mathrm{\scriptscriptstyle OFF}}$ .

Line-edge-roughness (LER) is one of undesirable process-induced random variation sources. LER is mostly occurred in the process of photo-lithography and etching, and it provokes random variation in performance of transistors such as metal oxide semiconductor field effect transistor (MOSFET), fin-shaped field effect transistor (FinFET), and gate-all-around field effect transistor (GAAFET). LER was analyzed/characterized with technology computer-aided design (TCAD), but it is fundamentally very time consuming. To tackle this issue, machine learning (ML)-based method is proposed in this work. LER parameters (i.e., amplitude, and correlation length X, Y) are provided as inputs. Then, artificial neural network (ANN) predicts 7-parameters [i.e., off-state leakage current (Ioff), saturation drain current (Idsat), linear drain current (Idlin), low drain current (Idlo), high drain current (Idhi), saturation threshold voltage (Vtsat), and linear threshold voltage (Vtlin)] which are usually used to evaluate the performance of FinFET. First, how datasets for training process of ANN were generated is explained. Next, the evaluation method for probabilistic problem is introduced. Finally, the architecture of ANN, training process and our new proposition is presented. It turned out that the prediction results (i.e., non-Gaussian distribution of device performance metrics) obtained from the ANN were very similar to that from TCAD in the respect of both qualitative and quantitative comparison.

The gate induced drain leakage (GIDL) effect in negative capacitance (NC) FinFET is investigated. A Landau–Ginzburg–Devonshire equation (which considers the polarization gradient in ferroelectric material) is used to estimate the characteristics of the NC FinFET. Specifically, metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NC FinFETs are compared, in order to figure out the effect of the internal metal layer on the GIDL effect. To analyze the impact of the polarization gradient on the GIDL effect in NC FinFET, a polarization gradient coefficient is varied. For MFMIS, the polarization gradient doesn't significantly affect the device performance. The subthreshold swing improves but the GIDL effect deteriorates because of the “uniform” NC effect in channel region. For MFIS, the device performance is explicitly affected by the polarization gradient. Smaller polarization gradients result in non-uniform NC effect in channel region, resulting in severe GIDL effects. On the other hand, higher polarization gradients alleviate GIDL effects.

The feedback field-effect transistor (FBFET) is a new type of transistor that uses a positive feedback mechanism, which enables the FBFET to exhibit steep-switching characteristics, i.e., subthreshold swing (SS) < 60 mV/decade at 300 K. The silicon-on-insulator (SOI) FBFET, which was studied previously, can be optimized by adjusting the fin height and fin width. For a given effective channel width, a device with low average SS and high ON-state drive current can be designed by stacking gate-all-around channels. In this article, for given various design parameters, the performance metrics of various stacked SOI FBFET device structures are compared. In addition, we investigated the transient characteristics of the SOI FBFETs. Using mixed-mode simulations, we confirmed whether the ON– OFF switching characteristics are completely implemented over time or not.

Power- and solar-to-chemical energy conversion has been spotlighted as a promising technology for the efficient use of renewable energy resources. In principle, various chemicals can be sustainably...

The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS)

In this study, a gate-stack engineering technique is proposed as a means of improving the performance of a 28 nm low-power (LP) high-k/metal-gate (HK/MG) device. In detail, it was experimentally verified that HfSiO thin films can replace HfSiON congeners, where the latter are known to have a good thermal budget and/or electrical characteristics, to boost the device performance under a limited thermal budget. TiN engineering for the gate-stack in the 28 nm LP HK/MG device was used to suppress the gate leakage current. Using the proposed fabrication method, the on/off current ratio (Ion/Ioff) was improved for a given target Ion, and the gate leakage current was appropriately suppressed. Comparing the process-of-record device against the 28 nm LP HK/MG device, the thickness of the electrical oxide layer in the new device was reduced by 3.1% in the case of n-type field effect transistors and by 10% for p-type field effect transistors. In addition, the reliability (e.g., bias temperature instability, hot carrier injury, and time-dependent dielectric breakdown) of the new device was evaluated, and it was observed that there was no conspicuous risk. Therefore, the HfSiO film can afford reliable performance enhancement when employed in the 28 nm LP HK/MG device with a limited thermal budget.

A metal-ferroelectric-metal (MFM) capacitor was fabricated to investigate the effect of the rate-of-change of temperature in the rapid thermal annealing (RTA) process on the physical properties of the MFM capacitor’s ferroelectric layer [lead zirconate oxide (PZT)]. Remnant polarization (2 × Pr) is measured and monitored while performing the RTA process at 500 °C–700 °C. It turned out that, for a given target/final temperature in the RTA process, 2Pr of the ferroelectric layer decreases with a higher rate-of-change of temperature. This can provide a way to adjust the properties of the PZT layer, depending on the RTA process condition (i.e., using various rate-of-changes of temperature) for a given final/target temperature.

This study presents the improved memory properties of TiN/Al2O3/Si3N4/SiO2/poly-Si (TANOS) capacitors after rapid thermal annealing (RTA) and high-pressure annealing processes (HPAP) using H2 and D2 molecules. First, it was confirmed that the recrystallization rate, and thus the grain size of the poly-silicon (poly-Si) film, increased with an increase of the RTA temperature, eventually improving the performance of the TANOS capacitor by reducing the trap densities at the poly-Si/SiO2 interface. Then, it was found that device performance parameters, such as program/erase speed and data retention, could be further improved through HPAP owing to the passivation of band gap states at the poly-Si channel grain boundary. Finally, it was confirmed that these improvements can be observed at a transistor level in the same fashion using the Silvaco TCAD simulation.

An in-depth study on the photovoltaic characteristics under indoor lights, i.e., light-emitting diode (LED), fluorescent lamps, and halogen lamps, was performed with varying the photoactive layer thickness (120–870 nm), by comparing those under 1-sun condition. The semi-crystalline mid-gap photoactive polymer, poly[(2,5-bis(2-hexyldecyloxy)phenylene)-alt-(5,6-difluoro-4,7-di(thiophen-2-yl)benzo[c][1,2,5]thiadiazole)] (PPDT2FBT) and a fullerene derivative, [6,6]-phenyl C71 butyric acid methyl ester (PC70BM) were used as a photoactive layer. In the contrary to the measurements under 1-sun condition, the indoor devices show a clearly different behavior, showing the thickness tolerant short-circuit current density (JSC) and fill factor (FF) values with 280–870 nm thick photoactive layers. The retained JSC and FF values of thick indoor devices were discussed in terms of the parasitic resistance effects based on the single-diode equivalent circuit model. The much lower series/shunt resistance (Rs/RP) ratio was measured with thick photoactive layer (≥280 nm), resulting in negligible decreases in the JSC and FF values even with a 870-nm-thick active layer under the LED condition. Under 1000 lx LED light, the PPDT2FBT:PC70BM device showed an optimum power conversion efficiency (PCE) of 16% (max power density, 44.8 μW/cm2) with an open-circuit voltage of 587 mV, a JSC of 117 μA/cm2, and a FF of 65.2. The device with a 870-nm-thick active layer still exhibited an excellent performance with a PCE of 12.5%. These results clearly suggest that the critical parasitic resistance effects on the performance vary depending on the light illumination condition, and the large RP associated with the viable thick photoactive layer and the well-matched absorption (of photoactive layer) with the irradiance spectrum (of indoor light) are essential to realize efficient indoor photovoltaic cells with high JSC and FF.

A tunnel field-effect transistor with segmented channels (Seg-TFET) on a corrugated substrate is proposed. The Seg-TFET takes advantage of using three stripes and the selective contact configuration to define the direction of current, and thereby its device performance can be improved. Furthermore, the process flow of the Seg-TFET demonstrates a substantiation of the new device structure. Consequently, its current flow is simply defined by adjusting the appropriate contact configuration at metal-zero-level without any additional front-end-of-line process.

A ferroelectric-gated nanoelectromechanical (NEM) nonvolatile random-access memory cell [negative capacitance (NC)-NEM memory] is proposed and investigated. By adjusting the structural parameters of the NEM relay, the pull-in voltage of the NC-NEM memory cell can be reduced, and its pull-out voltage can even become negative. Hence, an NEM relay with a ferroelectric layer in the gate stack can be used as a nonvolatile random-access memory cell. Herein, the device design and operational principles for read/program/erase are introduced in detail. The program/erase voltage and the program delay time of the NC-NEM memory cell have been quantitatively estimated.

As an effort to overcome the physical limitation of scaling down the size of transistors and to implement ultra-low-power consumption in integrated circuits, the use of negative quantum capacitance has attracted significant attention, because it can simply enhance the gate capacitance in field-effect transistors. Among various two-dimensional materials, topological insulators (TI) have immense potential to achieve the effect of negative quantum capacitance, because they can be included in the gate stack of conventional metal oxide semiconductor (MOS) field-effect transistors. In order to verify their advantages for various gate capacitance values, we have fabricated a MOS capacitor with a TI. At room temperature, the capacitance enhancement (i.e., total gate capacitance higher than the theoretically estimated geometric capacitance) of the capacitor was experimentally observed near the depletion region. The effect of negative quantum capacitance, which is caused by the electron system on the surface of TI, demonstrates that the gate capacitance can increase in the range of frequency, i.e., 50–100 kHz.

Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator (SOI) FBFET with extremely steep switching (~1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. The prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail.

Gate configuration phase transition fully depleted silicon-on-insulator (FDSOI) metal- oxide-semiconductor field-effect transistor (MOSFET) without an external resistor is proposed using Pb(Zr0.52Ti0.48)O3 (PZT)-based threshold selector (TS). Under 1 μA compliance current condition, the PZT-based TS exhibits its threshold switching property at ~0.9 V (threshold voltage) and ~0.01 V (hold voltage) over 4 orders of current. And its off-resistance is measured as ~2.3 × 1011 Ω. The PZT-based gate configuration phase transition FDSOI MOSFET without an external resistor was fabricated by connecting the PZT-based TS to a baseline FDSOI MOSFET. It is confirmed that the fabricated external resistor-free phase transition FDSOI MOSFET can operate regardless of the aforementioned 1 μA of compliance current condition. This device has not only demonstrated the feature of ~4 mV/decade subthreshold slope at ~0.96 V of gate voltage, but it also has decreased the gate leakage current of the baseline FDSOI MOSFET by ~10 times at 0 V of gate voltage and ~320 times at 2 V of gate voltage.

The 3-D technology computer-aided design simulations were performed with four metal-gate materials (i.e., titanium nitride, tungsten nitride, tantalum nitride, and molybdenum nitride) to quantitatively estimate the magnitude of work-function variation (WFV)-induced threshold-voltage variation (WFV-induced $\sigma {V}_{\mathrm{TH}}$ ) in high- $\kappa $ /metal-gate (HK/MG) MOSFETs [e.g., fin-shaped field-effect transistor (FinFET) and fully depleted silicon-on-insulator MOSFETs]. We found that the extended gate area effect in FinFETs extensively varied depending on the gate materials used. In order to substantially suppress the WFV-induced $\sigma {V}_{\mathrm{TH}}$ in HK/MG complementary metal–oxide–semiconductor technology, a new metal-gate material with the following characteristics should be developed: 1) higher standard deviation of probability for all grains and 2) lower standard deviation of WF values for all grains.

As the physical size of MOSFET has been aggressively scaled-down, the impact of process-induced random variation (RV) should be considered as one of the device design considerations of MOSFET. In this work, an artificial neural network (ANN) model is developed to investigate the effect of line-edge roughness (LER)-induced random variation on the input/output transfer characteristics (e.g., off-state leakage current (Ioff), subthreshold slope (SS), saturation drain current (Id,sat), linear drain current (Id,lin), saturation threshold voltage (Vth,sat), and linear threshold voltage (Vth,lin)) of 5 nm FinFET. Hence, the prediction model was divided into two phases, i.e., “Predict Vth” and “Model Vth”. In the former, LER profiles were only used as training input features, and two threshold voltages (i.e., Vth,sat and Vth,lin) were target variables. In the latter, however, LER profiles and the two threshold voltages were used as training input features. The final prediction was then made by feeding the output of the first model to the input of the second model. The developed models were quantitatively evaluated by the Earth Mover Distance (EMD) between the target variables from the TCAD simulation tool and the predicted variables of the ANN model, and we confirm both the prediction accuracy and time-efficiency of our model.

Supercapacitors have shown great potential as a possible solution to the increasing global demand for next-generation energy storage systems. Charge repositioning is based on physical or chemical mechanisms. There are three types of supercapacitors—the electrochemical double layer, the pseudocapacitor, and a hybrid of both. Each type is further subdivided according to the material used. Herein, a detailed overview of the working mechanism as well as a new method for capacitance enhancement are presented.

The impact of interface layer on charge trapping and polarization switching at multiple temperatures is investigated. At high temperature, the FeFET with metal-ferroelectric-insulator semiconductor (MFIS) gate-stack shows conventional electron-trapping dominated PBTI (i.e. $\Delta \mathrm{V}_{\mathrm{t}}\lt0$), whereas at room temperature, negative threshold voltage shifts $(\Delta \mathrm{V}_{\mathrm{t}})$ are observed. We demonstrate a link between interface layer and the subsequently-deposited ferroelectric layers effective permittivity: higher permittivity, consistent with higher tetragonal phase/ lower orthorhombic phase content is seen when the ferroelectric layer is deposited on hydrogen terminated silicon, whereas anomalous BTI consistent with higher orthorhombic phase is observed when the ferroelectric is deposited on oxygen-rich $(\mathrm{S}\mathrm{i}\mathrm{O}_{2}$, SiON) surfaces.

This paper confirms that the electrical characteristics of FinFETs such as the on/off ratio, drain-induced barrier lowering (DIBL), and sub-threshold slope (SS) can be improved by optimizing the FinFET spacer structure. An operating voltage that can maintain a life of 10 years or more when hot-carrier injection is extracted. An excellent on/off ratio (7.73&times, 107) and the best SS value were found at 64.29 mV/dec with a spacer length of 90 nm. Under hot carrier-injection conditions, the supply voltages that meet the 10-year lifetime condition are 1.11 V, 1.18 V, and 1.32 V for spacer lengths of 40 nm, 80 nm, and 120 nm, respectively. This experiment confirmed that, even at low drain voltages, the shorter is the spacer length, the greater is the deterioration. However, this increasing maximum operating voltage is very small when compared to the increase in the driving voltage required to achieve similar performance when the spacer length is increased, therefore, the effective life is expected to decrease. The results indicate that structural optimization must be performed to increase the driving current of the FinFET and prevent degradation of the analog performance.

Since the discovery of ferroelectricity in HfO2-based materials which are comparable to the complementary metal-oxide&ndash, semiconductor (CMOS) fabrication process&mdash, a negative capacitance effect in the HfO2-based materials has been actively studied. Owing to nonuniform polarization-switching (which is originated from the polycrystalline structures of HfO2-based ferroelectric materials), the formation of multi-domains in the HfO2-based materials is inevitable. In previous studies, perovskite-based ferroelectric materials (which is not compatible to CMOS fabrication process) were utilized to improve the electrical properties of a nanoelectromechanical (NEM) relay. In this study, the effects of a multi-domain HfO2-based ferroelectric material on the electrical characteristics of an NEM relay were theoretically examined. Specifically, the number of domains, domain inhomogeneity and ferroelectric thickness of the multi-domain ferroelectric material were modulated and subsequently, its corresponding results were discussed. It was observed that the switching voltage variation was decreased with increasing the number of domains and decreasing domain inhomogeneity. In addition, the switching voltage was decreased with increasing ferroelectric thickness, owing to enhanced voltage amplification.

Threshold voltage adjustment in threshold switching (TS) devices with HfO2/Al2O3 superlattice (by means of changing the cycle ratio of HfO2 to Al2O3 in atomic layer deposition) is investigated to implement a transparent cross-point array. TS devices with different cycle ratios (i.e., 3:1, 3:2, and 3:3) were fabricated and studied. The threshold voltage of the devices was increased from 0.9 V to 3.2 V, as the relative contents of Al2O3 layer in the superlattice were increased. At the same time, it is demonstrated that the off-resistance values of the devices were enhanced from 2.6 109 to 6 1010 as the atomic layer deposition (ALD) cycle ratio of HfO2 to Al2O3 layer was adjusted from 3:1 to 3:3. However, the hold voltage and the on-current values were almost identical for the three devices. These results can be understood using the larger barrier height of Al2O3 layer than that of HfO2 layer.

This work presents an analysis of the endurance of ferroelectric capacitors fabricated with a thin lanthanum-doped hafnium oxide layer in an SFS type of structure. The thin film has been measured by GIXRD and the main crystallographic parameters have been related to the ferroelectric behavior of the samples. The effect of variation in the process conditions, particularly La doping concentration and post deposition anneal, have also been investigated. It has been found that the crystallographic composition of the FE layer plays a role in the endurance of material.

Feedback field-effect transistors (FBFETs) are devices based on a positive feedback loop in which the electrons and holes in the channel region act on the energy states of the potential barrier and wall. Owing to the positive feedback phenomenon, FBFETs have an excellent subthreshold swing (~0 mV/decade at 300 K), a high on-/off current ratio (~1010), and a clear saturation region. The power consumption of both the turn-on state and turn-off state is significantly low until operation commences. In addition, the hysteresis caused by the carriers accumulated in the potential wall allows the FBFET to act as a memory device. Moreover, the power consumption of neuromorphic devices can be suppressed by ~100 times with the use of FBFETs. In this work, we analyze the device structure and operating principle of the FBFET and summarize its applications.

A ferroelectric-gated fin-shaped field effect transistor (Fe-FinFET) is fabricated by connecting a Pb(Zr0.2Ti0.8)O3-based ferroelectric capacitor into the gate electrode of FinFET. The ferroelectric capacitor shows coercive voltages of approximately &minus, 1.5 V and 2.25 V. The polarization-induced threshold voltage shift in the Fe-FinFET is investigated by regulating the gate voltage sweep range. When the maximum positive gate to source voltage is varied from 4 V to 2 V with a fixed starting negative gate to source voltage, the threshold voltage during the backward sweep is increased from approximately &minus, 0.60 V to 1.04 V. In the case of starting negative gate to source voltage variation from &minus, 4 V to &minus, 0.5 V with a fixed maximum positive gate to source voltage of 4 V, the threshold voltage during the forward sweep is decreased from 1.66 V to 0.87 V. Those results can be elucidated with polarization domain states. Lastly, it is observed that the threshold voltage is mostly increased/decreased when the positive/negative gate voltage sweep range is smaller/larger than the positive/negative coercive voltage, respectively.

The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS) $ mV/decade at 300 K. In this work, the n-type NCFET (i.e., pull-down (PD) and pass-gate (PG) transistor in SRAM bitcell) has SS of 53.92 mV/decade, and the p-type NCFET (i.e., pull-up (PU) transistor in SRAM bit-cell) has SS of 58.96 mV/decade. In the NCFET-based SRAM cell (vs. conventional SRAM cell with conventional planar bulk MOSFETs), its read (hold)-stability and write-ability are evaluated by the metric of read static noise margin (SNM) and write-ability current $(\mathbf{I}_{\mathbf{w}})$ , respectively. Then, under process-induced variation, the yield of NCFET-based SRAM array (vs. conventional SRAM array) is quantitatively estimated, using the cell-sigma.

In this work, the measured electrical characteristics of a fully depleted silicon-on-insulator (FDSOI) device and fin-shaped field-effect transistor (FinFET), whose gate electrode is connected in series to the bottom electrode of a ferroelectric capacitor (FE-FDSOI/FE-FinFET), are experimentally studied. The hysteretic property in input transfer characteristic of those devices is desirable for memory device applications, so that the understanding and modulating the hysteresis window is a key knob in designing the devices. It is experimentally observed that the hysteresis window of FE-FDSOI/FE-FinFET is decreased with (i) increasing the area of the ferroelectric capacitor and/or (ii) decreasing the gate area of baseline FET. The way how to control the hysteresis window of FE-FDSOI/FE-FinFET is proposed and discussed in detail.

A negative differential resistance fin-shaped field-effect transistor (NDR-FinFET) using a Pb(Zr0.52Ti0.48)O3 threshold selector (TS) is investigated. From the measured input transfer characteristic of NDR-FinFET, the following results are demonstrated: 1) superior reduction of off current by a factor of 350 (as compared to a baseline FinFET); 2) on current of NDR-FinFET comparable to that of the baseline FinFET; and 3) subthreshold slope of 3 mV/decade at 300 K. The operating principle of NDR-FinFET is demonstrated using MATLAB simulation. In the on-to-off and off-to-on switching processes, the existence of an unstable resistive switching region is verified through the comparison between simulation data and experimental results. The major device parameters that affect the formation of the unstable resistive switching region are revealed. Finally, it is proposed that: 1) lowering the hold voltage of the TS and 2) applying the drain voltage comparable to the threshold voltage can have the NDR-FinFET to work appropriately (i.e., not in unstable region).

With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal–oxide–semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor channel TFTs are experimentally demonstrated with solution-based fabrication process. Especially, this paper shed light on the NC effect in the organic-based TFTs. The step-up current-voltage characteristics are repeatedly and reliably observed in diverse TFTs, and then, with the results, transconductance ( $g_{m}$ ) amplification implemented by the negative capacitance was delved. Moreover, with the aid of ferroelectric polarization switching, super steep-switching characteristic of the organic-based TFT was experimentally confirmed. These experimental results and discussion would be helpful in understanding NC effects in TFTs.

The operating voltage of a nanoelectromechanical (NEM) relay can be scaled down significantly using negative capacitance (NC), which is a unique property of ferroelectric materials. It has been observed that a ferroelectric capacitor can amplify the internal voltage of a device (higher than the externally applied voltage) by means of the NC effect. In this simulation work, depending on the structural parameters of a ferroelectric capacitor and an NEM relay, an NC + NEM relay (in which the gate electrode of the NEM relay is connected in series to the ferroelectric capacitor) was investigated. As a result, a sub-0.5-V operating voltage is theoretically estimated.

For a given three different Si doping concentrations at room and high temperatures, the threshold voltage shift (ΔVth) on silicon-doped hafnium-oxide-based ferroelectric field effect transistor (FeFET) is experimentally investigated. It turned out that charge trapping in the gate stack of FeFET (versus polarization switching in the gate stack of FeFET) adversely affects ΔVth. Charge trapping causes the positive ΔVth, while polarization switching causes the negative ΔVth. The dominance of polarization switching is predominantly determined by the total remnant polarization (2Pr), which can be controlled by adjusting Si doping concentration in the hafnium-oxide layer. As the Si doping concentration increases from 2.5% to 3.6%, and 5.0%, 2Prdecreases 19.8μC cm-2to 15.25μC cm-2, and 12.5μC cm-2, which leads to ΔVthof -0.8 V, -0.09 V, and +0.1 V, respectively, at room temperature. At high temperature, the effect of polarization switching is degraded due to the decreasedPr, while the effect of charge trapping is very independent of temperature. For those three different Si doping concentrations (i.e. 2.5%, 3.6%, and 5.0%), at the high temperature, ΔVthof FeFET is -0.675 V, -0.075 V, and +0.15 V, respectively. This experimental work should provide an insight for designing FeFET for memory and logic applications.

A metal–interlayer–semiconductor (M–I–S) structure with excellent thermal stability and electrical performance for a nonalloyed contact scheme is developed, and considerations for designing thermally stable M–I–S structure are demonstrated on the basis of n-type germanium (Ge). A thermal annealing process makes M–I–S structures lose their Fermi-level unpinning and electron Schottky barrier height reduction effect in two mechanisms: (1) oxygen (O) diffusion from the interlayer to the contact metal due to high reactivity of a pure metal contact with O and (2) interdiffusion between the contact metal and semiconductor through grain boundaries of the interlayer. A pure metal contact such as titanium (Ti) provides very poor thermal stability due to its high reactivity with O. A structure with a tantalum nitride (TaN) metal contact and a titanium dioxide (TiO2) interlayer exhibits moderate thermal stability up to 400 °C because TaN has much lower reactivity with O than with Ti. However, the TiO2 interlayer cann...

In stacked-nanowire field-effect transistors (stacked-NW FETs), the effect of nanowire surface roughness (NWSR) and random interface traps (RIT) on device performance variation is investigated. The 3-D NWSR profile is applied to the surface of the nanowires, and then, the interface traps are generated and randomly placed in the interfacial layer between the silicon and high-k. First, the interaction between NWSR and RIT in a single-NW FET is investigated; the NWSR-induced performance varia- tion is not independent on the RIT-induced variation. Then, the correlation of NWSR profiles and RIT in stacked-NW FETs is explored. The degree of correlation between the NWSR profiles of stacked-NWs is varied in three cases: 1) positively correlated; 2) negatively correlated; and 3) uncorrelated. Without RITs, the NWSR-induced performance variation of the stacked-NW FETs dramatically increases as the NWSR profiles of the nanowires become positively correlated. However, with RITs, the more positively correlated the NWSR profiles of the nanowires, the larger is the ${V}_{T}$ variation that the interface traps induce. Interface traps barely affect the ${V}_{T}$ variation of the negatively correlated NWSR profiles. The variation of current slightly decreases because interface charge scattering degrades the mobility of the carriers.

This article looks into dynamics of open social enterprises. We used several research methods—literature review, content analysis and case studies through intensive interviews via semi-structured questionnaire. First, we developed a research framework, expressed as the social open innovation dynamics model through literature reviews on social economy, sharing economy, collaborative innovation, open innovation and social enterprise. Second, we applied the model to ten Korean social enterprises and determined the success factors of social open innovation, as well as the concrete dynamics behind it. Main finding of this research are as follows. The success of social enterprises depends on the extent to which they strive to move towards open innovation. Adopting open innovation strategies seem to be a fruitful pathway for social enterprises to progress and grow in their operations.

A topological insulator (TI) is a new kind of material that exhibits unique electronic properties owing to its topological surface state (TSS). Previous studies focused on the transport properties of the TSS, since it can be used as the active channel layer in metal-oxide-semiconductor field-effect transistors (MOSFETs). However, a TI with a negative quantum capacitance (QC) effect can be used in the gate stack of MOSFETs, thereby facilitating the creation of ultra-low power electronics. Therefore, it is important to study the physics behind the QC in TIs in the absence of any external magnetic field, at room temperature. We fabricated a simple capacitor structure using a TI (TI-capacitor: Au-TI-SiO2-Si), which shows clear evidence of QC at room temperature. In the capacitance-voltage (C-V) measurement, the total capacitance of the TI-capacitor increases in the accumulation regime, since QC is the dominant capacitive component in the series capacitor model (i.e., CT−1 = CQ−1 + CSiO2−1). Based on the QC model of the two-dimensional electron systems, we quantitatively calculated the QC, and observed that the simulated C-V curve theoretically supports the conclusion that the QC of the TI-capacitor is originated from electron–electron interaction in the two-dimensional surface state of the TI.

Improving the performance of resistive switching memories, while providing high transparency and excellent mechanical stability, has been of great interest because of the emerging need for electronic wearable devices. However, it remains a great challenge to fabricate fully flexible and transparent resistive switching memories because not enough research on flexible and transparent electrodes, for their application in resistive switching memories, has been conducted. Therefore, it has not been possible to obtain a nonvolatile memory with commercial applications. Recently, an electrode composed of a networked structure of Ag nanowires (AgNWs) embedded in a polymer, such as colorless polyimide (cPI), has been attracting increasing attention because of its high electrical, optical, and mechanical stability. However, for an intended use as a transparent electrode and substrate for resistive switching memories, it still has the crucial disadvantage of having a limited surface coverage of conductive pathways. Here, we introduce a novel approach to obtain a AgNWs/cPI composite electrode with a high figure-of-merit, mechanical stability, surface smoothness, and abundant surface coverage of conductive networks. By employing the fabricated electrodes, a flexible and transparent resistive memory could be successfully fabricated.

In this letter, a semi-analytical current–voltage model for a negative capacitance field-effect transistor (NCFET) with a ferroelectric material ( i.e. , BaTiO3) is proposed. Surface potential ( $\psi _{\mathrm {S}})$ in the channel region is determined first by solving the Landau–Khalatnikov (LK) equation numerically with Poisson’s equation. Then, the drain–current is achieved based on the current continuity equation using $\psi _{\mathrm {S}}$ determined earlier. In addition, by introducing a fitting potential for a given drain–voltage, threshold voltage shift can be captured, resulting in accurate surface potential and drain–current at different gate voltages. We have verified our model using the technology computer-aided design (TCAD)-MATLAB simulation, and our model exhibits an excellent agreement to the simulation results. In addition, the impacts of the ferroelectric thickness and channel doping concentration on the device performance and hysteresis window of NCFET are thoroughly explored.

Using 3-D technology computer aided design simulation, we investigated the impact of equivalent oxide thickness (EOT) on threshold voltage ( ${V}_{{\text {TH}}}$ ) variation induced by work-function variation (WFV) in multigate devices. The WFV-induced ${V}_{{\text {TH}}}$ variation in multigate devices does not significantly vary with the dielectric constant of the gate dielectric material, but increases with decreasing physical oxide thickness ( ${T}_{{\text {OX}}}$ ). As ${T}_{{\text {OX}}}$ becomes thinner, electric field tends to be locally concentrated, causing a large variation of electrostatic potential in channel. The slope of the ratio of average grain size to gate area (RGG) plot is observed with various oxide thicknesses. It is confirmed that we can alleviate the WFV-induced ${V}_{{\text {TH}}}$ variation without significant performance degradation if gate dielectric layer becomes thicker with appropriately adopted higher-k engineering. In addition, the impact of EOT (including interface layer) on the WFV-induced ${V}_{{\text {TH}}}$ variation is studied.

In this letter, an n-type short-channel negative capacitance FinFET (NC-FinFET) with a hysteresis window of 0.48 V, an on-/off-current ratio of 107, and a sub-20-mV/decade average subthreshold slope (SSavg) that is intended to overcome the Boltzmann limit (i.e., the physical limit in the SS, which is 60 mV/decade at 300 K), is experimentally demonstrated vs. a baseline FinFET with an SSavg of ~105 mV/decade. In our testing, we confirmed that the large hysteresis window in a short-channel NC-FinFET can be suppressed by using an appropriate source/drain extension length ( $\text {L}_{\text {ext}})$ . As $\text {L}_{\text {ext}}$ in the NC-FinFET is increased, the gate-to-source/drain capacitance ( $\text {C}_{\text {GS}}/\text {C}_{\text {GD}})$ decreased and the hysteresis window narrows.

The transient response of negative capacitance (NC) in an organic ferroelectric capacitor is experimentally investigated. To observe the transient response of the NC, a simple series network, consisting of an external series resistor and an organic ferroelectric capacitor, is built. The Landau coefficients of the organic ferroelectric capacitor were extracted from the measured polarization versus applied electric field data. A circuit level simulation was provided with the extracted parameters based on the Landau–Khalatnikov equation. To explore the impact of the RC time constant on the NC time duration in the RC series circuit, the external series resistor is altered as a tuning parameter. Also, the effect of various temperatures of the ferroelectric capacitor on the NC time duration is experimented. This paper demonstrates that either the external resistor or the ambient temperature can change the NC time duration in an organic ferroelectric capacitor.

Thin film transistors (TFTs) with anatase-TiO2 channel material deposited on an SiO2/Si substrate by atomic layer deposition are fabricated to investigate the effect of the source/drain (S/D) metal work function on the electrical characteristics of the TFTs. S/D materials such as aluminum, silver, and gold are selected for this study. From the measured current-voltage characteristic curves in the dark and at room temperature, it is demonstrated that the anatase TiO2-based TFT with Ag S/D material shows the highest on/off-current ratio (~ 105), field effect mobility in the saturation regime (μsat = 5.17 cm2V−1s−1), and saturation current (IDS,sat ~ 0.47 mA).

A perfect ohmic contact formation technique for low-resistance source/drain (S/D) contact of germanium (Ge) n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed. A metal–interlayer–semiconductor (M–I–S) structure with an ultrathin TiO2/GeO2 interlayer stack is introduced into the contact scheme to alleviate Fermi-level pinning (FLP), and reduce the electron Schottky barrier height (SBH). The TiO2 interlayer can alleviate FLP by preventing formation of metal-induced gap states (MIGS) with its very low tunneling resistance and series resistance and can provide very small electron energy barrier at the metal/TiO2 interface. The GeO2 layer can induce further alleviation of FLP by reducing interface state density (Dit) on Ge which is one of main causes of FLP. Moreover, the proposed TiO2/GeO2 stack can minimize interface dipole formation which induces the SBH increase. The M–I–S structure incorporating the TiO2/GeO2 interlayer stack achieves a perfect ohmic characteristic, which ...

As the physical sizes of devices have been scaled down, the negative impact of process-induced random variation on device performance has increased; therefore, there is an urgent demand for advanced simulation methods for variation. In this paper, a 3-D quasi-atomistic simulation methodology for line edge roughness (LER) in nonplanar devices, such as FinFETs and gate-all-around (GAA) FETs, is proposed. In addition, a simple gate oxide layer model is proposed to analyze the impact of LER on device performance while excluding the impact of oxide thickness variation. To verify the importance of the quasi-atomistic 3-D LER model and to compare the LER-induced performance variation in a FinFET to that in a GAA FET, the case studies using the 3-D quasi-atomistic LER model for FinFETs and GAA FETs are performed.

The effect of a triple metal-gate (TMG) on the performance and on the ambipolar current in a TMG vertical tunnel field-effect transistor with triple metal-gate (TMG-TFET) is investigated using technology computer-aided design simulation. The TMG-TFET is designed to tackle the performance as well as the ambipolar current, simultaneously, by modulating the TMG parameters—the work function of the TMG and/or the length of each MG—that have critical impacts on the energy-band diagrams of the channel region. The tempered on-/off-current ratio of $10^{\mathrm { {8}}}$ and the steep average subthreshold slope of 43.5 mV/decade at a power supply voltage of 0.5 V are ascribed to the formation of an energy barrier in the channel by the optimal device parameters. It is found that two main flaws in a conventional (single-material gate) TFET, which are the degraded on-state current and the ambipolar current, can be successfully controlled by adjusting the TMG structure.

In order to construct a design that exhibits variation immunity, the impacts of line-edge roughness (LER) of nanowires (NWs) in stacked-nanowire FETs (stacked-NW FETs) are investigated using 3-D LER simulations. To explore the LER-induced performance variations in stacked-NW FETs, three geometrical parameters are considered: 1) the correlation coefficient (P) between the LER profiles of NWs; 2) the cross-sectional area ratio (d) that represents the volume difference between NWs; and 3) the number of stacked NWs (n). In terms of the correlation between the LER profiles of NWs, positively correlated LER profiles cause the largest performance mismatches. In contrast, when the LER profiles between NWs are uncorrelated or negatively correlated, the performance variations are suppressed effectively. On the other hand, the performance variation can be reduced by a volume difference between the NWs in stacked-NW FETs (especially, when the lower NW is larger than the upper NW in stacked-NW FETs). Finally, in terms of the number of stacked NWs, the performance variation decreases as the number of stacked NWs increases, as long as the LER profiles of the NWs are poorly correlated.

A germanium-source vertical tunnel field-effect transistor with a field-enhanced high- $\kappa $ layer (FEHL-VTFET) is proposed to improve the device performance. The FEHL-VTFET takes advantage of bandgap engineering as well as field-enhancing engineering (i.e., a strong fringing electric field is used in the source region). The ON-state drive current ( $I_{\sc {\mathrm{ ON}}})$ is $69~\mu \text{A}/\mu \text{m}$ at $V_{DS} = V_{GS} =0.5$ V, and is 20 times higher than that of a germanium-source VTFET without the FEHL. The average subthreshold slope (SS) is 37.5 mV/decade at 300 K. The large permittivity constant of FEHL enhances both the $I_{\sc {\mathrm{ ON}}}$ and the average SS. Finally, the drain-induced barrier thinning is alleviated, because the use of an FEHL with a high- $\kappa $ layer can induce a stronger electric field in the source region; therefore, the tunneling generation rate is mainly determined by the gate voltage (and not by the drain voltage).

The impact of process-induced random dopant fluctuation (RDF)-induced threshold voltage ( $V_{\mathrm{ th}}$ ) variation on the performance of 7-nm n-type germanium (Ge) FinFETs with and without a metal–interlayer–semiconductor (MIS) source/drain (S/D) structure is investigated using 3-D TCAD simulations. In order to reduce the RDF-induced $V_{\mathrm{ th}}$ variation, an MIS S/D structure with a heavily doped n-type zinc oxide (ZnO) interlayer is used in the S/D region of the Ge FinFET. Thus, without performance degradation, the Ge FinFET with an MIS S/D structure achieves approximately threefold reduction in the RDF-induced $V_{\mathrm{ th}}$ variation (versus without an MIS S/D structure). The impact of various fin parameters (i.e., fin height and fin width) on the RDF-induced $V_{\mathrm{ th}}$ variation is also investigated. It is noteworthy that variation is suppressed as the fin height (fin width) increases (decreases).

Efforts have been made to improve the performance of social enterprises through many studies on social entrepreneurs and social entrepreneurship. However, previous studies have conceptualized social entrepreneurship based on researches on commercial entrepreneurs. In addition, the scale used in the analysis of social entrepreneurship focuses primarily on behavioral aspects. Although the social and economic values pursued by social enterprises are important virtues for social entrepreneurs, research on the value orientation of social entrepreneurship is insufficient. The essence of a social enterprise is creating social value based on financial sustainability, so the concept of blended value has been recently emphasized. This study analyzed the relationships among blended value orientation, social entrepreneurship, and the performance of social enterprises. The results indicate that the blended value orientation of social entrepreneurs influenced social entrepreneurship and performance, social entrepreneurship fully mediated blended value orientation and performance. These findings suggest that it is important to focus on the blended value orientation of social entrepreneurs and social entrepreneurship in the promotion and policies of social enterprises.