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Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called "data deluge gap"). This has resulted in both the academic and industrial community investigating novel computing paradigms and design approaches at all levels from materials, devices, circuits, architectures, and all the way to system-level implementations and applications. For example, to improve performance, the community has been investigating solutions through massively parallel and distributed systems that are a rupture from von Neumann architectures. As artificial neural networks (ANN) and deep neural networks (DNN) that are trained over hundreds of graphic processing units (GPU)-accelerated servers where each GPU can have thousands of cores. The limitations of data processing through the memory wall in von Neumann architectures have been overcome with bringing computing to the data inspired by biological brainlike computing. An alternative computing approach based on ANNs uses oscillators to compute or oscillatory neural networks (ONNs). Such an approach differs from classical CMOS and classical von Neumann where building blocks are analog and perform computations efficiently. Moreover, data is encoded on the oscillator signals phase, which is a departure from the classical voltage level-based data encoding (such as amplitude voltage to represent a logical bit '1' or '0'). ONNs can perform computations efficiently and can be used to build a more extensive neuromorphic system. How should a designer choose to optimally implement ONNs in analog is the focus of many ongoing research efforts. But here, we address a more fundamental problem, can we efficiently perform AI applications (such as image/pattern recognition) with ONNs? In other words, what are the advantages and limitations of the ONN computing paradigm for practical AI applications? Here, we present a digital ONN implementation to show a proof-of-concept of the ONN approach of "computing-in-phase" for pattern recognition applications. To the best of our knowledge, this is the first attempt to implement an FPGA-based fully-digital ONN. We report ONN accuracy, training, inference, memory capacity, operating frequency, hardware resources based on simulations and implementations of 5x3 and 10x6 ONNs. We present the digital ONN implementation on FPGA for pattern recognition applications such as performing digits recognition from a camera stream. We discuss practical challenges and future directions in implementing digital ONN.

The spread of epidemics and diseases is known to exhibit chaotic dynamics; a fact confirmed by many developed mathematical models. However, to the best of our knowledge, no attempt to realize any of these chaotic models in analog or digital electronic form has been reported in the literature. In this work, we report on the efficient FPGA implementations of three different virus spreading models and one disease progress model. In particular, the Ebola, Influenza, and COVID-19 virus spreading models in addition to a Cancer disease progress model are first numerically analyzed for parameter sensitivity via bifurcation diagrams. Subsequently and despite the large number of parameters and large number of multiplication (or division) operations, these models are efficiently implemented on FPGA platforms using fixed-point architectures. Detailed FPGA design process, hardware architecture and timing analysis are provided for three of the studied models (Ebola, Influenza, and Cancer) on an Altera Cyclone IV EP4CE115F29C7 FPGA chip. All models are also implemented on a high performance Xilinx Artix-7 XC7A100TCSG324 FPGA for comparison of the needed hardware resources. Experimental results showing real-time control of the chaotic dynamics are presented.

In this work, the implementations of the LBlock, Piccolo, Twine, and Klein lightweight ciphers in FPGA technology are studied in terms of area, frequency, throughput, and throughput/area. To accomplish this, loop unrolling and pipelining were employed in two phases. In the first phase, different loop unrolling factors were used to implement the round function of each cipher, while in the second phase, 2-stage pipelining with loop unrolling per stage was applied. The produced designs were implemented in Xilinx (Kintex-7) FPGA technology. Based on the implementation results, a detailed study on the above-mentioned design metrics was performed and important outcomes were derived.

Lightweight cryptography is a vital and fast growing field in today&rsquo, s world where billions of constrained devices interact with each other. In this paper, two novel compact architectures of the Enocoro-128v2 stream cipher are presented. The Enocoro-128v2 is part of the ISO/IEC 29192-3 standard. The first architecture has an 8-bit datapath while the second one has a 4-bit datapath. The proposed architectures were implemented on the BASYS3 board (Artix 7 XC7A35T) using the VERILOG hardware description language. The hardware implementation of the proposed 8-bit architecture runs at a 189 MHz clock and reaches a throughput equal to 302 Mbps, while at the same time, it utilizes only 254 Look-up Tables (LUTs) and 330 Flip-flops (FFs). Each round of computations requires 5 clock cycles. The 4-bit implementation has an operating frequency of 204 MHz and reaches a throughput equal to 181 Mbps, with each round requiring 9 clock cycles. The 4-bit implementation utilizes 249 LUTs and 343 FFs. To our knowledge, this is the first time that such implementations of the Enocoro-128v2 are presented. Both implementations utilize a very low number of resources (only 78 FPGA slices are required for the 8-bit architecture and only 83 for the 4-bit one) and the results demonstrate that they are sustainable for area constrained embedded devices.

The recently uncovered problem of multi-point progressive blocking (MPB) has significantly increased the complexity of schedulability analysis of priority-preemptive wormhole networks-on-chip. While state-of-the-art analysis is currently deemed safe, there is still significant inherent pessimism when it comes to considering backpressure issues caused by downstream indirect interference. In this paper, we attempt to simplify the problem by considering a novel flow control protocol that can avoid backpressure issues, enabling simpler schedulability analysis approaches to be used. Rather than construct the analysis to fit the protocol, we modify the protocol so that effective analysis applies. We describe the changes to a baseline wormhole router in order to implement the proposed protocol, and comment on the impact on hardware overheads. We also examine the number of routers that actually require these changes. Comparative analysis of FPGA implementations show that the hardware overheads of the proposed NoC router are comparable or lower than those of the baseline, while analytical comparison shows that the proposed approach can guarantee schedulability in up to 77% more cases.

The increasing complexity of new digital signal processing (DSP) applications is forcing the use of floating point (FP) numbers in their hardware implementations. In this brief, we investigate the advantages of using half-unit biased (HUB) formats to implement these FP applications on field-programmable gate arrays (FPGAs). These new FP formats allow for the effective elimination of the rounding logic on FP arithmetic units. First, we experimentally show that HUB and standard formats provide equivalent signal-to-noise ratio on DSP application implementations. We then present a detailed study of the improvement achieved when implementing FP adders and multipliers on FPGAs by using HUB numbers. In most of the cases studied, the HUB approach reduces resource use and increases the speed of these FP units while always providing statistically equivalent accuracy as that of conventional formats. However, for some specific sizes, HUB multipliers require far more resources than the corresponding conventional approach.

International audience; We present various FPGA implementations of protections against SCAs for RLWE-based PKE. We implemented the main solutions from the state of the art with improved variants. We also propose a new protection based on a redundant representation of the ring elements to randomize computations. We compare the implementation results of all these solutions.

This research investigates the use of FPGAs to create a fully autonomous system to detect hotspots on high voltage insulators by processing infrared videos. Initial algorithm development was conducted with MATLAB. The algorithm was automated by the addition of automatic temperature tracking and arc detection giving a sixtyfold speed increase (85 Hz). Explored two FPGA implementations of the algorithm: Verilog only; an embedded processor running compiled C++ code. Applications include post processing and live stream processing where alerts can be fed to maintenance teams of transmission system operators.

In this work, we propose a high-level synthesis approach for hardware sandboxes in system-on-chip. Using interface formalism to capture interactions between non-trusted IPs and trusted parts of a system on chip, along with the properties specification language to specify non-authorized actions of non-trusted IPs, sandboxes are generated and made ready for inclusion as IP in a system-on-chip design. The concepts of composition, compatibility, and refinement are used to capture illegal actions and optimize resources across the boundary of single IPs. We have designed a tool that automatically generates the sandbox and facilitates their integration into system-on-chip. Our approach was validated with benchmarks from trust-hub.com and FPGA implementations. All our results showed 100% Trojan detection and mitigation, with only a minimal increase in resource overhead and no performance decrease.

With the increasing need for highly secure systems, Physical Unclonable Functions (PUFs) have emerged within the last decade. Ordering based Ring Oscillator (RO) PUFs are one of the best performing structures with their robustness and suitability to FPGA implementations. Even though the performance of the ordering based RO-PUFs have been analyzed in detail, effects of aging have not been studied before. In this work, we present the results of an accelerated aging test applied to analyze the effects of aging on ROs. Then, the effects of aging on ordering based RO-PUFs are examined. Finally, a compensation method to protect the 100% robustness claim of the PUF structure is proposed and its influence on the circuit performance is presented. HighlightsResults of an accelerated aging test applied on ROs are presented.The effects of aging on ordering based RO-PUFs are examined.A compensation method to protect the 100% robustness of the PUF structure is proposed.

[EN] A method for the implementation of the atan2 operator based on the coordinate rotation digital computer algorithm is described. In the proposal, the computation of the z-path takes advantage of the look-up table-based FPGA resources to reduce by between 17 and 25%, without performance deterioration, the overall area of the unrolled architecture., This work was funded by the Spanish Ministerio de Economia y Competitividad and FEDER under the grant TEC2015-70858-C2-2-R.

In this paper, three eSTREAM Portfolio 2 ciphers: Grain v1, Mickey 2.0 and Trivium, and two Grain-like stream ciphers: Lizard and Plantlet are implemented in three versions aimed at different hardware application purposes. The hardware platform adopts Xilinx’s Spartan7 serial, and the simulations, syntheses and implementations are conducted in Vivado using the Verilog hardware design language. These implementations are compared with each other and those presented in existing literature in terms of performance metrics including: throughput, area consumption and throughput-area ratio. The basic version of Trivium achieves the highest frequency reaching a maximum of 416 Mbps and the serial version consumes the smallest area of 13 slices. In the parallel version, the maximum throughput-area ratio is 165.5 Mbps/Slice achieved by Trivium. At the same time, the basic version of the Mickey 2.0 algorithm achieved the second highest frequency of 384 Mbps, and the serial version of the Grain v1 algorithm achieved the second smallest area with 26 slices.

Authenticated ciphers potentially provide resource savings and security improvements over the joint use of secret-key ciphers and message authentication codes. The CAESAR competition aims to choose the most suitable authenticated ciphers for several categories of applications, including a lightweight use case, for which the primary criteria are performance in resource-constrained devices, and ease of protection against side channel attacks (SCA). In March 2018, two of the candidates from this category, ACORN and Ascon, were selected as CAESAR contest finalists. In this research, we compare two SCA-resistant FPGA implementations of ACORN and Ascon, where one set of implementations has area consumption nearly equivalent to the defacto standard AES-GCM, and the other set has throughput (TP) close to that of AES-GCM. The results show that protected implementations of ACORN and Ascon, with area consumption less than but close to AES-GCM, have 23.3 and 2.5 times, respectively, the TP of AES-GCM. Likewise, implementations of ACORN and Ascon with TP greater than but close to AES-GCM, consume 18% and 74% of the area, respectively, of AES-GCM.

This paper explores error-correcting codes for fuzzy extractor applications with Physical Unclonable Functions. We investigate BCH codes and compare them to convolutional codes using criteria of remaining entropy, probability of decoder failure, and hardware requirements. Parallel BCH coding is analyzed with a comprehensive search performed to find the smallest BCH code which satisfies the criteria in a parallel design to produce 128, 192, and 256-bit keys. A convolutional code is selected for comparison against the BCH codes found in this analysis. Application of the selected codes to a fuzzy extractor design is analyzed. Hardware requirements for FPGA implementations of each code is compared, with a BCH decoder design implemented for Artix-7 and Spartan-6 FPGA families. We find that a (127, 22, 47) parallel BCH code or (2, 1, 12) convolutional code is capable of performing as well as a single large BCH code, while requiring fewer FPGA resources when block RAMs can be leveraged. The convolutional code additionally requires the least amount of PUF ID bits.

Deep neural networks (DNNs) have gained popularity for their state-of-the-art accuracy and relative ease of use. DNNs rely on a growing variety of matrix multiply operations (i.e., dense to sparse, FP32 to N-bit). We propose an OpenCL-based matrix multiply design template, which enables automated design exploration to generate optimized FPGA matrix accelerators for DNN applications. Given the desired matrix operations (e.g., sparsity, data types), our template rapidly produces performance and area estimates for a variety of design variants and/or FPGA platforms. Upon identifying compelling design points and target platforms, FPGA implementations can then be generated automatically using the Intel® OpenCL™ FPGA SDK. We show the effectiveness of the template with a comparison to hand-tuned RTL, a design space exploration, and a DNN case study.

Hardware applications in an industrial context often have tight area, latency and throughput requirements or a specific combination thereof. This paper presents a method to improve area and throughput figures for folded circuits generated during a model-based hardware design process. The method targets FPGA implementations and is based on the automatic combination of isomorphic subgraphs and the detailed consideration of pipelined primitive operations for folding core scheduling. In the course of a design space exploration, the user is provided with fine-grain control over the area/throughput trade-off.

The growing trend toward heterogeneous platforms is crucial to meet time and power consumption constraints for high-performance computing applications. The OpenCL parallel programming language and framework enable programming CPU, GPU and recently FPGAs using the same source code. This eases software developers to implement applications on various devices supported by heterogeneous HPC platforms. This work presents two very different FPGA implementations of a database join operation, one using a direct O(n2) algorithm, and the other using a bitonic sort network to speed up the join operation. Comparison of performance and energy consumption for both FPGA and GPUs is provided which suggests a 40% performance/watt improvement by using an FPGA instead of a GPU.

Physical Unclonable Functions (PUFs) have gained a lot of research attention in recent years resulting in many different PUF proposals. Several of these proposals were aimed specifically at FPGA implementations. However, often these PUFs are evaluated and implemented for different (and often old) FPGA families with different metrics. Missing implementation details in many papers further hamper a fair analysis, as small details such as the exact routing can have significant impact on the PUF performance. In this paper we aim to overcome these problems by providing a fair comparison of some of the most promising Weak PUFs for FPGAs, the classic Ring Oscillator PUF (RO PUF), the Loop PUF and the TERO PUF. Each PUF is implemented with the same area optimizations and careful manual routing for modern Xilinx Artix-7 FPGAs and several implementation options are discussed. We measure the reliability and uniqueness of the PUF constructs on 100 BASYS-3 boards for a temperature range of −22°C to 44°C and use a glitch-generating core to analyze the vulnerability of the PUF constructs to surrounding logic. Our results show that the RO PUF has the best reliability in the presence of temperature variations while TERO has the best uniqueness of the three considered PUFs. Interestingly, the TERO PUF also shows the highest resistance to surrounding logic. To encourage further research in FPGA PUFs and to enable a fair comparison to future work the implementations as well as the measurement data will be made publicly available.

In this paper, we revisit lightweight FPGA implementations for SHA-3 and improve upon the state of the art by applying a new optimization technique to the slice-oriented architecture, which is based on a shallow pipeline. As a result, the area for the implementation reduces by almost one quarter (23%), compared to the up to now smallest implementation for Virtex-5 FPGAs. The proposed design also improves on the throughput-area ratio by 59%. For Virtex-6 FPGAs, the improvements are even higher, showing a throughput-area ratio increase by over 150% upon previously reported results for this FPGA. Furthermore, we evaluate several additional implementation trade-offs. First, we provide the maximum number of pipeline stages for lightweight architectures, which process several slices in parallel and for variants of SHA-3 with only 800 and 400 bits of internal state. Second, we evaluate several hardware interfaces. This evaluation shows, that the hardware interface may have a significant impact on the area consumption and the throughput.

In this paper, we propose a very large scale integration design method for a large-scale multiple-input multiple-output detection algorithm. Our design uses a modified version of the Successive Over Relaxation (SOR) method, which substantially reduces the highly computational complexity of data detection and achieves the near-optimal performance. We use a reconfigurable Processing Elements Array (PEA) to compute matrix-vector or matrix-matrix in SOR Method, which reduces the complexity of linear data detection. Then we implement our design on Xilinx Virtex-7 FPGA and the experimental results show that SOR method has a superior performance over conventional methods.

In this work, an architecture of low complexity non-linear Decision Feedback Equalizers is proposed, where the parallel filters of the feed-forward section are hardware-efficient structures based on Iterated Short Convolution. For the design of the parallel filters an algorithm is proposed, which provides an architecture with regularity that is more suitable for FPGA implementation. The proposed architecture achieves the typical throughput of 10 Gb/s, while its balanced design allows the implementation on smaller FPGA devices while reaching the target throughput.

Sub-pixel interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC sub-pixel (half-pixel and quarter-pixel) interpolation algorithm using a HLS tool in the literature is proposed. The proposed HEVC sub-pixel interpolation hardware is implemented on Xilinx FPGAs using Xilinx Vivado HLS tool. It, in the worst case, can process 45 quad full HD (3840×2160) video frames per second. Using HLS tool significantly reduced the FPGA development time. Therefore, HLS tools can be used for FPGA implementation of HEVC video encoder.

Date of Conference: 12-14 April 2016 Conference name: 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem is fatal to application-specific Network-on-Chip (NoC) designs as well if they cannot tolerate such failures. One solution to this problem can be having alternative routing options on the network for each communicating pair. In this study, we present an FPGA implementation of such a method for application-specific NoCs. This method adds additional network resources to the non-fault-tolerant design in an attempt to make it fault-tolerant. We show the effects of the presented fault-tolerant method on an FPGA implementation of Mp3 encoder based on energy consumption and area increase against non-fault-tolerant case. © 2016 IEEE.

The process to locate objects in an image passes through different phases. At the forefront of these phases, and most importantly, is the edge detection. If edges in an image are identified accurately, all of the objects will be located correctly for further processing phases. Noisy images contain high-frequency contents which might be interfered with image edges that makes edge detection more difficult. In this paper, a software comparative analysis of the performance of three different edge detectors, namely, Roberts, Prewitt and Sobel, is presented. The comparative analysis is performed to check the performance robustness of the edge detectors when noise level fluctuates in the image. In addition, an embedded hardware (HW) system is developed to implement the three detectors on the Zedboard FPGA prototyping board. The purpose of this implementation is to have an embedded system for on-the-move applications where portability is desired. To exploit the new features of the Xilinx Zynq-7000 series, we partition the implementation into (1) hardware part (running on logic gates of FPGA) and (2) software (SW) part (running on ARM processor of FPGA). This heterogeneous HW/SW implementation allows for high accurate results with high speed and efficient area. Furthermore, a hardware comparative analysis of the speed and area of the detectors is presented. The evaluation is performed by using different images (with their ground truths) downloaded from the BSDS500 dataset. The tools used for FPGA implementation are MATLAB and Microsoft Visual Studio (as software tools), Vivado High-level synthesis (HLS) and Software Development Kit (SDK) (as hardware tools). The experimental results show that the Roberts detector achieves better edge detection when the noise level is higher than 40%. It is also faster and requires less capacity of logic gates among the other detectors employed in this study.

\(\mathtt{PHOTON} \) is a lightweight hash function which was proposed by Guo et al. in CRYPTO 2011. This is used in low-resource ubiquitous computing devices such as RFID tags, wireless sensor nodes, smart cards and mobile devices. \(\mathtt{PHOTON} \) is built using sponge construction and it provides a new \(\mathtt{MAC} \) function called \(\mathtt{MAC}-\mathtt{PHOTON} \). This paper deals with FPGA implementations of \(\mathtt{MAC}-\mathtt{PHOTON} \) and their side-channel attack (SCA) resistance. First, we describe three architectures of the \(\mathtt{MAC}-\mathtt{PHOTON} \) based on the concepts of iterative, folding and unrolling, and we provide their performance results on the Xilinx Virtex-5 FPGAs. Second, we analyse security of the \(\mathtt{MAC}-\mathtt{PHOTON} \) against side-channel attack using a SASEBO-GII development board. Finally, we present an analysis of its Threshold Implementation (TI) and discuss its resistance against first-order power analysis attacks.

We present a new high speed cycle-approximate simulator, addressing an important, neglected category of multi-core systems: deeply-embedded cache-incoherent MPSoCs. We take advantage of the unique properties of these systems to increase the parallelism of the simulation. In doing so we achieve performance not possible using previous simulation techniques, without compromising the accuracy of the results. We present quantitative performance results across a large range of simulated NoC designs, comprising 1 to 64 cores. On average we simulate at 5.9 MIPS, with simulation speeds reaching 373 MIPS in the best case. Comparing against FPGA implementations we demonstrate that the simulator manages this with an average timing error of only 2.1%.

This paper proposes a novel hardware compilation approach targeting dataflow designs. This approach is based on aspect-oriented programming to decouple design development from design optimisation, thus improving portability and developer productivity while enabling automated exploration of design trade-offs to enhance performance. We introduce FAST, a language for specifying dataflow designs that supports our approach. Optimisation strategies for the generated designs are specified in FAST, making use of facilities in the domain-specific aspect-oriented language, LARA. Our approach is demonstrated by implementing various seismic imaging designs for ReverseTime Migration (RTM), which have performance comparable to state-of-the-art FPGA implementations while being produced with improved developer productivity.

The original publication is available at www.springerlink.com; International audience; In this paper, we present an efficient FPGA implementation of the SHA-3 hash function candidate Shabal. Targeted at the recent Xilinx Virtex-5 FPGA family, our design achieves a relatively high throughput of 2 Gbit/s at a cost of only 153 slices, yielding a throughput-vs.-area ratio of 13.4 Mbit/s per slice. Our work can also be ported to Xilinx Spartan-3 FPGAs, on which it supports a throughput of 800 Mbit/s for only 499 slices, or equivalently 1.6 Mbit/s per slice. According to the SHA-3 Zoo website, this work is among the smallest reported FPGA implementations of SHA-3 candidates, and ranks first in terms of throughput per area.

This paper presents small FPGA implementations of low precision polynomial approximations of functions without multipliers. Our method uses degree-$2$ or degree-$3$ polynomial approximations with at most $3$-bit coefficients and low precision estimations of the powers of $x$. Here, we denote by $3$-bit coefficients values with at most $3$ non-zero and possibly non-contiguous signed bits (e.g. $1.001000\overline1$). This leads to very small operators by replacing the costly multipliers by a small number of additions. Our method provides approximations with very low average error and is suitable for signal processing applications.