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Low-loss reverse-conducting normally- OFF double-channel AlGaN/GaN power transistor with the built-in Schottky barrier diode (SBD) has been systematically studied. This device features the MOS-gate section and SBD-anode section paralleled to an interdigital layout along the gate width direction. A common access region that conducts current at both forward and reverse ON-states is employed, which is beneficial to reduce the conduction loss. With a MOS-HEMT/SBD finger width of ${4}~\mu \text{m}/2~\mu \text{m}$ and a total width ratio of 2:1, the device exhibits a threshold voltage of +0.8 V at a drain current of ${10}~\mu \text{A}$ /mm and a low forward ON-resistance of $12.1~\Omega \cdot \text {mm}$. The Schottky metal contacts 2-DEG directly, which results in a low reverse turn-on voltage of −0.6 V (at −1 mA/mm) and low reverse ON-state voltage of −1.7 V (at −50 mA/mm). A leakage suppression MOS field plate (FP) is applied to shield the Schottky contact from the strong electric field, leading to a low OFF-state leakage current of 14 nA/mm at +100-V drain bias and a high breakdown voltage (BV) of +698 V. The finger width and the number of fingers should be optimized. A narrow finger width benefits the current sharing at the access region, while the increasing number of fingers introduces more Schottky depletion regions along the gate width direction that degrade ${R}_{ \mathrm{\scriptscriptstyle ON}}$. [ABSTRACT FROM AUTHOR]

An MOS field plate-protected Schottky-drain (gated Schottky-drain) is successfully integrated on a double-channel AlGaN/GaN MOS-HEMT to provide reverse blocking capability. The leakage suppression MOS field plate is deployed on the etched upper GaN channel layer after a barrier fully recess process, leading to a low reverse OFF-state leakage current of −20 nA/mm (at −100 V). The drain metal is deployed adjacent to the MOS field plate, contacting the upper MOS-channel and lower heterojunction channel from the sidewall. A metal-2DEG Schottky contact with a low turn-ON voltage of 0.5 V is achieved. Since the lower channel (below the MOS field plate) is separated from the etched surface of upper GaN channel layer, a high-conductivity MOS-gated channel with a sheet resistance of 806 $\Omega$ /Square is obtained. The device exhibits a threshold voltage of +0.6 V (at $10~\mu \text{A}$ /mm and +1.9 V from linear extrapolation) and an ON-resistance of ~18 $\Omega {\cdot} \text {mm}$. Besides, a high forward (and reverse) breakdown voltage of 790 V (and −656 V, all at $10~\mu \text{A}$ /mm) is achieved. [ABSTRACT FROM AUTHOR]

An AlGaN/GaN double-channel Schottky barrier diode (DC-SBD) with dual-recess gated anode is demonstrated in this letter. The DC-SBD features two recess steps. The deep one cuts through two channels, and the anode metal contacts 2DEG directly from the sidewall of the recessed heterostructure. The shallow one terminates at the upper channel layer and is located adjacent to the Schottky contact. A MOS field plate is placed on the shallow recess region to pinchoff the underlying channels, so the off-state leakage current of the DC-SBD can be suppressed. Since the lower channel is separated from the etched surface, the field-effect mobility beneath this MOS structure shows a high peak value of 1707 cm2/( \text V\cdot \text s ). The DC-SBD with an anode-to-cathode length ( L\text {ac} ) of 15~\mu \textm exhibits a turn-on voltage ( V\text {T} ) of ~0.6 V (at 1 mA/mm), a leakage current of 7.8 nA/mm (at −100 V), and a breakdown voltage of 704 V (at 1~\mu \textA /mm). The double-channel design also allows both the deep and shallow recesses to be terminated at GaN layers that results in high uniformity of V\text {T} . [ABSTRACT FROM PUBLISHER]

The switching behavior of on-chip photon sources, i.e., the p-doping-free Schottky-on-heterojunction light-emitting diodes (SoH-LEDs), which can be seamlessly integrated into the AlGaN/GaN-on-Si power high electron mobility transistors platform is investigated. It is demonstrated that the electroluminescence (EL) from an interdigital SoH-LED can be switched at least up to 10 MHz, fulfilling the requirement of most power switching circuits. In order to evaluate the EL switching limit of SoH-LEDs, a quantitative analysis of the dependence of junction current on operating frequency at different dc biases is performed based on S-parameter characteristics. At a criterion of junction-current/input-current to 50%, the cutoff frequency of an interdigital SoH-LED is obtained to be 210 MHz at a forward bias of 4 V. This letter proves that the SoH-LED is adequately fast for being employed as an on-chip synchronous photon source in GaN power switching applications. [ABSTRACT FROM PUBLISHER]

Very fast transients of V {\text {TH}} shift and their impact on R\mathrm{\scriptscriptstyle ON} under dynamic AC (1 k–1 MHz) positive gate stress in depletion-mode (D-mode) metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) are revealed. We achieve data acquisition within 120 ns right after each stress pulse throughout the entire stress time range from 10^ -7 up to 10^ 3 s, by virtue of a short stress-to-sense delay of \sim 100 ns and high sampling rate up to 50 MSa/s. Despite the considerable V_{\mathrm {\mathbf {TH}}} shift, its impact on R\mathrm{\scriptscriptstyle ON} in D-mode MIS-HEMT is modest, if the device is under sufficient gate overdrive. Furthermore, V_{\mathrm {\mathbf {TH}}}$ shift and the consequent R\mathrm{\scriptscriptstyle ON} increase under dynamic stress, which are more relevant to high-frequency switching operation, exhibits frequency dependence within 1 k–1 MHz and is always smaller than that under conventionally used static (constant) stress. [ABSTRACT FROM PUBLISHER]

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level $E1$ with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while $E2$ with an activation energy of 0.22 eV is located in the buffer layer. [ABSTRACT FROM AUTHOR]

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth. [ABSTRACT FROM AUTHOR]

We investigate in detail the influence of AlN passivation on dynamic ON-resistance ( \(R_{\mathrm{{\scriptstyle ON}}}\) ) and electric field ( \(E\) -field) distribution in high-voltage AlGaN/GaN high electron mobility transistors (HEMTs) on a Si substrate based on pulsed \(I\) – \(V\) measurements, electroluminescence (EL) microscopy, and 2-D physics-based numerical device simulations. It is found that the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) increase has been significantly suppressed to below 10% at various temperatures ranging from −50 to 200 °C owing to the effective and robust compensation of deep acceptor-like trap states at the AlN/GaN (passivation/cap) interface by the additional positive polarization charges induced in the epitaxial AlN thin passivation layer grown in a plasma-enhanced atomic layer deposition system. To the best of our knowledge, this is the first time that highly suppressed current collapse in an AlGaN/GaN HEMT on a Si substrate within a wide temperature range is ever reported. By monitoring the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) for 100 consecutive 133-kHz switching cycles, its variation is observed to be less than 2.5%, indicating excellent stability of the passivation effectiveness. The electric field in an AlN-passivated device is found to be well confined at the drain-side gate edge, as shown in EL measurement and numerical simulation results. This phenomenon directly suggests that the virtual gate effect arising from surface trap charging has been effectively alleviated by the AlN passivation technique. [ABSTRACT FROM AUTHOR]

In this paper, we report the device performance of a high-voltage normally off Al2O3/GaN MOSFET on the Si substrate. Normally off operation is obtained by multiple cycles of O2 plasma oxidation and wet oxide-removal gate recess process. The recessed normally off GaN MOSFET with 3 \mum gate-drain distance exhibits a maximum drain current of 585 mA/mm at 9 V gate bias. The threshold voltage of the MOSFET is 2.8 V with a standard derivation of 0.2 V on the sample with an area of 2 \,\times\, 2 {\rm cm}^{2} . The gate leakage current is below 10^{-6}~{\rm mA}/{\rm mm} during the whole gate swing up to 9 V and the I{\scriptstyleON}/I{\scriptstyle OFF} ratio is larger than 10^{9} , indicating the good quality of Al2O3 gate insulator. The MOSFET with 10 \mum gate-drain distance shows a three terminal OFF-state breakdown voltage (BV) of 967 V at zero gate-source bias with a drain leakage current criterion of 1 \muA/mm . The specific ON-resistance $(R_{{{\scriptstyle {\rm ON}}},{\rm SP}}) of the device is 1.6 m\Omega\,\cdot\,cm^2 and the power figure of merit (BV^2/R{{\scriptstyle ON},SP}) is 584 MW/cm^2 . [ABSTRACT FROM AUTHOR]

The threshold voltage ( VT) instability of metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) is investigated. In the enhancement-mode AlGaN/GaN MIS-HEMT fabricated by fluorine plasma implantation technique featuring Al2O3 gate dielectric, a hysteresis of 0.6 V in transfer characteristics is observed by quasi-static I - V (current-voltage) measurement, in which the gate bias is swept at a low rate (0.7 V/s). Pulsed transfer characteristics measurement, however, unveils much larger hysteresis under the same gate voltage swing. The VT-instability is attributed to the traps located at the dielectric/III-nitride interface as well as in the bulk of gate dielectric. It is proposed that pulsed measurement can count for the effect of fast traps (shallow traps) while the quasi-static measurement can only reflect slow traps (deep traps), and is more accurate for VT-instability evaluation. In addition, the existence of bulk traps is implied by a slow time-dependent shift of VT under large gate bias. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Improvement of the AlGaN/GaN high-electron mobility transistor's (HEMT's) off -state breakdown voltage is achieved by implanting ^19\F^+ ions at an energy of 50 keV and dose of \1 \times \10^12\ \cm^-2 under the gate region using \BF3 as the source. The charge state of the implanted fluorine ions changes from positive to negative in the AlGaN/GaN structure because of fluorine's strong electronegativity. The negative-charged fluorine ions at the back side of the two-dimensional electron gas can raise the energy barrier of the GaN buffer layer under the channel, effectively blocking the current injected from the source to the high-field region of the GaN channel when the HEMT is biased at off-state. The source-injected electrons, if not blocked, could flow to the high-field region and initiate a premature three-terminal off-state breakdown in a conventional AlGaN/GaN HEMT. A 38% improvement of the three-terminal off-state breakdown voltage and 40% improvement of the power figure-of-merit VBD-off^2/Ron are achieved in the enhanced back barrier HEMT. [ABSTRACT FROM AUTHOR]

The ON-resistance and its temperature dependence of the high electron mobility transistor (HEMT)-compatible lateral field-effect rectifier (L-FER) are investigated. Three types of transfer length method (TLM) patterns are utilized to extract the temperature-dependent electrical parameters of the resistance model. The technique presented in this paper delivers a direct and simple methodology for the investigation of the temperature dependence of the ON-resistance in the L-FER. The simulated output characteristics of the L-FER are in good agreement with the experimental results. [ABSTRACT FROM AUTHOR]

AlGaN/GaN high-electron mobility transistor's (HEMT's) off-state breakdown is investigated using drain-current injection techniques with different injection current levels. Competitions between the source leakage and gate leakage, pure leakage and impact ionization, and source- and gate-injection-induced impact ionization during the drain-injection measurement are discussed in detail. It was found that the breakdown originates from the source/gate leakage at low drain injection levels but is dominated by source/gate-induced impact ionization process at high drain injection currents. The source-induced impact ionization usually precedes the gate-induced impact ionization in low-gate leakage devices, resulting in a premature three-terminal off-state breakdown. We also found that the gate-bias value affects the breakdown voltage in the conventional three-terminal off-state breakdown I-V measurement and should be carefully considered. [ABSTRACT FROM AUTHOR]

This letter reports a GaN high-electron mobility transistor (HEMT) with reduced current collapse using a multicycle combined plasma-free ozone oxidation and wet surface treatment before Si3N4 passivation. The surface oxide and decomposed layers could be effectively removed and a perfect AlGaN surface is obtained after the treatment. Pulsed $IV$ and RF power measurement indicate that the current collapse is greatly suppressed due to the removal of imperfect surface layer and damage free nature, providing an effective surface treatment method to improve the effect of passivation in GaN HEMT. [ABSTRACT FROM AUTHOR]

Al2O3/AlGaN/GaN enhancement-mode metal-isolator-semiconductor high-electron-mobility transistor (MIS-HEMT) featuring a partially recessed (Al) GaN barrier was realized by a fluorine plasma implantation/etch technique. By properly adjusting the RF power driving the fluorine plasma, the fluorine plasma is able to produce two desirable results: 1) a well-controlled slow dry etching for gate recess and 2) implanting fluorine ions into the AlGaN barrier. The fluorine ions become negatively charged in the barrier layer and induce a positive shift in the threshold voltage. The proposed MIS-HEMT exhibits a threshold voltage ( V\mathrm {\mathbf {TH}}) of +0.6 V at a drain current of 10~\mu \textA /mm, a maximum drive current of 730 mA/mm, an ON-resistance of 7.07~\Omega \,\cdot \, mm, and an OFF-state breakdown voltage of 703 V at an OFF-state drain leakage current of 1~\mu \text{A} /mm. From room temperature to 200 °C, the device exhibits a small negative shift of V_{\mathrm {\mathbf {TH}}}$ ( $\sim 0.5$ V) that is attributed to the high-quality dielectric/F-implanted-(Al) GaN interface and the partially recessed barrier. [ABSTRACT FROM AUTHOR]

In this letter, 600-V normally-OFF SiNx/AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) is reported. Normally-OFF operation and low OFF-state gate leakage are obtained by using fluorine plasma ion implantation in conjunction with the adoption of a 17-nm SiNx thin film grown by plasma-enhanced chemical vapor deposition as the gate insulator. The normally-OFF MIS-HEMT exhibits a threshold voltage of +3.6~V, a drive current of 430 mA/mm at a gate bias of 14 V, a specific ON-resistance of 2.1 m\Omega\cdotcm^2 and an OFF-state breakdown voltage of 604 V at a drain leakage current of 1 \muA/mm with VGS=0~\rm V, and the substrate grounded. Effective current collapse suppression is obtained by AlN/SiNx passivation as proved by high-speed pulsed I\--V and low-speed high-voltage switching measurement results. [ABSTRACT FROM AUTHOR]

This letter reports a normally-OFF Al2O3/GaN gate-recessed MOSFET using a low-damage digital recess technique featuring multiple cycles of plasma oxidation and wet oxide removal process. The wet etching process eliminates the damage induced by plasma bombardment induced in conventional inductively coupled plasma dry etching process so that good surface morphology and high interface quality could be achieved. The fully recessed Al2O3/GaN MOSFET delivers true enhancement-mode operation with a threshold voltage of +1.7~V. The maximum output current density is 528 mA/mm at a positive gate bias of 8 V. A peak field-effect mobility of 251 cm^2/V\cdots is obtained, indicating high-quality Al2O3/GaN interface. [ABSTRACT FROM AUTHOR]

An effective passivation technique that yields low off-state leakage and low current collapse simultaneously in high-voltage (600-V) AlGaN/GaN high-electron-mobility transistors (HEMTs) is reported in this letter. The passivation structure consists of an AlN/\SiNx stack with 4-nm AlN deposited by plasma-enhanced atomic layer deposition and 50-nm \SiNx deposited by PECVD. The AlN/ \SiNx-passivated HEMTs with a gate–drain distance of 15 \mu\m exhibit a high maximum drain current of 900 mA/mm, a low off-state current of 0.7 \mu\A/mm at VDS = \600\ \V, and a steep subthreshold slope of 63 mV/dec. Compared with the static on-resistance of 1.3 \m\Omega \cdot \cm^2, the dynamic on-resistance after high off-state drain bias stress at 650 V only increases to 2.1 \m\Omega \cdot \cm^2. A high breakdown voltage of 632 V is achieved at a drain leakage current of 1 \mu\A/mm . [ABSTRACT FROM PUBLISHER]

Kink effects are studied in conventional AlGaN/GaN high-electron-mobility transistors by measuring their current-voltage characteristics with various bias sweeping conditions at drain and gate terminals. It is found that the kink effect is induced by drain and gate pumping. The magnitude of kink is directly related to the maximum drain voltage and current levels during on-state operation. The hot electrons in the 2-D electron gas channel generated under high drain bias could be injected into the adjacent epitaxial buffer layer where they can be captured by donor-like traps. Hot electron trapping and the subsequent field-assisted de-trapping is suggested to be the dominant mechanism of kink generation in the studied device. The extracted activation energy of the traps accounting for the kink effect is 589 \pm 67 meV from temperature-dependent transient measurement, and is close to the energy of the E2 trap widely reported in GaN layers. [ABSTRACT FROM AUTHOR]

Enhancement-mode (E-mode) AlGaN/GaN heterojunction field effect transistors (HFETs) with a nominal gate length of 0.35 \mu\m are fabricated on a SiC substrate by fluorine plasma ion implantation without the use of gate recess. The threshold voltage is measured to be +0.2 V by linear extrapolation from the transfer characteristics. The E-mode device exhibits a saturation drain current density of 735 mA/mm at a gate bias of 4 V, a peak transconductance of 269 mS/mm, a current-gain cutoff frequency (fT) of 39 GHz, and a maximum oscillation frequency (f\max) of 91 GHz. At 18 GHz, the fabricated E-mode device exhibits a maximum output power density of 3.65 W/mm, a linear gain of 11.6 dB, and a peak power-added efficiency of 42%. This is the first report of the large-signal performance of AlGaN/GaN E-mode HFETs in the Ku-band. [ABSTRACT FROM AUTHOR]

Enhancement-mode Si3N4/AIGaN/GaN metal-insulator-semiconductor HFETs (MISHFETs) with a 1-µm gate footprint are demonstrated by combining CF4 plasma treatment technique and a two-step Si3N4 deposition process. The threshold voltage has been shifted from -4 [for depletion-mode HFET] to 2 V using the techniques. A 15-nm Si3N4 layer is inserted under the metal gate to provide additional isolation between the gate Schottky contact and AIGaN surface, which can lead to reduced gate leakage current and higher gate turn-on voltage. The two-step Si3N4 deposition process is developed to reduce the gate coupling capacitances in the source and drain access region, while assuring the plasma-treated gate region being fully covered by the gate electrode. The forward turn-on gate bias of the MISHFETs is as large as 7 V, at which a maximum current density of 420 mA/mm is obtained. The small-signal RF measurements show that the current gain cutoff frequency (fT) and power gain cutoff frequency (fmax) are 13.3 and 23.3 GHz, respectively. [ABSTRACT FROM AUTHOR]

We report broadband microwave noise characteristics of a high-linearity composite-channel HEMT (CC-HEMT). Owing to the novel composite-channel design, the CC-HEMT exhibits high gain and high linearity such as an output third-order intercept point (OIP3) of 33.2 dBm at 2 GHz. The CC-HEMT also exhibits excellent microwave noise performance. For 1-µm gate-length devices, a minimum noise figure (NFmin) of 0.7 dB and an associated gain (Ga) of 19 dB were observed at 1 GHz, and an (NFmi) of 3.3 dB and a Ga of 10.8 dB were observed at 10 GHz. The dependence of the noise characteristics on the physical design parameters, such as the gate-source and gate-drain spacing, is also presented. [ABSTRACT FROM AUTHOR]

We report a novel approach in fabricating high-performance enhancement mode (E-mode) AlGaN/GaN HEMTs. The fabrication technique is based on fluoride-based plasma treatment of the gate region in AlGaN/GaN HEMTs and post-gate rapid thermal annealing with an annealing temperature lower than 500 °C. Starting with a conventional depletion-mode HEMT sample, we found that fluoride-based plasma treatment can effectively shift the threshold voltage from -4.0 to 0.9 V. Most importantly, a zero transconductance (gin) was obtained at Vgs = 0 V, demonstrating for the first time true E-mode operation in an AlGaN/GaN HEMT. At Vgs = 0 V, the off-state drain leakage current is 28 μA/mm at a drain-source bias of 6 V. The fabricated E-mode AlGaN/GaN HEMTs with 1 μm-long gate exhibit a maximum drain current density of 310 mA/mm, a peak gm, of 148 mS/mm, a current gain cutoff frequency fT of 10.1 GHz and a maximum oscillation frequency fmax of 34.3 GHz. [ABSTRACT FROM AUTHOR]

We report the characterization of quality (Q) -factor of RF metal-semiconductor-metal (MSM) planar interdigitated varactors fabricated by standard AlGaN/GaN HEMT process. The MSM varactors have wide tuning range and exhibit high quality-factor at both the maximum and minimum capacitance values. The fundamental limitation of the Q-factor in the medium capacitance range is also revealed. The elimination of ohmic contact resistance in the MSM varactor configuration pushed up the peak Q-factor to 92 at 0.5 GHz and 41 at 1.1 GHz. The operation of the MSM varactor is modeled by a physical equivalent circuit, with which the dependence of the Q-factor over the entire tuning voltage range can be explained. [ABSTRACT FROM AUTHOR]

Abstract: We report detailed results on the temperature dependence and thermal stability of the planar-integrated enhancement/depletion-mode (E/D-mode) AlGaN/GaN high-electron mobility transistors (HEMTs). Compared to the standard mesa etching technique, the plasma treatment can achieve the same device isolation results. The E/D-mode HEMTs and the corresponding digital integrated circuits fabricated by the planar process exhibit stable operation from room temperature up to 350°C. No degradation in device performance was observed after a 140-h thermal stress at 350°C, implying excellent thermal stability of the planar process. The direct-coupled FET logic inverter, realized by planar-integration of E/D-mode HEMTs, presents larger noise margins (NMS) at high temperatures than the previously reported work, demonstrating promising potential for GaN-based high-temperature digital ICs. The NM improvement can be attributed to the higher threshold voltage and the improved gate turn-on voltage of the E-mode HEMTs that is achieved with larger plasma treatment dose. [Copyright &y& Elsevier]