Search

In this work, we demonstrate enhancement-mode regrown p-GaN gate devices with high threshold voltage as well as a robust forward time-dependent gate breakdown (TDGB) stability. The regrown p-GaN gate HEMTs are fabricated with two different AlGaN barriers. Devices with 16nm Al0.235 Ga0.765 N yield a $\text{V}_{\text {TH}}$ of 1.5V and a high threshold voltage ($\text{V}_{\text {TH}}$) of 2.7V is observed for 7nm AlGaN along with a gate breakdown voltage of more than 10V. Lastly, the regrown p-GaN gate HEMTs with 7nm AlGaN barrier demonstrate an operating $\text{V}_{\text {G}}$ of 7.46V and 7V for 1% failure rate of 10-year lifetime at 150°C and 25°C, which is amongst the highest values compared to the reported literature for regrown p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

The mapping of the current induced by a focused electron beam in a scanning electron microscope (SEM) has been used to localize electrically stressed regions in the AlGaN/GaN-on-Si Schottky barrier diode (SBD) structures cross-sectioned by the focused ion beam (FIB) technique. We have shown that homogeneously distributed electron beam induced current (EBIC) intensity detected below the Schottky contact at 0 V changes with increasing reverse voltage VR and peaks at the edges of a field-plate region. The build-up of local microavalanches at high electric voltages has been indicated by overexposed EBIC signal at areas following the edges of the field plate structure. Interpretation of EBIC measurements is supported by electro-physical modeling and simulations employing the 2-D finite element method in Synopsys TCAD Sentaurus. The simulations prove that the electric field intensity in the SBD locally reaches values sufficiently high to trigger multiplication of the excessive carriers generated by an electron beam, which helps one to visualize and localize critical regions in GaN-based power electronic devices by the EBIC method. [ABSTRACT FROM AUTHOR]

In this letter, we present an analysis of the threshold voltage shift induced by positive bias temperature instability stress in GaN-based power HEMTs with p-type gate, controlled by a Schottky metal/p-GaN junction. In particular, we show the positive effect of the magnesium compensation process in the p-GaN layer on the long-term threshold voltage instability. When a relatively high positive bias is applied to the gate (Schottky junction reverse-biased), holes are generated by impact ionization in the high-field depleted p-GaN region, then accelerated toward the AlGaN layer. The high-energy holes, combined with the high temperature effects, create defects in the AlGaN or at its interface with p-GaN, causing a long-term positive threshold voltage shift. A process variation in the p-GaN layer is introduced which promotes a wider depletion region near the Schottky interface with the metal, lowering the electric field and reducing the generation of holes due to impact ionization. As a result, the long-term threshold voltage instability is improved without altering the dc transistor parameters, such as threshold voltage, trans-conductance, and subthreshold slope. [ABSTRACT FROM AUTHOR]

This paper analyses the influence of the GaN and Si3N4 passivation (or “cap”) layer on the top of the AlGaN barrier layer on the performance and reliability of Schottky barrier diodes with a gated edge termination (GET-SBDs). Both GaN cap and Si3N4 cap devices show similar dc characteristics but a higher density of traps at the SiO2/GaN interface or/and an increase of the total dielectric constant in the access region result in higher $R_{\mathrm{ON}}$ -dispersion in GaN cap devices. The leakage current at medium/low temperatures in both types of devices shows two low-voltage-independent activation energies, suggesting thermionic and field-emission processes to be responsible for the conduction. Furthermore, a voltage-dependent activation energy in the high-temperature range occurs from low voltages in the GaN cap devices and limits their breakdown voltage (${V}_{\mathsf {BD}}$). Time-dependent dielectric breakdown measurements show a tighter distribution in Si3N4 cap devices (Weibull slope $\beta = {3.3}$) compared to GaN cap devices ($\beta = 1.8$). Additional measurements in plasma-enhanced atomic layer deposition (PEALD)-Si3N4 capacitors with different cap layers and TCAD simulations show an electric field distribution with a strong peak within the PEALD-Si3N4 dielectric at the GET corner, which could accelerate the formation of a percolation path and provoke the device breakdown in GaN cap SBDs even at low-stress voltages. [ABSTRACT FROM AUTHOR]

Enhanced leakage paths below Ti-/Al-based contacts to GaN-on-Si HEMTs have been identified and studied. Through a novel use of the quasi-static capacitance–voltage technique, the depth of these preferential leakage paths was determined to be $\sim 1.6~\mu \text{m}$ , extending down into the superlattice strain relief layer. Along these paths, the material resistivity was reduced by more than a factor of 100 compared to the uncontacted epitaxy. It is suggested that the cause of the additional leakage is decoration of dislocations. This result is important for understanding buffer transport, a critical parameter for breakdown, and buffer charge storage. [ABSTRACT FROM AUTHOR]

The backgating effect on trench-isolated enhancement-mode p-GaN devices fabricated on 200-mm GaN-on-SOI was investigated. We show that to minimize the backgating effect in the monolithically integrated half-bridge, the sources of both the low side and high side need to be connected to their respective fully isolated Si(111) device layers to keep the substrates and the sources at equipotential. [ABSTRACT FROM AUTHOR]

This paper focuses on the time-dependent breakdown of the AlGaN/GaN Schottky barrier diodes with a gated edge termination (GET) submitted to high-voltage stress. The impact of the GET structure, the passivation layer thickness, and a preclean process (sulfuric acid and hydrogen peroxide mixture + ammonia and hydrogen peroxide mixture) before the GET layer deposition on the time to breakdown ${t}_{\text {BD}}$ is analyzed. Initially, a reference structure with a single-GET structure, a thick passivation layer and excellent performance under dc, and pulse characterization is submitted to stress. The results show that the time to failure follows a Weibull distribution with high shape parameter values ( $\beta \sim \text {3}$ and/or $\beta \sim \text {5}$ ) related to intrinsic failure mechanisms. The exponential dependence of ${t}_{\text {BD}}$ on the stress voltage suggests a degradation driven by the electric field, while lower thermal activation energies indicate that temperature acts as a weak acceleration factor. A more uniform distribution of the electric field—by adding an additional peak (double-GET structure) or with more equilibrated peaks (thin passivation structure)—and a more aggressive preclean process before the GET layer deposition improves the breakdown voltage and prolongs the device lifetime. [ABSTRACT FROM AUTHOR]

Epitaxial AlGaN/GaN/AlGaN-on-Si high-electron mobility structures with and without carbon doping have been studied. By considering the donor density required to suppress a 2D hole gas in the undoped structure, we demonstrate that the $2 \times 10^{19}$ cm−3 substitutional carbon incorporated during metal-organic chemical vapor deposition must be a source of donors as well as acceptors, with a donor to acceptor ratio of at least 0.4. This compensation ratio was determined based on the comparison of substrate bias experiments with TCAD simulations. This value, which was previously unknown, is a key parameter in GaN power switching high- electron- mobility transistors, since it determines the resistivity of the layer used to suppress leakage and increase breakdown voltage. [ABSTRACT FROM AUTHOR]

An analytical model for the calculation of the threshold voltage for enhancement-mode (E-mode) p -(Al)GaN high-electron-mobility transistors (HEMTs) is presented. The ON-state behavior (at low output voltages) of both p -GaN HEMTs and p -AlGaN HEMTs—including the gate injection transistor—are discussed in detail, and closed expressions for the threshold voltage VT of both devices are deduced. It is found that the threshold voltage values for both devices are close to one another, and that there is an ideal upper limit when the p -type doping in the AlGaN gate is perfectly tailored, yielding more positive threshold voltages. This ideal case might be difficult to realize technologically, but can serve as a benchmark for the VT of p -(Al)GaN HEMTs. [ABSTRACT FROM PUBLISHER]

In this paper, we present an experimental analysis of the degradation induced by positive bias temperature instability stress in GaN-based power high electron mobility transistors with p-type gate, controlled by a Schottky metal/p-GaN junction. In particular, the role of the aluminum content (Al%) in the AlGaN barrier layer on the threshold voltage degradation is investigated by means of constant voltage stress measurements. This has been performed for different process conditions with varying Al content. Main results in this paper demonstrate that when a relatively large positive bias is applied on the gate, two competing trapping mechanisms take place in the AlGaN barrier layer or at the p-GaN/AlGaN interface causing V\text {TH} instability. First, an aluminum independent hole trapping mechanism, caused by elastic tunneling from p-GaN valence band (2-D hole gas), leads to a relatively short-time and recoverable negative V\text {TH} shift. In the second step, defect creation occurs. These additional defects are filled with electrons and cause a permanent or slowly recoverable positive V\text {TH} degradation. The amount of defect creation was dependent on the Al% in the barrier. [ABSTRACT FROM PUBLISHER]

In this letter, we analyzed the gate capacitance characteristics in p-GaN gate/AlGaN/GaN heterostructures by using a two-junction capacitor model. First, we have observed that the C – V behavior depends on the different processing conditions of the p-GaN gate. Second, a two-junction capacitor model considering a series connection of the Schottky metal/p-GaN junction capacitor and the AlGaN barrier capacitor is proposed to explain this C – V behavior. Based on this model, the junction capacitance has an influence on the total capacitance value under a high gate bias due to the Schottky metal/p-GaN junction. Furthermore, the Mg-concentration and hole density can be extracted. The extracted hole density is consistent with the results obtained by Hall measurements. [ABSTRACT FROM AUTHOR]

In this letter, we investigate the time-dependent breakdown mechanisms in edge terminated AlGaN/GaN lateral Schottky diodes under high-temperature reverse bias (HTRB) tests. Thanks to a combined experimental/simulation analysis, we ascribe the device failure to two distinct time-sequential breakdown mechanisms caused by a localized electric field peak at the edge termination corner. In particular, the combined effect of high electric field and temperature causes a first breakdown of the plasma-enhanced atomic layer deposition (PEALD)-Si3N4 followed by a second one in the AlGaN barrier. To validate this hypothesis, a 2-D TCAD simulator was used, and the breakdown path in Si3N4 was modeled by an inclusion of a narrow metal filament. The electrical simulations well reproduce the characteristics of the fresh and degraded GaN diodes. Finally, we demonstrate that the diode reliability under HTRB tests can be significantly improved by using a metalorganic chemical vapor deposition (MOCVD)-Si3N4 dielectric in the edge termination. This reliability improvement is related to a better material quality of MOCVD-Si3N4, showing a higher breakdown field compared with the PEALD-Si3N4. [ABSTRACT FROM PUBLISHER]

We are reporting the growth of AlGaN based enhancement-mode high electron mobility transistors (HEMTs) on 200 mm silicon (111) substrates using a single wafer metalorganic chemical vapor deposition reactor. It is found that TMAl pre-dosing conditions are critical in controlling the structural quality, surface morphology, and wafer bow of the HEMT stack. Optimal structural quality and pit-free surface are demonstrated for AlGaN HEMTs with pre-dosing temperature at 750°C. Intrinsically, carbon-doped AlGaN, is used as the current blocking layer in the HEMT structures. The lateral buffer breakdown and device breakdown characteristics, reach 400 V at a leakage current of 1 μA/mm measured at 150°C. The fabricated HEMT devices, with a Mg doped p-GaN gate layer, are operating in enhancement mode reaching a positive threshold voltage of 2-2.5 V, a low on-resistance of 10.5 Ω mm with a high drain saturation current of ~0.35 A/mm, and a low forward bias gate leakage current of 0.5 × 10 A/mm ( V = 7 V). Tight distribution of device parameters across the 200 mm wafers and over repeat process runs is observed. [ABSTRACT FROM AUTHOR]

In this paper, we present the results of a combined measurement/simulation analysis of the degradation induced by on-state stress in Au-free AlGaN/gallium-nitride-on-Si Schottky barrier diodes (SBDs). Turn-on voltage ( V\mathrm{ TON} ) and on-resistance ( R\mathrm{\scriptscriptstyle ON} ) are affected by charge carrier trapping/detrapping, occurring in different regions and caused by different mechanisms, when a high stress current is applied to the device. In particular, we have investigated the degradation of SBDs adopting different stress conditions and analyzing the influence of the diode geometry; consequently, we were able to identify the physical mechanisms responsible for long-term degradation of V\mathrm{ TON} and R\mathrm{\scriptscriptstyle ON} . In addition, thanks to this approach, a critical electric field for the R\mathrm{\scriptscriptstyle ON} degradation has been determined. [ABSTRACT FROM AUTHOR]

In this paper, we have extensively investigated the impact of anode recess on the reverse leakage current, forward voltage ( VF ), and dynamic characteristics of Au-free AlGaN/GaN Schottky barrier diodes with a gated edge termination (GET-SBDs) on 200-mm silicon substrates. By increasing the number of atomic layer etching (ALE) cycles for anode recessing, we have found that: 1) the reverse leakage current is strongly suppressed due to a better electrostatic control for pinching off the channel in the GET region; a median leakage current of \sim 1 nA/mm and an {I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}} ratio higher than 10^{8}$ have been achieved in GET-SBDs with six ALE cycles; 2) the forward voltage ( $\sim 1.3$ V) is almost independent of the ALE cycles, taking into account its statistical distribution across the wafers; 3) when the remaining AlGaN barrier starts to be very thin (in the case of six ALE cycles), a spread of the ON-resistance, mainly attributed to the GET region, can occur due to the difficult control of the remaining AlGaN thickness and surface quality; and 4) the dynamic forward voltage of GET-SBDs shows a mild dependence on the ALE process in pulsed $I$ – $V$ characterization, and a more ALE-dependent dynamic ON-resistance is observed. [ABSTRACT FROM AUTHOR]

In this paper, several experimental methods (electrical and optical) for channel temperature detection in AlGaN/GaN high-electron mobility transistors have been studied and experimentally benchmarked. This paper encompasses four electrical methods (two dc characterization methods, low-RF output conductance measurement, and gate-resistive sensing technique) and one optical method (micro-Raman spectroscopy), which have been frequently used to sense temperature in AlGaN/GaN transistors. The experiments are carried out on identical test structures on wafer-level conditions as well as on single dies mounted on printed circuit board for power densities up to 12 W/mm. Due to a large temperature distribution along the channel of the devices and due to the physics on which each method is based, it was shown that the differences between the measured temperatures using the different methods can be as high as 50%. Experimental results are discussed and compared with coupled TCAD and finite element modeling simulations, where significant agreements have been observed. [ABSTRACT FROM AUTHOR]

We investigate the DC and dynamic characteristics of AlGaN/GaN Schottky barrier diodes (SBDs) and the diodes with a gated edge termination (GET-SBD) fabricated on unintentional doped (UID) and carbon-doped AlGaN buffers. The off-state characteristics of diodes fabricated on UID buffer are dominated by buffer leakage and buffer breakdown voltage (BV) at higher reverse voltage ( [ABSTRACT FROM AUTHOR]

In this paper, a further leakage reduction of AlGaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been achieved by optimizing the physical vapor deposited TiN as the anode metal without severe degradation of on-state characteristics. The optimized GET-SBD multifinger power diodes with 10 mm anode width deliver \sim 4 A at 2 V and show a median leakage of 1.3 \mu \text{A} at 25 °C and 3.8 \mu \text{A} at 150 °C measured at a reverse voltage of −200 V. The temperature-dependent leakage of Si, SiC, and our GaN power diodes has been compared. The breakdown voltage (BV) of GET-SBDs was evaluated by the variation of anode-to-cathode spacing ( L\mathrm{ AC} ) and the length of field plate. We observed a saturated BV of \sim 600 V for the GET-SBDs with L\mathrm{ AC} larger than 5 \mu \textm . The GET-SBD breakdown mechanism is shown to be determined by the parasitic vertical leakage current through the 2.8 \mu \textm -thick buffer layers measured with a grounding substrate. Furthermore, we show that the forward voltage of GET-SBDs can be improved by shrinking the lateral dimension of the edge termination due to reduced series resistance. The leakage current shows no dependence on the layout dimension LG (from 2 to 0.75 \mu \textm ) and remains at a value of $\sim 10$ nA/mm. The optimized Au-free GET-SBD with low leakage current and improved forward voltage competes with high-performance lateral AlGaN/GaN SBDs reported in the literature. [ABSTRACT FROM PUBLISHER]

In this letter, we identified a dominant buffer trapping causing a bias-dependent dynamic R\mathrm{\scriptscriptstyle ON} for AlGaN/GaN Schottky barrier diodes (SBDs) fabricated on a C-doped AlGaN buffer as back-barrier. Current transient measurements at various temperatures were performed simultaneously on an AlGaN/GaN SBD and a transmission line model (TLM) structure based on the AlGaN/GaN heterojunction. During the stress of the TLM structure, the two Ohmic contacts are biased at the same voltage forming an equipotential surface while creating a uniform vertical electrical field to induce buffer trapping. We extracted the same dominant trap level of EC-0.60 eV from the current transient spectroscopy on both the AlGaN/GaN SBD and the TLM structure after stressing at −100 V, indicating that the increase in the dynamic R\mathrm{\scriptscriptstyle ON} of the diode is due to the electron trapping in the buffer layers. More electron filling of this buffer trap occurs at higher stressing voltages (from −50 to −200 V), which reflects in an enhanced current-transient amplitude at the same time-constant under higher stressing voltages. [ABSTRACT FROM PUBLISHER]

In this paper, we report the results of an experimental analysis of the degradation induced by ON-state stress in GaN-based Schottky barrier diodes (SBDs). When a high stress current is applied to the device, turn-ON voltage ( V\mathrm{TON} ), forward voltage ( VF ), and ON-resistance ( $R_{{{\mathrm{\scriptscriptstyle ON}}}})$ are affected by charge carrier trapping occurring at the AlGaN surface close to the anode corners and/or into the AlGaN barrier layer. We have investigated the degradation of SBDs under different stress conditions, analyzing the influence of temperature and voltage, investigating the activation energy of the traps, and hence the trapping mechanisms. In addition, thanks to this approach, the device lifetime has been evaluated, proving good device reliability. [ABSTRACT FROM AUTHOR]

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-gm), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si3N4, Rapid Thermal Chemical Vapor Deposition Si3N4, and Atomic Layer Deposition (ALD) Al2O3) for AlGaN/GaN Metal-Insulator- Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (Dit), the amount of border traps, and the threshold voltage (VTH) shift during a positive gate bias stress can be obtained. The results show that the VTH shift during a positive gate bias stress is highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the VTH shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract Dit needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the gm dispersion commonly attributed to border traps might be influenced by interface states. [ABSTRACT FROM AUTHOR]

AlGaN/GaN/AlGaN double heterojunction high-electron-mobility transistors were grown on 200 mm Si (111) using metalorganic chemical vapor deposition. The Al composition of AlGaN barrier varied from 20 at% to 30 at% and thickness from 10 nm to 20 nm. In some structures, a 1 nm AlN interlayer was inserted between AlGaN barrier and GaN channel. The as-grown wafers were proven to be of high material quality and the layer thickness were well controlled to the target values. A buffer break down voltage of over 700 V were obtained for all grown wafers. Compared to their counterparts without AlN interlayer, structures with AlN interlayer showed a much lower and more uniform two-dimensional electron gas sheet resistance. With the presence of AlN interlayer, the sheet resistance was much less sensitive towards variations in AlGaN barrier composition and thickness. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

This works presents a comparison of several different AlGaN/GaN powerbar designs, with a total gate width of 9mm, with the goal to minimize the total gate resistance. Analytical models were developed for the interconnect parasitics to aid in the design phase. The different power transistor topologies were fabricated in a GaN-on-Si MISHEMT technology. Measurements on the fabricated transistors showed a good agreement between the analytical models and the measurements. Furthermore, the modelling framework allowed us to design power transistors that reached the goal of reducing the gate resistance while having minimal impact on other characteristics. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Au-free GaN-based metal–insulator–semiconductor high electron-mobility transistors grown on 150-mm Si substrates are reported. The device characteristics for three different processes are compared: an ohmic-first and a gate-first process with Al2O3-only as gate dielectric and a novel approach with a bilayer gate dielectric stack consisting of Si3N4 and Al2O3. The Si3N4 layer was deposited in situ in the metal-organic chemical vapor deposition reactor in the same growth sequence as the rest of the epilayer stack and the Al2O3 layer was deposited ex situ by atomic layer deposition. Only the process with the bilayer gate dielectric results in robust devices with a breakdown voltage >600~V. The ohmic contact resistance for Au-free Ti/Al/W metallization scheme is <1~\Omega\cdotmm. The devices show high maximum output current density (>0.4~A/mm); and low gate and drain leakage (<10^-10~A/mm). The maximum pulsed mode drain–source current of power bars with 20 mm gate width is 8 A. The specific on-state resistance is 2.9 m \Omega\cdotcm^2. [ABSTRACT FROM AUTHOR]

In this paper, we review and add additional data and understandings on our findings on the two most common failure modes of GaN-based HEMTs: 1) permanent gate leakage current increase and 2) output current drop. We suggested that they have different origins and one is not necessarily correlated to the other. Yet, they can both concur to the device degradation. First, we demonstrate that the phenomenon of gate leakage current increase has a voltage-accelerated degradation kinetic. Therefore, the identification of the critical voltage for leakage increase is meaningless. We demonstrate that the time-to-breakdown tBD data are Weibull distributed and we prove that they represent intrinsic failures. According to our data, this phenomenon is not related to the inverse piezoelectric effect. Finally, a new degradation model for the gate leakage current increase based on the percolation path theory is proposed. Second, we show that the permanent output current drop is a consequence of the relaxation of AlGaN layer. This occurs by means of formation of crystallographic defects as described by the inverse piezoelectric degradation model. Finally, we show an excellent stability of devices with reduced Al content in the AlGaN barrier, proving the crucial role of strain in the reliability of AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

In this letter, we studied the forward bias gate breakdown mechanism on enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistors. To the best of our knowledge, it is the first time that the temperature dependence of the forward gate breakdown has been characterized. We report for the first time on the observation of a positive temperature dependence, i.e., a higher temperature leads to a higher gate breakdown voltage. Such unexpected behavior is explained by avalanche breakdown mechanism: at a high positive gate bias, electron/hole pairs are generated in the depletion region at the Schottky metal/p-GaN junction. Furthermore, at a high gate bias but before the catastrophic gate breakdown, a light emission was detected by a emission microscopy measurement. This effect indicates an avalanche luminescence, which is mainly due to the recombination of the generated electron/hole pairs. [ABSTRACT FROM PUBLISHER]

This letter reports an extensive analysis of the charge capture transients induced by OFF-state bias in double heterostructure AlGaN/GaN MIS- high electron mobility transistor grown on silicon substrate. The exposure to OFF-state bias induces a significant increase in the ON-resistance (R \(_{\mathrm {{on}}}\) ) of the devices. Thanks to time-resolved on-the-fly analysis of the trapping kinetics, we demonstrate the following relevant results: 1) R \(_{\mathrm {{on}}}\) -increase is temperature- and field-dependent, hence can significantly limit the dynamic performance of the devices at relatively high-voltage and high temperature (100 °C–140 °C) operative conditions; 2) the comparison between OFF-state and back-gating stress indicates that the major contribution to the R \(_{\mathrm {{on}}}\) -increase is due to the trapping of electrons in the buffer, and not at the surface; 3) the observed exponential kinetics suggests the involvement of point-defects, featuring thermally activated capture cross section; and 4) trapping-rate is correlated with buffer vertical leakage-current and is almost independent to gate-drain length. [ABSTRACT FROM AUTHOR]

We report on a novel Au-free CMOS process-compatible process for AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors. The process starts from a 150-mm GaN-on-Si substrate with an embedded \Si3\N4\/ \Al2\O3 bilayer gate dielectric, encapsulated by a high-temperature low-pressure chemical vapor deposited nitride layer. Power devices with a 20-mm gate width reach a maximum output current of 8 A, a breakdown voltage of 750 V, and a specific on-resistance Ron, sp of 2.9 \m\Omega\cdot\cm^2. The off-state drain leakage at 600 V is 7 \mu\A. We show robust gate dielectrics with a large gate bias swing. [ABSTRACT FROM PUBLISHER]

III-Nitride materials are very promising to be used in next-generation high-frequency power switching applications. In this letter, we demonstrate the performance of normally off AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs) using a boost-converter circuit. The figures of merit of our large (57.6-mm gate width) GaN transistor are presented: RON \ast QG of 2.5 \Omega\cdot\nC is obtained at VDS = \140\ V. The switching performance of the GaN DHFET is studied in a dedicated high-frequency boost converter: both the switching times and power losses are characterized. We show converter efficiency values up to 96.1% at 500 kHz and 93.9% at 850 kHz at output power of 100 W. [ABSTRACT FROM AUTHOR]

In this letter, we present a local substrate removal technology (under the source-to-drain region), reminiscent of through-silicon vias and report on the highest ever achieved breakdown voltage (VBD) of AlGaN/GaN/AlGaN double-heterostructure FETs on a Si (111) substrate with only 2-\mu\m-thick AlGaN buffer. Before local Si removal, VBD saturates at \sim700 V at a gate–drain distance (LGD) \geq \8\ \mu\m. However, after etching away the substrate locally, we measure a record VBD of 2200 V for the devices with LGD = \20\ \mu\m . Moreover, from Hall measurements, we conclude that the local substrate removal integration approach has no impact on the 2-D electron gas channel properties. [ABSTRACT FROM AUTHOR]

This paper reports an extensive analysis of the trapping and reliability issues in AlGaN/GaN metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs). The study was carried out on three sets of devices with different gate insulators, namely PEALD SiN, RTCVD SiN and ALD Al 2 O 3 . Based on combined dc, pulsed and transient measurements we demonstrate the following: (i) the material/deposition technique used for the gate dielectric can significantly influence the main dc parameters (threshold current, subthreshold slope, gate leakage) and the current collapse; and (ii) current collapse is mainly due to a threshold voltage shift, which is ascribed to the trapping of electrons at the gate insulator and/or at the AlGaN/insulator interface. The threshold voltage shift (induced by a given quiescent bias) is directly correlated to the leakage current injected from the gate; this demonstrates the importance of reducing gate leakage for improving the dynamic performance of the devices. (iii) Frequency-dependent capacitance–voltage (C–V) measurements demonstrate that optimized dielectric allow to lower the threshold-voltage hysteresis, the frequency dependent capacitance dispersion, and the conductive losses under forward-bias. (iv) The material/deposition technique has a significant impact on device robustness against gate positive bias stress. Time to failure is Weibull-distributed with a beta factor not significantly influenced by the properties of the gate insulator. The results presented within this paper provide an up-to-date overview of the main advantages and limitations of GaN-based MIS HEMTs for power applications, on the related characterization techniques and on the possible strategies for improving device performance and reliability. [ABSTRACT FROM AUTHOR]

We focus on slow de-trapping phenomena in AlGaN/GaN MIS-HEMTs with a bilayer dielectric ( in-situ Si 3 N 4 /Al 2 O 3 ) with two different thicknesses of in-situ Si 3 N 4 (10 nm and 5 nm). By using a “filling pulse” at a positive gate voltage, a trap with activation energy of 0.69–0.7 eV was identified to be responsible for the V TH shift. Based on literature, filling conditions, and the simulated band diagrams, this trap is most probably located at the interface between the dielectrics and AlGaN barrier. A physical model is proposed to explain the V TH shift due to the trapping/de-trapping phenomena based on the occupation dynamics of donor traps at the interface between the in-situ Si 3 N 4 /Al 2 O 3 and the AlGaN barrier. [ABSTRACT FROM AUTHOR]

The reliability of Au-free Ohmic contacts has been evaluated under a constant current stress (500 mA/mm) in a high temperature environment (150 °C, 175 °C, and 200 °C). Two Ohmic contact schemes with different Ti/Al thicknesses (5 nm/100 nm and 10 nm/100 nm) have been tested. The results showed that the degradation of the resistance ( R increase ) is accelerated at a higher temperature condition. Moreover, R increase has a square root dependence with the time. This indicates that a diffusion process could be responsible for the observed degradation. This has been confirmed by means of physical failure analyses (FIB/TEM) performed on a highly degraded device: an apparent roughness of the interface between TiN and the Ohmic metal layer was observed. On top of this, Nitrogen out-diffusion into the Ohmic metal was observed in the EDS/EELS analyses, suggesting that a material diffusion phenomenon might play a role. In addition, we observed that the devices with a lower initial contact resistance ( R c ) showed lower degradation with respect to devices with a larger initial R c . This suggests that obtaining lower R c is beneficial not only for the performance but also for the reliability. [ABSTRACT FROM AUTHOR]