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In this article, threshold-voltage VTH instabilities under positive gate voltage stress VGStress in GaN-on-Si devices are thoroughly investigated. Measurement-stress-measurement pBTI technique using ultrafast VG ramp was applied in this study. PBTI transients performed at different VGStress and several temperatures highlight the influence of two trap populations, one being related to Al2O3 gate oxide defects and the other one to CN acceptors in GaN lattice. Both trap populations are located close to the Al2O3/GaN interface and lead to VTH instabilities via two different underlying mechanisms simulated by TCAD. PBTI transients obtained under several dc and ac stress conditions have also been modeled using capture emission time (CET) maps and allowed the identification of the two trap populations. Analysis of the temperature-dependent CET maps gives an activation energy of 0.8–0.9 eV related to CN traps and an energy range between 0.7 and 1.5 eV ascribed to Al2O3 defects above the GaN conduction band energy. This study provides a better understanding of the underlying physical mechanisms, leading to BTI degradation in GaN-HEMT technologies.

International audience; This work presents the performance and low-frequency noise (LFN) of 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The experimental measurements and the analysis are performed as a function of temperature for the first time, focusing on cryogenic applications, down to 4.2 K. The back bias impact on device performance is evaluated. The results reveal that the threshold voltage tuning is found to be temperature independent, allowing extra drain current improvement. This is particularly interesting for short channel devices, whose drain current gain with temperature lowering is expected to be smaller in comparison with long channel MOSFETs. LFN is characterized by means of time-domain current sampling measurements. Moderate and strong inversion regimes are investigated. The carrier number with correlated mobility fluctuations model can well describe the 1/f noise behavior down to 4.2 K. The physical origin behind the drain current noise-to-signal power augmentation with temperature lowering could be mainly attributed to the normalized transconductance improvement.

International audience; The wide range of cryogenic applications, such as spatial, high performance computing or high-energy physics, has boosted the investigation of CMOS technology performance down to cryogenic temperatures. In particular, the readout electronics of quantum computers operating at low temperature requires larger bandwidth than spatial applications, so that advanced CMOS node has to be considered. FDSOI technology appears as a valuable solution for co-integration between qubits and consistent engineering of control and read-out. However, there is still lack of reports on literature concerning advanced CMOS nodes behavior at deep cryogenic operation, from devices electrostatics to mismatch and self-heating, all requested for the development of robust design tools. For these reasons, this chapter presents a review of electrical characterization and modeling results recently obtained on ultra-thin film FDSOI MOSFETs down to 4.2 K.

International audience; A new protocol based on Y-function is used for accurate statistical extraction of electrical parameters of High Electron Mobility Transistor (HEMT) devices for GaN technology. This protocol presented here is used for extraction of relevant electrical parameters such as oxide capacitance, threshold voltage, effective mobilities and access resistance. This study has been verified over a large range of channel lengths for two normally-off HEMT GaN wafers having different levels of access resistances.

In this paper, the flicker noise properties of bottom-gate ESL structured amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) from two different technologies have been studied and modeled. Model development is carried out by adapting the Unified Model parameter Extraction Method (UMEM), developed for parameter extraction and compact modeling of TFT devices, and the unified 1/f noise model. Furthermore, comparative study of device figures of merits is performed to point out the device performance enhancements that the different fabrication technologies have brought about. It is found out that both devices have low deep state density, whereas the second device demonstrated higher performance in terms of carrier mobility and subthreshold slope. Both the DC and noise models are validated by matching them against experimental data obtained in different regimes of device operation.

This paper discusses the impact of both contact and channel resistance on capacitance and conductance characteristics measured with pseudo-MOSFET method by analyzing the impedance and admittance in frequency domain. We clarify the mechanisms affecting the ac response of pseudo-MOSFET structure for SOI wafer with thin SOI film by using simple series and parallel circuits composed of resistance and capacitance. Our measurement results show the gate bias range where the influence of the contact resistance becomes dominant in measurements with single and multiple probes. The degradation of the capacitance measured at high frequency is also analyzed by constructing an equivalent circuit, which detach the influence of the contact and channel resistances quantitatively. The necessity to carefully account for the influence of the contact resistance in pseudo-MOS method is clarified.

FD-SOI five-gate (5G) qubit MOS devices are electrically characterized in linear regime down to deep cryogenic temperatures. The Lambert-W function is successfully used for the modelling of such 5G MOS devices from subthreshold regime to strong inversion. Its applicability is demonstrated down to 20 K. The 5G device is modeled as a series of five independent transistors: the "active" one, that directly controls the current, and the "external" ones, that act as access resistances. The Lambert-W function enables to accurately determine the inversion charge and the active channel resistance from weak to strong inversion. This approach allows reconstructing the drain current characteristic avoiding the evaluation of the mobility attenuation factors. The main device parameters are extracted versus temperature. Finally, the role of different scattering mechanisms has been investigated, underlying the impact of neutral defects for the gates in proximity of source and drain.

In this paper we present an analytical experimental study regarding the extraction and analysis of 28 nm FD-SOI MOSFET parameters, from room temperature down to 25 K, and from micro- to nanometer gate lengths. It is shown that the FD-SOI device behavior with temperature can reliably be described by the already established theory of physics for deep cryogenic conditions: Boltzmann statistics and phonon scattering mechanisms are the two main factors that define the device electrical behavior. Moreover, we also demonstrate the advantage of the Y-function as a parameter extraction method, across different channel lengths, and a wide temperature range. We demonstrate the dependence of threshold voltage, sub-threshold swing, low-field mobility and source-drain series resistance on temperature, and how this may be affected by the gate length decrease.

We target the analysis and modeling of the I-V characteristics in organic thin film transistors (OTFTs) and IGZO TFTs from 150K to 350K, as well as the temperature dependences of the extracted parameters. Our compact model reproduces very well the I-V characteristics within that range of temperatures for both types of devices.

This work presents a new method, called “pinch to detect”, for the characterization of Random Telegraph Noise (RTN) in nanometer length Tri-Gate Nanowire MOSFETs, allowing for the maximum number of active RTN traps to be detected. We demonstrate that the channel pinch-off effect, which takes place in saturation region, can actually be exploited for the modulation of RTN amplitudes and kinetics, and therefore disable (or enable) the appearance of RTN signals which are present (or not) in linear region, where the channel is uniform. It is shown that by combining the measurements for three different channel configurations, i.e. uniform, pinched-off near the drain and pinched-off near the source, the total number of detectable RTN traps can be maximized. This conclusion is also supported by noise spectral analysis and TCAD simulations. Furthermore, it is demonstrated through how going to longer channels with no short-channel effects does not make this effect disappear, but just limit it to traps in the pinched-off region.

We review recent compact modeling solutions for Organic and Amorphous Oxide TFTs (OTFTs and AOS TFTs, respectively), which were developed, under the framework of the EU-funded project DOMINO, to address issues specifically connected to the physics of these devices. In particular, using different approaches, analytical equations were formulated to model the Density of States (DOS), different transport mechanisms, trapping/de-trapping, drain current, stress, capacitances, frequency dispersion and noise. The final TFT models were, after implementation in Verilog-A, validated by means of the design and simulation of test circuits.

In this article, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D subband structure. The conditions for which these specific features appear in thin-film silicon-on-insulator (SOI) devices have been analyzed, by varying the temperature, drain voltage, silicon channel thickness, and gate length.

A novel technique is presented for a direct evaluation of oxide breakdown under AC stress at high frequencies up to 500MHz. It relies on a RF setup, which combines a high speed pulse generator, transition converters and $50\Omega $ termination probes, to deliver to the device a digital AC signal without overshoot and distortion. The method leads to similar results than a complex on-chip solution while offering more simplicity and flexibility. Time Dependent Dielectric Breakdown (TDDB) in 28nm Fully Depleted Silicon On Insulator (FDSOI) transistors is then characterized under DC and AC stress at various frequencies. It follows a power law with frequency TDDB $\alpha \text{F}^{\mathbf {a}}$ with a ≈0.3, allowing an extended lifetime to circuits operating at GHz frequency.

28 nm FD-SOI technology is electrically characterized aiming at cryogenic applications. Electrostatics and transport are evaluated and compared while lowering temperature from 300 K down to 4.2 K. FD-SOI versatility is shown over a wide temperature range of operation, as the back gate tuning efficiency is preserved at low temperatures. Insights on back gate bias behavior at room and low temperatures are obtained and the electrostatic coupling between front and back channels can be successfully modelled by using 1D Poisson-Schrodinger calculation from 300 K down to 4.2 K.

Junctionless transistors (JLTs) are one of attractive candidates for further scaling down thanks to their promising advantages based on a structural simplicity without PN junctions, and their physical operation is quite different from traditional inversion-mode (IM) transistors. In this paper, we investigated the subthreshold operation of tri-gate JLTs with various effective width (Weff) and compared to that of IM transistors. The on current to off current ratio (Ion/Ioff) and subthreshold swing (SS) of JLTs were varied dramatically as changing Weff. In addition, a better immunity against short channel effects (SCEs) of JLTs was proven. Physical operation mechanism on the subthreshold regime was also discussed in detail with considering distribution of mobile charge carriers, maximum depletion width, full-depletion mode, bulk neutral and surface accumulation conduction.

International audience; A new concept of differential effective mobility is proposed. It characterizes the effective mobility of an increment of drain current resulting from a small increase of inversion charge in MOSFET channel. It allows us to show that the effective mobility can be described by a local electric field approach and not entirely by an effective electric field model.

We investigated the performances of GaN junctionless fin-shaped field-effect transistors (FinFETs) with two different types of gate structures; overlapped- and partially covered-gate. DC, low-frequency noise (LFN), and pulsed I-V characterization measurements were performed and analyzed together in order to identify the conduction mechanism and examine both the interface and buffer traps in the devices. The fabricated GaN junctionless device with overlapped-gate structure exhibits improved DC and noise performance compared to the device with partially covered-gate, even though its gate length is much larger. The LFN behavior was found to be dominated by carrier number fluctuations (CNF). At off-state, the device with partially covered-gate exhibits generation-recombination (g-r) noise on top of 1/ ${f}$ noise. This superposition is correlated with the severe current collapse revealed by pulsed I-V measurements. In contrast, the device with overlapped-gate shows clear 1/ ${f}$ behavior without g-r noise.

Mismatch performance of 28 nm FDSOI technology is electrically characterized at low temperatures using integrated on-chip addressing for a matrix of transistors. The first statistical results ever published on FDSOI variability at 4.2 K provide valuable information for future compact transistor modeling in cryogenic circuit design. Slight increase of the threshold voltage mismatch is observed at low temperature. Nevertheless, the suppression of fluctuations in the random distribution of dopants for the fully-depleted transistor channel leads to a smaller threshold voltage variability for FDSOI at 4.2 K compared to advanced Bulk technology at room temperature.

The quality of interfaces between dielectrics and semiconductors has a tremendous impact on the performances of semiconductor devices. High-k dielectrics are omnipresent in the gate stack of advanced MOSFETs. They are also used as passivation layers for silicon in fields such as solar cells [1] or image sensors [2]. When referring to passivation, two mechanisms can be identified: chemical passivation (quantified by the interface state density, Dit) and electric-field passivation (quantified by fixed oxide charge density, Qox). An ideal characterization method for passivated silicon should give access to both chemical and field-effect relevant quantities (ideally being able to distinguish them) in a non-destructive way. Among the commonly used techniques, we can cite electrical methods based on current or capacitance monitoring of simple test devices [3], Corona characterization of semiconductors [4], carrier lifetime extraction [5] conducted through photoconductance or photoluminescence decay measurements, etc. The choice among these several options is based on criteria such as sensitivity, non-destructiveness, possibility of direct on-wafer probing without any additional device fabrication steps, ability to discriminate Dit and Qox, capability to provide a high spatial resolution. A recent technique which could meet all these criteria is the second harmonic generation (SHG) [6], provided that an appropriate calibration method is developed for Dit and Qox extraction. The SHG is a non-linear optics phenomenon: when a high intensity laser beam of wavelength λ reaches a sample, a second harmonic wave at λ/2 is generated by the sample. For centrosymmetric materials (such as silicon, SiO2, Al2O3, etc.) the SHG signal contains two parts: one related to the symmetry breaking inherently present at interfaces between two different materials, and another one produced by any “static” electric field in the sample [7]. Such field is present at the vicinity of dielectric-to-semiconductor interfaces due to charge trapping by various mechanisms. In other words, the magnitude of the generated SHG signal contains information on both Dit and Qox This technique has already been used for dielectric characterization with various modalities (SHG versus power, time, wavelength ...) [8], [9], [10]. The SHG proved very promising (sensitive, non-destructive, applied directly on-wafer, etc.); however its extensive use still needs a more general calibration methodology. Such a methodology requires not only SHG measurements, but also real Qox/Dit values extracted by classical electrical methods on the same samples and modeling to understand/anticipate the expected effect of these parameters on the SHG signal. In this paper, we’ll discuss all these issues based on a review of our recent advances on how to exploit SHG for dielectrics on semiconductor characterization. Acknowledgements This work was supported by Region Rhône Alpes (ARC6 program), the French National Research Agency within the framework of the OXYGENE project (ANR-17-CE05-0034) and French National Plan Nano2022, within the IPCEI Nanoelectronics for Europe program. [1] A. G. Aberle, "Surface passivation of crystalline silicon solar cells: a review," Progress in Photovoltaics: Research and Applications, vol. 8, pp. 473-487, 2000. [2] J. L. Regolini, D. Benoit, and P. Morin, "Passivation issues in active pixel CMOS image sensors," Microelectronics Reliability, vol. 47, pp. 739-742, 2007. [3] D. K. Schroder, Semiconductor Material and Device Chracterization, 3rd Edition ed. New Jersey: John Wiley & sons, 2006. [4] M. Wilson, J. Lagowski, L. Jastrzebski, A. Savtchouk, and V. Faifer, "COCOS (corona oxide characterization of semiconductor) non-contact metrology for gate dielectrics," AIP Conference Proceedings, vol. 550, pp. 220-225, 2001. [5] D. K. Schroder, "Carrier lifetimes in silicon," Electron Devices, IEEE Transactions on, vol. 44, pp. 160-170, 1997. [6] G. Lupke, "Characterization of semiconductor interfaces by second-harmonic generation," Surface Science Reports, vol. 35, pp. 75-161, 1999. [7] J. E. Sipe, D. J. Moss, and H. M. van Driel, "Phenomenological theory of optical second- and third-harmonic generation from cubic centrosymmetric crystals," Physical Review B, vol. 35, pp. 1129-1141, 1987. [8] J. Price, M. Lei, P. S. Lysaght, G. Bersuker, and M. C. Downer, "Charge trapping defects in Si/SiO2/Hf(1−x)SixO2 film stacks characterized by spectroscopic second-harmonic generation," Journal of Vacuum Science & Technology B, vol. 29, p. 04D101, 2011. [9] N. M. Terlinden, G. Dingemans, V. Vandalon, R. H. E. C. Bosch, and W. M. M. Kessels, "Influence of the SiO2 interlayer thickness on the density and polarity of charges in Si/SiO2/Al2O3 stacks as studied by optical second-harmonic generation," Journal of Applied Physics, vol. 115, p. 033708, 2014. [10] H. Park, J. Qi, Y. Xu, K. Varga, S. M. Weiss, B. R. Rogers, et al., "Boron induced charge traps near the interface of Si/SiO2 probed by second harmonic generation," Physica Status Solidi (b), vol. 247, pp. 1997-2001, 2010.

GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gate-all-around (GAA) structure. In this article, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows a threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low-voltage/power applications. However, the devices with smaller diameters of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance.

A comprehensive Kubo-Greenwood modelling of FDSOI MOS devices is carried out down to deep cryogenic temperatures. It is found that a single set of mobility parameters is only needed to fit the device characteristics versus temperature for long channel devices. Instead, in short channels, the neutral scattering mobility component µN is found to decrease at small gate length due to the increased presence of neutral defects close to source/drain ends whatever the temperature.

International audience; New analytical expressions for the subthreshold swing in FDSOI structures operated in both front gate and bottom gate modes are developed. These new equations (9)-(10) provide an accurate description of the subthreshold swing SW as a function of the main FDSOI stack parameters (film thickness, front gate thickness, back gate oxide thickness) and front/back interface trap density. They can be very useful for architecture design as well as electrical characterization of FDSOI devices operated either in front gate or free top surface bottom gate configurations.

International audience; Forward AC stress and relaxation have been performed on GaN-on-Si Schottky diodes to study the shift of diode characteristics such as threshold voltage. Influence of frequency and length of first anode field plate are studied. PBTI measurement performed on HEMTs with gate similar to the first anode field plate rules out the degradation of the dielectric under the anode field plate and tends to prove that Schottky contact itself could be the cause of forward stress degradation.

International audience; For advanced gate stacks, effective work function (WFeff) and equivalent oxide thickness (EOT) are fundamental parameters for technology optimization. On FDSOI transistors, and contrary to the bulk technologies, while EOT can still be extracted at strong inversion from the typical gate-to-channel capacitance (Cgc), it is no longer the case for WFeff due to the disappearance of an observable flat band condition on capacitance characteristics. In this work, a new experimental method, the Cbg(VBG) characteristic, is proposed in order to extract the well flat band condition (VFB, W). This characteristic enables an accurate and direct evaluation of WFeff. Moreover, using the previous extraction of the gate oxide (tfox), and buried oxide (tbox) from typical capacitance characteristics (Cgc and Cbc), it allows the extraction of the channel thickness (tch). Furthermore, the measurement of the well flat band condition on Cbg(VBG) characteristics for two different Si and SiGe channel also proves the existence of a dipole at the SiGe/SiO2 interface.

We target the device parameter analysis and drain current modelling for amorphous indium gallium zinc oxide (IGZO) thin film transistors from 210 to 370K. We study and discuss the temperature behaviour of physical IGZO TFT parameters from low to high temperatures. We demonstrated and explained that in IGZO TFTs, the characteristic temperature of the density of states (DOS) increases, with increasing temperature. Finally, using the extracted parameters, we validate our IGZO TFT drain current model at temperatures from 190K up to 370K.

A new differential method for accurate extraction of electrical parameters of high-electron mobility transistor (HEMT) devices for gallium nitride (GaN) technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the total metal–insulator semiconductor (MIS)-HEMT device conductance. First, an analytical model is proposed to account for the relative conduction of the edges and the main flat part of the channel HEMTs. Second, the differential method allows the split- CV mobility extraction of each part, allowing a precise analysis of the resistive contribution of each region of the HEMT devices. This study has been performed over a large range of channel lengths for two normally OFF HEMT GaN wafers having different recess depths.

International audience; For the first time, an in-depth analysis of the intertier dynamic coupling and RF crosstalk of digital circuits in 3D sequential integration enables to conclude on the need of a Ground Plane (GP) for various applications. Experiments in conjunction with TCAD simulations reveal the parasitic capacitances responsible for the dynamic coupling effects and their impact is investigated for a 3D sequential 2-bitcell SRAM cell circuit configuration. Furthermore, we show a greater than 20dB suppression up to 100GHz of the inter-tier RF crosstalk, achieved by the addition of a strategically designed polysilicon Ground Plane between active device layers enabling the possibility of heterogeneous 3DSI integration without metallic Ground Plane. We propose a technological solution to create experimentally a 34nm-thick polysilicon GP of 1.8x10 20 at/cm 3 n-doping and 295Ω/sq sheet resistance.

A new methodology for MOSFET characterization making use of the on-resistance characteristics Ron(Vg,Vd) = Vd/Id(Vg,Vd) and associated derivatives dRon/dVg and dRon/dVd is proposed. This approach enables to eliminate the influence of source-drain series resistance Rsd not only in linear region but also in non-linear region of MOSFET operation. Therefore, it allows for intrinsic MOSFET parameter extraction free from source and drain series resistance.

The impact of different interfacial layers (ILs) on the electrical performances of Au/Ti/HfO2/Ge0.9Sn0.1 metal oxide semiconductor (MOS) capacitors is studied. Parallel angle resolved x-ray photoelectron spectroscopy measurements show that germanium diffuses into the HfO2 layer when no IL is used. This results in an increase in the tin content at the interface and a high interface state density. We demonstrate that the use of an IL prevents germanium and HfO2 intermixing and improves the electrical performance of MOS capacitors. Several ILs are studied such as alumina (Al2O3) and plasma oxidized GeSn (GeSnOx) prior to HfO2 deposition. C–V measurements correlated with simulations made by a customized analytical model indicate an interface state density of 5 × 1011 eV−1 cm−2 for the HfO2/GeSnOx/Ge0.9Sn0.1 gate stack. This result is promising for the integration of high mobility GeSn channels in CMOS devices.The impact of different interfacial layers (ILs) on the electrical performances of Au/Ti/HfO2/Ge0.9Sn0.1 metal oxide semiconductor (MOS) capacitors is studied. Parallel angle resolved x-ray photoelectron spectroscopy measurements show that germanium diffuses into the HfO2 layer when no IL is used. This results in an increase in the tin content at the interface and a high interface state density. We demonstrate that the use of an IL prevents germanium and HfO2 intermixing and improves the electrical performance of MOS capacitors. Several ILs are studied such as alumina (Al2O3) and plasma oxidized GeSn (GeSnOx) prior to HfO2 deposition. C–V measurements correlated with simulations made by a customized analytical model indicate an interface state density of 5 × 1011 eV−1 cm−2 for the HfO2/GeSnOx/Ge0.9Sn0.1 gate stack. This result is promising for the integration of high mobility GeSn channels in CMOS devices.

We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low ION and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sentaurus TCAD tool. Extending the source (anode) at the bottom of the body region generates vertical band-to-band tunneling. Moreover, reducing the vertical distance between the extension and the gate oxide (Lrt) yields a very steep slope and higher ION compared to a device with only lateral tunneling, but only for gate lengths longer than 100 nm. Using an ultrahigh boron dopant concentration (1021 cm−3) thin layer at the bottom for extremely small body thickness (TSi

Time Dependent Dielectric Breakdown (TDDB) experiments are performed in the GHz frequency range on a dedicated test structure to mimic operating conditions. It is shown that TDDB device lifetime can be significantly improved at high frequency in the temperature range from −40 °C to 200 °C. In addition, no effect on voltage acceleration is measured between DC and AC stress modes. This result has strong implications for logic circuit lifetime estimation over extended voltage and temperature ranges and gives new insights on the mechanism responsible for AC TDDB effects.

We present a detailed study of the process influence on two-dimensional electron gas (2DEG) transport properties in Al0.25Ga0.75N/AlN/GaN heterostructure. Hall effect measurements are used to analyze the conduction in normally on devices demonstrating the formation of a second channel at the Al2O3/AlGaN interface for high biases. Electrical characterization is performed on a large set of devices for temperatures ranging from 25 °C to 250 °C, and 2DEG mobility is extracted using split C-V measurement technique. Various technological splits were experimentally tested and the corresponding mobility characteristics were modeled using the Kubo-Greenwood formula in order to determine the dominant scattering phenomenon limiting the 2DEG mobility.

In this paper, Low Frequency Noise (LFN) characterization of SP500 polymer-based Organic Thin Film Transistors with a nonfluorinated dielectric material is presented. The work aimed at identifying the mechanism of 1/f noise as well as inspecting the quality of the gate dielectric interface. Analysis of the LFN experimental data reveals that the 1/f noise power spectral density (PSD) follows 1/f γ frequency dependence over 1 Hz–10 kHz range. The normalized current noise PSD is found to vary similar to the squared-transconductance drain current ratio with respect to drain current, and is inversely related to the gate-area. Furthermore, the high carrier mobility (on the order of 2–3 cm 2 / Vs) obtained in these devices indicates that low density of traps exists in the semiconducting organic thin film. Such results ascribed the origin of 1/f noise to the dynamic exchange of charge carriers between the gate-dielectric traps and the channel. In addition, Nst values extracted from the 1/f noise experimental data reflect the enhanced quality of the gate dielectric and the interface it forms with the channel material.In this paper, Low Frequency Noise (LFN) characterization of SP500 polymer-based Organic Thin Film Transistors with a nonfluorinated dielectric material is presented. The work aimed at identifying the mechanism of 1/f noise as well as inspecting the quality of the gate dielectric interface. Analysis of the LFN experimental data reveals that the 1/f noise power spectral density (PSD) follows 1/f γ frequency dependence over 1 Hz–10 kHz range. The normalized current noise PSD is found to vary similar to the squared-transconductance drain current ratio with respect to drain current, and is inversely related to the gate-area. Furthermore, the high carrier mobility (on the order of 2–3 cm 2 / Vs) obtained in these devices indicates that low density of traps exists in the semiconducting organic thin film. Such results ascribed the origin of 1/f noise to the dynamic exchange of charge carriers between the gate-dielectric traps and the channel. In addition, Nst values extracted from the 1/f noise experimental...

A thorough investigation of trap density (Dit) in defective zones of Tunnel FET (TFET) devices is presented. The TFETs were fabricated with standard high-temperature (HT, 1050ºC) and low-temperature (LT, 600ºC) processes [1]. A larger average of defects at the top surface in LT process TFETs was found [2]. For the first time, we use charge pumping (CP) method [3] in Silicon On Insulator (SOI) HT & LT TFETs (Fig. 1) with a ultrathin silicon thickness of 11 nm, EOT of 1.18 nm and 145 nm thick BOX [4]. CP method requires the presence of majority and minority carriers since ICP current results from the recombination of detrapped electrons in the channel region with holes. Therefore, ICP is proportional to Dit and frequency. In FDSOI structures, the top and bottom interfaces are extremely close. This means that the pulse applied on the front-gate can sweep the whole film from accumulation to inversion. Carriers from the top region could also be trapped in defects located at the back interface, enabling a net contribution to the ICP current and thus, providing a non-accurate value of Dit. For this reason, it is mandatory to apply a back-gate voltage (VBG) in order to avoid the scanning of the back interface traps. In the past, the influence of the substrate polarization on the CP current has been studied for SOI devices with thicker films (from 450 nm to 100 nm) [5,6,7]. Here, we present the relation between the CP current (experiments) and the carrier concentration (TCAD simulation), for TFETs with ultrathin film. Specifically, for VBG = -20V at VG,top = +0.65V the electron density is located at the top surface, while the back interface is depleted of electrons (lower than 1015 cm-3). For VG,base = -0.65V, two layers of holes are formed at the channel interfaces. Considering both mechanisms at the same time, during the falling edge of the pulse, the concentration of electrons that could be trapped by defects at the bottom interface is at best equal to 1015 cm-3. Although the concentration of holes is significantly higher, the recombination at the back-interface is negligible because it is proportional to the lowest concentration of either carriers (here electrons). So, traps at the back-interface are rather empty of electrons and their contribution to ICP is low. The situation is different for VBG = +20V: at VG,top = +0.65V, electrons are present at each interface. At VG,base = -0.65V, the hole density is only formed at the top surface, while the back-interface is depleted of holes, deactivating the possibility of recombination. Finally, when VBG = 0V, electron and hole concentrations at the back-interface are more similar and participate in the recombination process. Simulation results indicate that the variation of the ICP depends of the carriers available for recombination at the front and back interfaces. Therefore either one of these concentrations decreases when the back-gate voltage is more negative (fewer electrons) or more positive (fewer holes), not only at the back but also at the top interface. Fig. 2 shows the minority carrier concentration (which governs the recombination rate and ICP) for different applied back-gate voltages. The curve of the carrier concentration presents the same shape as the one obtained for the experimental charge pumping current [2], explaining the recombination mechanism. Same consistent results between experiments and simulations have been obtained for different VG,base voltages respectively (-0.35 V and -0.85 V). We discuss in detail the shape of CP curves as well as the back-gate selection for the traps at the back-interface to have negligible contribution to the front-pulse CP current. Our updated CP method is applied to determine and compare the density of traps in HT and LT FD-SOI TFETs. Acknowledgments This work is partly funded by the French Public Authorities through NANO 2017 program and EQUIPEX FDSOI11. References C. Le Royer et al, EuroSoi-Ulis, pp. 69-72, (2015). C. D. Llorente et al, IEEE S3S, (2018). J. S. Brugler and P.G.A. Jespers, IEEE TED., vol. 16, no. 3 (1969). C. D. Llorente et al, Solid-State Electron., vol.144, pp.78-85 (2018). T. Ouisse et al, Trans. Electron Devices., vol.38, no.6 (1991). D. J. Wouters et al, Trans. Electron Devices, vol.36, no.9 (1989). Y. Li and T. P. Ma, Trans. Electron Devices, vol.45, no.6 (1998). Figure 1

In this paper, we propose the integration of a Ge-Sb-Se-N (GSSN) back-end selector with a HfO 2 /Ti resistive memory (RRAM) in 1S1R configuration. GSSN composition was tuned in order to be optimized for RRAM characteristics, combining low leakage current without degrading operating voltages. Electrical characterization of 1S1R structure was achieved to quantify and extract device features. More than 2 decades were measured between ON and OFF states. Leakage current lower than 1nA was achieved on unselected devices (V read /3). Modeling was performed in order to understand RRAM and OTS contributions in 1S1R conduction and to identify the best reading strategy. Based on 1S1R electrical performances, crossbar array was investigated predicting >1Mb size for the elementary array tile down to 10nm node.

Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (V gb ) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (V th ) and flat-band voltage (V fb ) of JLTs. In addition, series resistance (Ra) of JLTs was dependent on V gb and back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable R sd effects. The R sd was extracted by transfer length method (TLM) and its effects were de-embedded using simple equation.

This paper deals with the temperature dependence of the transfer characteristics of Silicon nanonet-based transistors. Electrical parameters such as threshold voltage, low field mobility and subthreshold slope ideality factor were extracted using a Lambert W function based model. Their variation with temperature was studied as a function of density of nanowires and channel length value.

In SiN/AlGaN/GaN heterostructures, the evaluation of interface charges at the SiN/AlGaN and AlGaN/GaN interfaces is crucial since they both rule the formation of the two-dimensional electron gas (2DEG) at the AlGaN/GaN interface. In this paper, we conducted a thorough analysis of the gate-to-channel capacitance CGC(VG) and of the drain current ID(VG) over a gate voltage VG range enabling the depletion of the 2DEG and the formation of the electron channel at the SiN/AlGaN interface. This work includes the establishment of analytical equations for VTH1 (formation of the 2DEG) and VTH2 (formation of the electron channel at the SiN/AlGaN interface) as a function of interface charges and of the p-doping below the 2DEG. The inclusion of the p-doped layer below the 2DEG and the use we made of VTH2 have not been reported in previous studies. Our analysis allows a reliable estimate of the interface charges at the AlxGa1−xN/GaN and SiN/AlxGa1−xN interfaces for various Al concentrations x as well as to demonstrate that the polarization charge at the SiN/AlxGa1−xN interface is compensated, which confirms previous findings. Moreover, this compensation is found to be induced by the AlGaN layer rather than the SiN layer.

International audience; Transconductance (gm) and its derivative (dgm/dVg) of junctionless transistors (JLTs), considered as a possible candidate for future CMOS technology, show their unique operation properties such as bulk neutral and surface accumulation conduction. However, source/drain series resistance (Rsd) causes significant degradation of intrinsic gm and dgm/dVg behavior in JLTs. In this letter, the Rsd effects on the operation of JLTs were investigated in detail and also verified with analytical modeling equations. This work provides helpful information for a better understanding of the operation mechanism of JLTs with de-embedded Rsd effects.

International audience; The negative bias temperature instability (NBTI) is investigated in ultrathin body ultrathin box (UTBB) fully depleted silicon-on-insulator (FD-SOI) p-MOSFETs with zero back gate bias and small drain bias voltage. The threshold voltage shifts during stress at different temperatures and gate bias voltage conditions show that the NBTI is dominated by the trapping of holes in preexisting traps of the gate dielectric, while the recovery transient follows a logarithmic-like time dependence. Considering the hole-trapping/detrapping mechanisms, NBTI modeling has been proposed capturing the temperature and gate voltage dependence.

A detailed study of the hot-carrier degradation in nano-scale fully depleted ultra-thin body and buried oxide n-MOSFETs is presented. The degradation mechanisms were identified based on static current-voltage measurements. The degradation of the transistor was explained by considering generation of traps at the gate dielectric/Si interface and traps located within a tunneling distance of the interface. All stress parameters are considered describing with semi-empirical relations their impact on the transistor parameters. Based on our analytical compact model, we propose an aging hot-carrier model predicting with good accuracy the device degradation stressed under different bias conditions using a unique set of model parameters. Display Omitted The hot-carrier degradation of nanoscale UTBB FD-SOI n-MOSFETs has been investigated under different drain and gate bias stress conditions.The degradation mechanisms have been identified by studying the static current-voltage characteristics measurements.The impact of the HC degradation on the device parameters has been expressed with semi-empirical models in terms of the stress time, channel length, drain bias and gate bias.Based on our analytical compact model, HC aging model is proposed enabling to predict the device degradation stressed under different bias conditions, using a unique set of few model parameters determined for each technology through measurements.

In this work, we studied the effect of high-pressure deuterium annealing (HPDA) on a p-type omega-gate nanowire field effect transistor by random telegraph noise (RTN) signal analysis. After HPDA under conditions of 400 °C and 10 atm for 30 min, IOFF decreases by 41.2% and ION increases by up to 5.4%. Also, subthreshold swing (SS) is reduced from 72 mV dec-1 to 70 mV dec-1. In RTN analysis, multi-level RTN is reduced to single-level RTN due to the passivation of a fast trap site by HPDA. ΔID/ID is also decreased 1.3 and 1.1 times at |VOV| = 0.2 V and 0.4 V, respectively. From the low-frequency noise analysis, the reduction of trap density is observed by 86% at |VOV| = 0.4 V after HPDA. Through these results, we found that the HPDA reduces traps of gate dielectric and improves the quality of the interface between gate dielectric and NW channel in p-type OGNW FET.

International audience; Two different lateral GaN-based nanowire gate-all-around transistors with and without 2-D electron gas (2-DEG) channel were fabricated using top-down approach, and their noise characteristics were investigated. The nanowire transistor with 2-DEG channel had a relatively larger channel cross section, which consists of regrown AlGaN/GaN plateau on the trapezoidal GaN layer, and exhibited negative threshold voltages ( ${V} _{\textsf {th}}$ ). The transistor without 2-DEG channel consisted only GaN layer with triangular-shaped smaller channel cross section and exhibited a positive ${V} _{\textsf {th}}$ . Both nanowire transistors clearly demonstrated typical $1/{f}$ noise characteristics, but the AlGaN/GaN nanowire transistor with 2-DEG channel showed larger noise magnitude. The noise characteristics of both devices are well explained by the carrier number fluctuation with correlated mobility fluctuation model. Using this model, the interface trap densities and the remote Coulomb scattering parameters were extracted, revealing a worse interface quality for the AlGaN/GaN device on the one hand, but stronger scattering for the narrow GaN transistor on the other hand.

International audience; In this paper we report on the fabrication and electrical characterization of InAs-on-nothing metal-oxide-semiconductor field-effect transistor composed of a suspended InAs channel and raised InAs n+ contacts. This architecture is obtained using 3D selective and localized molecular beam epitaxy on a lattice mismatched InP substrate. The suspended InAs channel and InAs n+ contacts feature a reproducible and uniform shape with well-defined 3D sidewalls. Devices with 1 μm gate length present a saturation drain current (I Dsat) of 300 mA mm−1 at V DS = 0.8 V and a trans-conductance (GM ) of 120 mS mm−1 at V DS = 0.5 V. In terms of electrostatic control, the devices display a minimal subthreshold swing of 110 mV dec−1 at V DS = 0.5 V and a small drain induced barrier lowering of 50 mV V−1.

International audience; We have investigated the impact of different wet treatments on the electrical performances of germanium–tin (GeSn)-based p-MOS capacitors with 10% Sn. Atomic force microscopy (AFM) showed the presence of Sn droplets for the degreased Ge0.9Sn0.1 surface, which were removed by HCl, HF, and HF:HCl treatments. On the other hand, (NH4)2S and NH4OH treatments were not fully able to remove these droplets. X-ray photoelectron spectroscopy (XPS) measurements confirmed AFM results and highlighted the efficiency of HF, HCl, and HF:HCl treatments in removing Ge and Sn native oxide, which was not the case with (NH4)2S and NH4OH. Nevertheless, XPS showed a reoxidation of the Ge0.9Sn0.1 surfaces a few minutes only after HF, HCl, and HF:HCl wet treatments. Therefore, another approach was tested. It consisted in using (NH4)2S to protect Ge0.9Sn0.1 surfaces from immediate reoxidation by creating a Ge0.9Sn0.1-S monolayer. Chemical depth profiles of Ge0.9Sn0.1/Al2O3 stacks were investigated using parallel angle resolved XPS (pAR-XPS), indicating a high quality interface when the Ge0.9Sn0.1 surface is cleaned previously by HF and then (NH4)2S. There was notably a lack of Sn or Ge diffusion into the Al2O3 layer. C–V characteristics combined with a custom-analytical model yielded a low interface trap density (Dit).

In this paper, we explore the influence of the fully recessed gate length on threshold voltage instabilities. The study has been performed by the use of ultra-fast pBTI measurements on GaN-on-Si E-mode MOSc-HEMTs, as well as TCAD simulations. It reveals that gate length reduction tends to decrease the pBTI degradation. Transient analyses (degradation/relexation) reveal same dynamics whatever the gate length while the value of the initial V TH directly influences BTI. TCAD simulations highlight that the full recess gate configuration creates a short-channel effect responsible for this peculiar Vth degradation.

In this paper, we investigate the influence of negative gate stress on threshold voltage V TH instabilities in GaN-on-Si devices. This study has been carried out by using ultra-fast Measurement-Stress-Measurement (MSM) procedure on GaN-on-Si E-mode MOSc-HEMTs (Enhancement-mode MOS-channel HEMTs) for different gate lengths L G . NBTI transients at different temperatures and complementary ToF-SIMS analysis reveal the influence of two trap populations involved on V TH instabilities, both of them are related to the C N acceptor traps. The first one is close to the interface between GaN and Al 2 O 3 gate oxide due to N-vacancies induced by the dry etching process, the second one is likely to be related to GaN:C layer. NBTI transients also exhibit a dependence with L G , which is consistent with the E-field distribution of the gate region obtained by TCAD simulations at different gate stress voltages, and confirm the proximity of a C N trap population to the gate oxide.