Search

Condition monitoring of insulated gate bipolar transistor (IGBT) modules is an effective way to improve the transient performance and reliability of modular multilevel converters (MMC). This article proposes a novel bond wire failure monitoring method for the multichip IGBT modules in the MMC half-bridge submodule (SM) structure. The collector voltage undershoot VCA(np) of the complementary IGBT switch is measured during the turn-off switching transition of the controlled IGBT switch. VCA(np) is sensitive to the induced voltage over the stray inductance of the IGBT bond wires and provides high sensitivity as a health indicator. The non-intrusive measurement technique is demonstrated using a half-bridge circuit during the turn-off transition of the controlled IGBT, while its complementary switch (i.e., the device under test) is in the off state. Theoretical analysis and experimental results show that the parametric drift due to wire bonding failures can be effectively monitored with high specific relative sensitivity and granularity. To ensure its effectiveness in practical applications, the influence of load current, SM capacitor voltage, and junction temperature is discussed. In addition, a readout circuit is designed featuring the integrated desaturation detection and voltage peak detection, which offers both the short-term overcurrent fault protection and long-term bond wire aging monitoring functions. [ABSTRACT FROM AUTHOR]

Integrated gate-commutated thyristors (IGCTs) have successfully demonstrated to be well-suited devices for an application in medium-voltage dc transformers based on LLC resonant converter topology. This appli- cation enables unusually high switching frequencies in kilohertz range thanks to the zero-voltage switching while maintaining the high conversion efficiency. Moreover, the clamp circuit that is an inseparable part of every hard-switched IGCT-based converter can be completely omitted—further lowering the converter complexity and cost. Nevertheless, without the clamp circuit, the effect of shoot through becomes fatal, considering that the IGCTs have a defined mode of failure in short circuit and the desaturation effect is practically nonexistent. To prevent the shoot through, this letter proposes a simple, yet effective, protection method based on anode-voltage measurement that can be implemented locally on the IGCT gate unit. The validity of the solution is demonstrated using a custom IGCT gate unit in a medium-voltage resonant test setup. [ABSTRACT FROM AUTHOR]

Side-channel attack (SCA) is one of the physical attacks, which will reveal the confidential information from cryptographic circuits by statistically analyzing physical manifestations. Various circuit-level countermeasures have been proposed as fundamental solutions to eliminate the correlations between side-channel information and circuit’s internal operations. The existing solutions, however, will introduce nonnegligible power and area overheads, making them difficult to be deployed in resource-constrained applications. In this article, a novel three-independent-gate silicon nanowire field effect transistor (TIGFET) with the intrinsic SCA-resilience characteristics is introduced to balance the tradeoffs among cost, performance, and security of cryptographic implementations. We construct six TIGFET-based current mode logic (CML) gates that can retain lower power variation under all possible transitions compared to the CMOS counterparts. As a proof of concept, advanced encryption standard (AES), SM4 block cipher algorithm (SM4), and lightweight cryptographic algorithm PRESENT are implemented utilizing the TIGFET-based CML gates. Correlation power attack is performed to evaluate the improvement of SCA resilience. Simulation results verify that the TIGFET-based cryptographic implementations decrease 42.37% area usage, lower 61.16% energy efficiency, reduce $5.35\times $ power variation, and achieve a similar level of SCA resistance compared to the CMOS counterpart, which is applicable for the resource-constrained applications. [ABSTRACT FROM AUTHOR]

In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length (${L}_{g}$) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large ${L}_{g}$ effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with ${L}_{g}$ and GPs. With the same gate space, the short ${L}_{g}$ device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance. [ABSTRACT FROM AUTHOR]

This article proposes a voltage balancing technique for series-connected power devices in voltage source converters (VSCs). Each main power device has an active clamping module (ACM), consisting of a capacitor and an auxiliary switch. The ACM can clamp the main power device voltage, and voltage sharing among series-connected power devices can be realized by balancing the ACM capacitor voltages. The balancing circuit does not affect the normal operation of the devices and the introduced power losses can be ignored. The possible charging and discharging principles of the ACM capacitors are summarized. Then, the control strategy to balance the ACM capacitor voltages is introduced. The operating principles of a VSC with series-connected devices and the proposed balancing circuits are presented, including charging stage, discharging stage, and steady voltage stage. A switching sequence of auxiliary switch and main power switch is proposed to ensure ZVS-on of the auxiliary switch. Besides, design considerations of key parameters are presented. Finally, experimental results are provided to verify the effectiveness and feasibility of the proposed method. The voltage imbalance degree of the six series-connected devices is less than 3% under different operating conditions. The proposed method shows good balancing performance, good scalability, and low power losses. [ABSTRACT FROM AUTHOR]

This article introduces a silicon carbide (SiC)-based high-voltage silicon-controlled rectifier (HV-SCR) for on-chip electrostatic discharge (ESD) protection. The SiC HV-SCR is formed by implanting a $\text{p}^{+}$ region into the n-well of SiC laterally diffused metal-oxide semiconductor (LDMOS) structures. Both LDMOS and HV-SCR structures were characterized using a transmission line pulse (TLP) system to investigate their ESD behaviors. The TLP measurement results show that the trigger voltage (${V}_{\text {t1}}$) of the SiC HV-SCR is $\sim 230$ V and has minor dependence on the drift length. The ${V}_{\text {t1}}$ value of the SiC LDMOS decreases from 224 to 202 V when its drift length decreases from 6 to 4 $\mu \text{m}$. TLP measurements with 500- $\Omega $ impedance were conducted to obtain an accurate holding voltage (${V}_{\text {h}}$) and failure current (${I}_{\text {t2}}$) of HV-SCR and LDMOS. Relatively high ${I}_{\text {t2}}$ (i.e., 33 mA/ $\mu \text{m}$) of the HV-SCR structure was observed, which is much stronger than the LDMOS structure (i.e., 0.2 mA/ $\mu \text{m}$). The ${V}_{\text {t1}}$ and ${V}_{\text {h}}$ values of HV-SCR were also investigated with varying gate bias voltages. Moreover, technology computer-aided design (TCAD) simulations of the SiC HV-SCR and LDMOS were carried out to further understand their ESD behaviors. [ABSTRACT FROM AUTHOR]

Direct bidirectional current discharge paths between input/output (I/O) and ground (GND) are imperative to achieve robust charged device model (CDM) protection for very stringent design window in advanced low-voltage (LV) processes. In this brief, a compact and fast response dual-directional silicon-controlled rectifier (CFR-DDSCR) has been proposed. Using P-electrostatic discharge (ESD) implantation layer to implement each diode-triggered silicon-controlled rectifier (SCR) within only one n-well, the inherent defect of the prior art (i.e., the cumbersome p-well/n-well triggering diode) is eliminated, ensuring the low resistance of auxiliary triggering path and the compactness of silicon footprint. Moreover, by shielding all internal shallow trench isolation (STIs) with floating high- ${k}$ metal gates (HKMGs), an all-gate-bounded SCR structure is realized, and all triggering diodes evolve into gated diodes with compact current paths, thus improving the CDM protection capability greatly. Experimental results indicate that the CFR-DDSCR, with a design window suitable for 1.2 V-CMOS technologies, acquires a higher effective CDM robustness (73% improved), a faster turn-on speed (64% improved), and a more compact layout (31% shrunk) compared with its conventional counterpart, which is promising for the advanced LV CDM protection. [ABSTRACT FROM AUTHOR]

Low-frequency mymargin noise, thermal noise, and dc characteristics of nanoscale MOS transistors with dimensions close to the process minimum are highly variable. This article demonstrates a phase noise (PN) reduction technique for LC voltage-controlled oscillators (VCOs) that use an intelligent post-fabrication selection of a subset of an array of near minimum-size cross-coupled transistor pairs with reduced low-frequency noise and thermal noise. Using the technique, the PN of a VCO is lowered from the maximum by 3.5 dB at 600-kHz, 1-MHz, and 3-MHz offsets from a 3.8-GHz carrier. The lowest PN of −122, −129, and −139.5 dBc/Hz at 600-kHz, 1-MHz, and 3-MHz offsets, respectively, from a 3.8-GHz carrier has been measured using the PLL method of the Keysight E5052B Signal Source Analyzer. The VCO prototype was fabricated in a 65-nm CMOS process and dissipates 7 mW of dc power. The maximum figure of merit (FoM), including PN, carrier frequency, and power consumption, is 193 dBc/Hz, and the FoM, including the VCO core area, ${\mathrm {FoM}}_{A}$ , is 209 dBc/Hz. [ABSTRACT FROM AUTHOR]

A novel diode-triggered silicon-controlled rectifier with embedded MOS and island diodes (DTSCR-EMOS-ID) is proposed and investigated. The DTSCR-EMOS-ID was fabricated in 0.18- $\mu \text{m}$ and 22-nm CMOS processes for verifying the process transplantation. The fabricated DTSCR-EMOS-ID presents a low trigger voltage of 1.3 V, a small turn-on resistance of 8 $\text{m}\Omega /\mu \text{m}$ and a small parasitic capacitance of 43 fF. Meanwhile, the effective failure current and response time of DTSCR-EMOS-ID are optimized to 4.3 A and 3.6 ns, respectively. The DTSCR-EMOS-ID shows much better ESD performance than the conventional LVTSCR and DTSCR fabricated in the same process, which can be attributed to the diode triggering, gate coupling and large injection effects. Moreover, the TCAD simulation results of DTSCR-EMOS-ID agree well with the transmission line pulse testing results, further confirming that the proposed DTSCR-EMOS-ID can be widely used as an effective ESD protection device for high-speed ICs, without the limitation of the fabrication process. [ABSTRACT FROM AUTHOR]

In this article, a novel voltage divider trigger silicon-controlled rectifier (VDTSCR) with low trigger voltage and low leakage current for electrostatic discharge (ESD) protection applications has been proposed and verified in a 65-nm epitaxial CMOS process. The trigger structure formed by a voltage divider and an nMOS is introduced to the proposed structure. The voltage divider composed of two series capacitors can control the turn-on of the nMOS, and the nMOS current can trigger the silicon-controlled rectifier (SCR) device to reduce the trigger voltage of the proposed device. Such triggering structure is fully embedded in the proposed device for saving area. The measurement results show that the proposed device can achieve a low trigger voltage of 2.88 V, a low leakage current of 120 pA, and the second breakdown current of 4.35 A for a 1.2-V application. Furthermore, the VDTSCR device can be immune from the risk of latch-up and false triggering. Due to the low trigger voltage and low leakage current of the proposed device, it is suitable for low-voltage and low-power applications. [ABSTRACT FROM AUTHOR]

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18- $\mu \text{m}$ BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current (${I}_{\text {t2}}{)}$ of 1.59 A at a finger width of 50 $\mu \text{m}$. Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation. [ABSTRACT FROM AUTHOR]

This paper reports investigation of failure mechanisms of GaN-on-Si power device under electrostatic discharge (ESD) stress using on-wafer transmission-line pulse (TLP) testing. Hot-hole injections under the gate and filament formation in the buffer layer are examined by monitoring the threshold voltage ($V_{th}$) and on-resistance ($R_{on}$) subjected to a floating gate or an off-state gate voltage. Distinct and continued degradation has been observed after the ESD stress is removed indicating a slow de-trapping process due to deep-level buffer traps. Finally, 2D device simulation is used to probe the physical insight into failure mechanisms. [ABSTRACT FROM AUTHOR]

This letter focused on the additive effect of horizontal Schottky diodes on the drain side of a high-voltage p-channel laterally diffused metal–oxide–semiconductor (pLDMOS). These components were evaluated using transmission-line pulse and human body model (HBM) tests. When the parasitic Schottky area at the drain was smaller, the Schottky characteristics were less obvious; the device’s current mostly flowed through the heavily doped $\text{P}^{+}$ area, and the improvement in ${I}_{\text {t2}}$ was minor. When the parasitic Schottky area covered more than 60% of the drain side, the Schottky area accounted for the majority of current flow; therefore, the electrostatic discharge current could flow more evenly. These modified pLDMOSs can withstand higher voltages because of their parasitic Schottky diodes and higher impedance. In addition, their ${I}_{\text {t2}}$ values are superior to those of normal pLDMOSs. With the drain side of the pLDMOS completely covered by Schottky diodes, the device produced the highest ${I}_{\text {t2}}$ value of 1.659 A (130.4% higher than that of the reference sample), an HBM value of 5 kV (300% higher than the reference), and an improved holding voltage (4% greater than that of the reference). [ABSTRACT FROM AUTHOR]

We examine the electrostatic discharge (ESD) behavior of bottom-gate bottom-contact pentacene organic field-effect transistor (OFET) devices with a parylene-C gate dielectric. A comparison between devices with gate and contact overlap geometries of −2 to $3~\mu \text{m}$ are analyzed. In particular, the relationship between contact overlap, the protective effect of the increased overlap, and the electric field in the dielectric and their effect on ESD resilience is detailed. We find a markedly increased tolerance for negative contact overlaps and a small decrease in tolerance for more positive overlaps. We also report on a highly resilient effect where OFET devices continue to operate but with a reduction in performance after multiple dielectric breakdown. A negative overlap length should be carefully considered when designing OFET devices in a tradeoff between decreased performance and higher ESD resilience. [ABSTRACT FROM AUTHOR]

This article proposes a novel power p-GaN high-electron-mobility transistor (HEMT) with self-triggered discharging channel to improve gate-to-source electrostatic discharge (ESD) robustness. The self-triggered discharging channel consists of a small-size self-triggered p-GaN HEMT, a current-limiting resistor ${R}_{{1}}$ , and a proportional amplification resistor ${R}_{{2}}$. At ESD events, the proposed power p-GaN HEMT will be self-triggered by the high transient ESD voltage, and hence the accumulated electrostatic charges at its gate will be released through the self-triggered discharging channel. This avoids the gate-to-source damage of the proposed device, thereby enhancing the gate-to-source ESD robustness. Compared with the conventional power p-GaN HEMT, simulation results show that the transmission line pulsing (TLP) current handling capability (over 6.5 kV human body model failure voltage) of the proposed device is improved by 1900% without compromising other device characteristics. In addition, the fabrication process of the proposed device is fully compatible with the traditional power p-GaN HEMT platform, and the increase of total active area is less than 0.5%. The proposed device with self-triggered discharging channel can be a good reference for the design of power p-GaN HEMT with high ESD robustness. [ABSTRACT FROM AUTHOR]

A novel electrostatic discharge (ESD) protection device based on an n-type metal–oxide–semiconductor field-effect transistor (NMOSFET) with segmented topology was proposed and investigated, considering the material characteristics of 4H-SiC, which is a wide-bandgap material (3.3 eV). ESD phenomena are important in terms of semiconductor reliability, and the benefits of using 4H-SiC as a material can provide robustness and excellent thermal reliability to ESD protection devices. The proposed device improves the wide range of snapback phenomena caused by the high critical electric field (2.4 MV/cm), in comparison to using Si (0.25 MV/cm); it also improves triggering characteristics and provides a high holding voltage. The proposed device and a traditional silicon-controlled rectifier, a gate-grounded-NMOS, and a gate-body floating NMOS were fabricated using the 4H-SiC process. The electrical characteristics of the experimental devices, determined by a transmission-line-pulsing system, were comparatively analyzed. Additionally, this article presents the analysis of the optimization of electrical characteristics according to the critical design variables of the proposed device, stacking for high-voltage applications, and reliability test results for high temperatures (300–500 K). [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs more sensitive to charged-device model (CDM) ESD events, especially under cross-domain stresses. The traditional cross-domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal-oxide-semiconductor (MOS) structure against cross-domain CDM ESD stresses was proposed in this work and verified in 0.18-μm CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking-MOS protection designs was also investigated in detail. [ABSTRACT FROM AUTHOR]

This work presents a novel gated- diode SCR-incorporated BJT (SIB) structure for ESD protection purpose. A gated diode built in the SIB structure modulates reverse-biased P+ / N-well diode for better junction breakdown control. This device could achieve high TLP second breakdown current /ESD threshold close to that of an SCR, very high holding voltage, and reduced trigger voltage, as well as excellent latchup immunity. [ABSTRACT FROM AUTHOR]

This letter presents a fully integrated Ku-band low-noise amplifier (LNA) with a large-size transistor using 65-nm bulk complementary metal–oxide–semiconductor (CMOS) technology. To achieve an ultralow-noise figure, an optimization methodology balancing the ON-chip gate inductor and the parasitic capacitance of the large-size device is introduced. Using a voltage supply of 1 V, the proposed LNA has a 1.66-dB noise figure and 32.48-dB gain and, thus, outperforms other reported Ku-band bulk CMOS LNAs in these two respects. The LNA achieves the highest figure of merit I among reported Ku-band CMOS, silicon germanium, and gallium arsenide hetero-junction bipolar transistor LNAs. The LNA consumes a dc power of 22 mW and occupies a core area of $0.58\,\,{\times }\,\,0.43\,\,{\text {mm}}^{2}$. [ABSTRACT FROM AUTHOR]

Dual-direction electrostatic discharge (ESD) protection devices can discharge both positive and negative ESD surges, owing to their excellent area efficiency. This study proposes a novel dual-direction MOSFET ESD protection device with a high holding voltage. Most existing dual-direction ESD protection devices are based on silicon-controlled rectifiers (SCR). Among them, the low triggering dual-directional SCR (LTDDSCR) has good trigger characteristics, but with low holding voltage. In contrast, the proposed high-holding-voltage dual-direction NMOS (HHDDNMOS) operates using two NPN parasitic bipolar transistors connected to the ESD discharge path and has a very high holding voltage and excellent snapback characteristics. The electrical and dual-directional characteristics of HHDDNMOS were analyzed using the transmission-line -pulsing system, and the latch-up immunity was verified by conducting transient-induced latch-up tests using the 0.18- $\mu \text{m}$ BCD process. [ABSTRACT FROM AUTHOR]

This article proposes a dual-directional silicon-controlled rectifier (SCR) with a novel structure and high holding voltage to improve the electrostatic discharge (ESD) design area efficiency in high-voltage environments. In terms of structure, by decreasing the emitter injection efficiency of the p-n-p parasitic bipolar transistor formed at the bottom of the gate region, the SCR positive feedback gain is reduced, which endows the proposed device with improved snapback characteristics compared with the conventional low-voltage triggering SCR (LVTSCR) and low-trigger dual directional SCR (LTDDSCR). This article conducted 2-D and mixed-mode simulations to compare and analyze the operating principles of the proposed and traditional devices. Additionally, experimental devices were fabricated under the same conditions using the 0.13-μm process to verify their electrical properties and latch-up immunity by measuring the transmission line pulse (TLP) and transient latch-up (TLU). This article also conducted a detailed analysis on the optimization of electrical properties for the ESD design window of the proposed device according to the design variables and application of segment topology, and also analyzed the temperature reliability using a hot chuck control system. The measurement results reveal that the proposed device is highly suitable for the 12-V-class ESD design window, has improved reliability, and can provide excellent area efficiency in related applications. [ABSTRACT FROM AUTHOR]

This article explores the scope of drain-extended FinFET (DeFinFET) as a high-voltage (HV) device contender for Fin-based SoC applications. For the first time, guidelines for efficient and reliable HV integration in sub-14 nm FinFET nodes are given. Up to what extent DeFinFET stands as a promising choice is carefully investigated through device-circuit interactions and reliability analysis of range of DeFinFET options. The same is then compared, in terms of radio frequency (RF)-power amplifier (PA) performance, dc–dc conversion efficiency, electrostatic discharge (ESD) robustness, and hot carrier immunity (HCI) reliability, with other HV alternatives in FinFET nodes and its planar counterpart, that is drain-extended MOS (DeMOS). [ABSTRACT FROM AUTHOR]

Ti, Co, Pt, and Ni salicide processes optimized for a range of CMOS technology nodes down to 90nm were fabricated using 0.35 $\mu {\mathrm{ m}}$ SiGe BiCMOS. On-wafer circuitry was used to program discrete eFuse elements to compare their pre and post programmed resistances as well as their behavior during programming between each salicide process employed, with TEM analysis to confirm successful electromigration in the fuse link. A T0 analysis of CoSi shows link resistance scaling and temperature characteristics. Discrete eFuses were also subjected to 100ns Transmission Line Pulse (TLP) to compare ESD handling and robustness, and the associated MOSFET circuitry characterized for safe operating area (SOA) under DC and pulsed conditions. The analysis was expanded to look at the difference between the blow FET DC (reflected in the device models) and the pulsed FET (TLP) behavior (not captured in Design Kits). This work demonstrates the compatibility of electrically programmable fuse (eFuse) technology across a range of process technology nodes, as well as its robustness in high reliability applications. [ABSTRACT FROM AUTHOR]

Single and multi-Fin behavior of drain-extended FinFET (DeFinFET) devices under low and high current injection conditions is studied using detailed 3-D TCAD simulations. For completeness, electrostatic discharge (ESD) behavior of both shallow trench isolation (STI)-type and non-STI-type DeFinFET devices is studied. Under low current injection, junction breakdown, parasitic bipolar turn-on, as well as the onset of space charge modulation and its implications on high current behavior are explored. Under high current injection, the role of space charge modulation in electrothermal instability and filament formation is discussed. Unique filament spreading behavior has been discovered in DeFinFETs. Fin-based construction was found responsible for filament spreading. The interplay among bipolar turn-on, bipolar efficiency, filament density, and nature of filament spreading is explained. [ABSTRACT FROM AUTHOR]

The turn-around effect of drain linear current (Idlin) with stress time in a pMOSFET in the off-state stress is investigated. The degradation rate of Idlin increases to a maximum of 6.1% at 20 s of the stress time and then continuously decreases to 3.35% at 1000 s in the off-state stress. The turn-around effect is analyzed by comparing the degradation rates of the performance parameters (Idlin, Idsat, SS, and Vth) in the off -state and gate induced drain leakage (gidl) -state stress modes. The results indicate that the Idlin turn-around effect in the off-state stress, which occurs as an effect of the negative oxide charge (Qox) formation, is more significant than that of the interface trap (Nit) for short stress time (before 20 s), and the donor-like Nit formation has major effects compared to those of Qox over a long stress time (after 20 s). This observation shows that the stress-induced trap generation can be investigated even if the protection diode exists and critically impacts the drain current degradation and should be seriously considered in the reliability of a DRAM circuit. [ABSTRACT FROM AUTHOR]

In an industrial-grade bus, transient voltage suppressor (TVS) devices that need to withstand inrush currents ensure electrostatic discharge (ESD) reliability of the core chip. This article designs four types of dual-direction silicon-controlled rectifier (DDSCR) device structures based on the 0.5-μm CMOS process. The ESD performance of the TVS device is predicted and verified based on the basic principles of the device, two-dimensional device simulation, and transmission line pulse test results. Four DDSCR structures are embedded with floating N+ to adjust the device's holding voltage window. The results show that the current release capacity of DDSCR_1 is 81.93 mA/μm. The current release capability of DDSCR_2, which has a double-dummy-gate structure, is 82.37 mA/μm. The current release capability of DDSCR_3 of the gate-controlled structure is 86.68 mA/μm. The current release capability of DDSCR_4 of the double-dummy-gate structure and the gate-controlled structure is 86.25 mA/μm. Furthermore, the effect of the size of these devices on the ESD characteristics was studied. The on-resistance of the device structure is calculated by the curve-fitting method. The influence of the dummy gate structure and the gate-controlled structure on the ESD characteristics is analyzed. Finally, the optimal device size to meet the window is found. [ABSTRACT FROM AUTHOR]

This article reports the distinct failure mechanisms and insights on device degradation of AlGaN/GaN high electron mobility transistors (HEMTs) under electrostatic discharge (ESD) stress conditions. The role of device surface, MESA isolation, and gate Schottky junction in defining the degradation type is discovered. Premature breakdown at the MESA Schottky junction and dislocation induced failure in the active region and their consequences on ESD robustness are reported. Physical mechanisms responsible for snapback instability in transmission line pulsing (TLP) characteristics are discussed. Change in device failure from soft to hard with pulsewidth is revealed. Finally, the role of contact resistivity, surface diffusion, and channel electric field and its fringing effect at contacts are analyzed in context to ESD failure of AlGaN/GaN HEMTs. Various stages of device degradation during TLP stress are captured on-the-fly using high-resolution (HR) optical microscopy and high-speed Si charge-coupled device (CCD) detector. Postdevice failure, damaged regions are analyzed using transmission electron microscopy and scanning electron microscopy together with in situ energy-dispersive X-ray spectroscopy to probe details of failure mechanisms involved. Finally, based on the learning from this article, design guidelines for an ESD robust HEMT are proposed. [ABSTRACT FROM AUTHOR]

Large area and flexible electronic systems are widely used in applications such as displays, image sensors, wearable electronics and energy harvesting systems. A key element in many of these systems is the electrostatic discharge protection circuit. The conventional protection circuit uses large aspect-ratio diode connected thin film transistors that offer a low resistance path to the surge current but also does the same to signals during normal system operation resulting in power loss. Here we describe as well as demonstrate the feasibility of a novel idea for electrostatic discharge protection involving an adaptive dielectric thin film transistor that self-configures itself to a low resistance state during an electrostatic discharge event and a high resistance state during normal operation without external control. This results in 1000–10000 times the power savings compared to diode connected TFTs. [ABSTRACT FROM AUTHOR]

This experimental study reports new aspects of electrostatic discharge (ESD) behavior in AlGaN/GaN HEMTs. The role of Schottky gate and MESA is investigated using special test structures. Influence of piezoelectric field, carrier trapping, and self-heating on ESD behavior is studied. A unique power-law-like behavior is found. Linear scaling of failure current with source–drain spacing is reported. Spot measured drain-to-source DC current is realized as an important parameter to monitor degradation. Unique degradation trends are observed for the first time and a correlation between snapback depth and % degradation is established. Cumulative nature of device degradation is discovered. Change from soft to hard failure with an increase in pulsewidth (PW) is reported. Finally, the cause of snapback instability observed in device, at low PW, is discussed. [ABSTRACT FROM AUTHOR]

In this paper, we present the detailed physical insights into the electrostatic discharge (ESD) behavior of hydrogenated amorphous silicon (a-Si:H)-based thin-film transistor (TFT) technology. Device failure under ESD conditions is studied in detail using electrical and optical techniques. Device degradation under ESD timescales is studied using real-time capacitance–voltage and a spatially variant degradation behavior is reported. Variations in material properties are studied before and after device failure using Raman spectroscopy. Device dimension-dependent failure mechanism is explored. Impact of stressing conditions and presence of top passivation on failure behavior is also explored. Failure physics of technologically relevant device architectures including diode-connected transistors (gated diodes) and drain underlap TFTs and their increased ESD robustness is discussed. Finally, ESD behavior of a-Si:H-based TFTs is discussed. [ABSTRACT FROM AUTHOR]

To effectively protect the interface circuit between separated power domains from electrostatic discharge (ESD) damage, a new diode-triggered quad-silicon-controlled rectifier (DTQSCR) is proposed and realized in a 0.18- $ {\mu }\text{m}$ 1.8-V/3.3-V CMOS process. Since the DTQSCR embeds four silicon-controlled rectifier paths and a structure of back-to-back diodes, the silicon area can be efficiently reduced more than 30% as compared to the traditional ESD protection design under the same ESD specification. From the measurement results in silicon chip, an interface circuit (level shifter) with the proposed ESD protection design can successfully sustain a human-body-model of greater than 5.5 kV. The proposed ESD protection device is suitable to protect the interface circuits between different power domains. [ABSTRACT FROM AUTHOR]

We demonstrate a gate-lifted nMOS electrostatic discharge (ESD) protection device triggered by a p-n-p in series with a diode in a 0.18- $\mu \text{m}$ bulk CMOS technology for 5-V mobile applications up to 85 °C. This voltage-triggering scheme is suitable for fail-safe, open-drain, supply, and surge protections. In addition, the robust ESD performance is boosted by parasitic embedded-silicon-controlled-rectifier action in the high-current regime. No extra masks nor additional RC control circuitry are required for this implementation. [ABSTRACT FROM AUTHOR]

A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18- $\mu \text{m}$ 1.8-/3.3-V CMOS technology. Codesigned with the on-chip electrostatic discharge (ESD) protection devices (gate-ground nMOS and gate-VDD pMOS) equipped at the input–output (I/O) pad, the overshooting/undershooting trigger current during latch-up test can be conducted away through the turned-on channels of the ESD protection MOSFET’s to the power rails (${V}_{\textsf {DD}}$ or ${V}_{\textsf {SS}}$). Therefore, the trigger current injecting from the I/O devices (that directly connected to the I/O pad) through the substrate to initiate the latch-up occurrence at the internal circuit blocks can be significantly reduced. Thus, the latch-up immunity of the whole chip can be effectively improved under the same placement distance between the I/O cells and the internal circuit blocks. The new proposed design is a cost-efficient solution to improve latch-up immunity and also to mention good ESD robustness of the I/O cells. [ABSTRACT FROM AUTHOR]

For circular ultra-high voltage (UHV) 300-V power nLDMOS devices, a novel device architecture of high voltage p-well (HVPW) zones is embedded into a high voltage n-well (HVNW) drift region to form superjunction (SJ) structures (radial-type). And, by the HVPW/HVNW SJ of the radial-type, eight types of area ratios are fabricated. However, the human-body model (HBM) capacity of this UHV nLDMOS reference group is only 2500 V. For equal partition radial-type SJ, due to more even HVPW distribution in the equal 32-partitions, the HBM level (6750 V) was the highest. Meanwhile, it can maintain a fairly high breakdown voltage as with the reference sample. Finally, for the radial-type 30 equal partitions with different HVPW/HVNW area ratios, because the HVPW area was large in the HVPW/HVNW ratio(≈2:1), more conduction current flowed into the BNW layer under these new inserted HVPWs and dispersed the conduction current; thus, the HBM (7000 V) was the best. Thus, the more even partition and higher proportion of HVPW/HVNW area ratio in drain-side SJ architecture, the stronger its electrostatic discharge reliability performance. [ABSTRACT FROM AUTHOR]

This paper develops a degradation test scheme for insulated gate bipolar transistors (IGBTs) that are subjected to repeated electrostatic discharge (ESD). The proposed 7-step scheme is implemented to characterize the latent ESD damage of trench gate field stop IGBTs. An empirical degradation model based on the shift in threshold voltage is proposed with three model parameters: two parameters are IGBT-type-dependent and the other parameter is manufacturer-dependent. The two IGBT-type-dependent parameters for trench gate field stop IGBTs are determined using the test results obtained from two types of IGBT components produced by the same manufacturer. The correlation between the model and the test data is extremely high, which proves the accuracy of the proposed model. The applicability of the model is further corroborated using the test data obtained from IGBT components and modules produced by other manufacturers. The results confirm that the proposed degradation model can accurately predict the degradation of IGBT components as well as modules subjected to ESD damage. [ABSTRACT FROM AUTHOR]

In this paper, a compact and self-isolated dual directional silicon-controlled rectifier (CSDDSCR) developed in a single N-well has been proposed and demonstrated. Without using the P-well, the N-type isolation structure as well as an auxiliary trigger component, which are normally required in the traditional DDSCR, the novel CSDDSCR possesses a very high area-efficiency and robustness of ~8.81 V/ $\mu$ m2. It is also shown that the CSDDSCR preserves a lower trigger voltage as 10 V, an adjustable holding voltage from 3.32 to 8.79 V under the TLP test, a smaller overshoot voltage of ~19 V at 2 A VFTLP stress, as well as an extremely low leakage current of ~94 pA measured at 3.3 V, making it a superior candidate for electrostatic discharge protection in the 3.3 V/5 V CMOS processes. Moreover, a holding voltage reversal effect has also been discovered and explained with TCAD simulation. [ABSTRACT FROM AUTHOR]

For sub-5 nm bulk Si CMOS, a gate-all-around (GAA) nanowire (NW) device is a promising candidate. The new device architecture will have an impact on the transient performance of an electrostatic discharge protection diode. The 100 ns transmission line pulse (TLP) and 2 ns very fast TLP measurement results and TCAD simulations prove that the performance in bulk GAA NW-based diodes is maintained in comparison to bulk FinFET diodes. [ABSTRACT FROM AUTHOR]

A novel gate diode triggered silicon-controlled rectifier (GDTSCR) with dual-direction high-voltage (HV) electrostatic discharge (ESD) protection and a low snap-back voltage is proposed and investigated. Compared to conventional MOS triggered SCR (MTSCR), the GDTSCR has two gate diodes and one additional n-p-n. Superior to the MTSCR, the GDTSCR exhibits a high holding voltage of 15 V, a small trigger voltage of 17 V, and a strong ESD robustness of 6000 V in an area of $1600~\mu \text{m}^{\textsf {2}}$ , benefitting from the gate-controlled field effect diodes and the weakened regenerative feedback of the SCR. As such, the proposed GDTSCR is an attractive device for constructing effective and latch-up immune solutions for HV ESD protection. [ABSTRACT FROM AUTHOR]

In this letter, we propose a 4H-SiC-based electrostatic discharge (ESD) protection circuitwith a new structure that has low on-resistance and good high-temperature characteristics while improving the high triggering voltage by applying an improved floating technology to the 4H-SiC grounded-gate n-type metal–oxide–semiconductor (GGNMOS) for 70-V applications. Electrical characteristics of the 4H-SiC-based conventional GGNMOS, floating-body NMOS, and the proposed ESD protection circuit were compared and analyzed using the transmission-line pulse test. To verify the high-temperature characteristics of the proposed 4H-SiC-based ESD protection circuit, its thermal reliability was measured at high temperatures (300–500 K). [ABSTRACT FROM AUTHOR]

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness. [ABSTRACT FROM AUTHOR]

The influences of three typical latch-up immunity structures, including high concentrated P++ doping layer, N+/P+ segmented emitter and P-sink well, upon electro-static discharge (ESD) robustness of the silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) devices are compared. The high concentrated P++ doping layer makes the SOI-LIGBT have the weakest ESD robustness, because the slow turn-on speed of parasitic n-p-n transistor brings long-time high power state and heat accumulation. The N+/P+ segmented emitter causes the SOI-LIGBT to own the medium ESD robustness and the SOI-LIGBT fails at the emitter side due to the crowded current made by the small N+ emitter region. For the P-sink well, it makes SOI-LIGBT exhibit the strongest ESD robustness, because the current can flow along the P-sink into the emitter vertically, which is helpful for reducing surface current density. Considering the comprehensive performances, the P-sink well is suggested as the latch-up immunity structure, which guarantees high latch-up immunity ability and strong ESD robustness simultaneously. [ABSTRACT FROM AUTHOR]

In this paper, electrostatic discharge (ESD) tests are performed on silicon carbide (SiC) MESFETs in order to understand their physical behavior and failure mechanisms during such stresses. The purpose is to point out advantages and drawbacks of this technology, paying special attention to aspects related to its possible commercialization and reliability. Three MESFETs designed to be integrated as a driver in monolithic SiC systems, featuring some ESD internal protection are investigated. Different configurations on ohmic and Schottky contacts are analyzed. Lock-in thermography is carried out for the physical failure location. With technology computer aided-design Sentaurus simulation, it allows to determine the nature of the defects on the damaged areas. Hypothesis on the failure mechanism as SiO2 breakdown or SiC sublimation are presented. Solutions to increase the ESD robustness, such as a Zener diode integration or the use of Al2O3 dielectric for passivation, are therefore proposed in this paper. [ABSTRACT FROM AUTHOR]

We demonstrate a PNP-based bidirectional ESD protection device with base bias controlled by two pMOS transistors, realized in a 0.18- \mu \textm CMOS process for 5–7 V applications. With respect to the conventional floating-base PNP device, very similar ESD performance is achieved. Due to the presence of extra parasitic diodes, the dc breakdown ( V\text {BD} ) and holding ( VH ) voltages are extended up to 8.0 and 7.6 V at 150 °C, respectively. Only a very limited area increase is needed and no extra mask is required for this implementation. [ABSTRACT FROM PUBLISHER]

The purpose of this paper is to investigate a method to derive component metal–metal electrostatic discharge (ESD) rating from its human body model (HBM) ESD rating. Symbolic computations and equivalent circuit simulations are used for this purpose. It can be seen from the components datasheets, that the machine model (MM) rating is often ten times less than the HBM rating. This paper proposes an explanation of this dependence derived from thermal failure physics. This paper presents a method of the ESD rating estimation based on injected power or charge analysis. This estimation method also could be applied for the CDM and charged board model (CBM) cases. We obtained a good correlation of HBM and MM ratings and a limited correlation of HBM and CBM/CDM ratings. The CBM case for power mosfet also was considered. [ABSTRACT FROM AUTHOR]

The electrostatic discharge robustness of indium–zinc–oxide thin-film transistor (IZO TFT) was investigated in this brief by employing a transmission line pulsed (TLP) test with different durations. A transition of operation region was observed in the TLP I–V characteristics which may be induced by space charge limited current effects. The experimental results show the breakdown in the long channel IZO TFTs only depends on the stress voltage level, which is related to the gate insulator. Furthermore, the evolution and mechanisms of prebreakdown degradation and latent failure were also presented. Due to hole trapping in the gate insulator and formation of localized states, threshold voltage decreases while electron field-effect mobility and subthreshold swing increase after TLP stress. Moreover, low-frequency noises (LFNs) before and after TLP stress were measured. Spatial distributions of trapped charges in the gate insulator were extracted based on LFN results. [ABSTRACT FROM PUBLISHER]

Gate-grounded tunnel field-effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. It has been reported that two current paths exist when the ggTFET is turned on under the ESD events. In this letter, the double current path phenomenon in ggTFETs is further investigated using TCAD simulation. It is found that the upper path is a hole current path, while the lower path mainly consists of electrons, and the grounded gate is a major factor that influences the double current path phenomenon. The heat and lattice temperature distributions in ggTFETs are also discussed. [ABSTRACT FROM AUTHOR]

In this letter, we investigate the robustness of silicon-on-insulator-based gate-all-around silicon nanowire transistors (GAA SNWTs) subject to electrostatic discharge (ESD) stress by thermal analysis and transmission line pulse measurements.. The thermal conductance modeling shows that heat dissipation, from channel to substrate through gate oxide, gate electrode, and buried oxide, dominates the thermal failure mechanism and thus the intrinsic ESD performance in GAA SNWTs. Accordingly, a new GAA SNWT is proposed and fabricated. A record failure current density of 18.8 mA/ \mu \textm is achieved at a nanowire diameter of 5 nm and a gate length of 500 nm. The impact of device parameters on ESD performance is also studied to give the guidance for the future ESD design with silicon nanowire transistors. [ABSTRACT FROM AUTHOR]

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip. [ABSTRACT FROM PUBLISHER]

Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach using 3-D TCAD has been presented for various superjunction (SJ) type DeMOS devices. In this context, how to effectively utilize the SJ concept in a DeMOS device for System on Chip applications, which often has stringent switching and RF performance targets, is explored in detail in this paper. Moreover, design and reliability tradeoffs for switching and RF applications are discussed, while considering two unique sets, one with fixed breakdown voltage and other with fixed ON-resistance. Finally, hot carrier generation, safe operating area concerns, and electrostatic discharge physics are explored and compared using 3-D TCAD simulations. [ABSTRACT FROM PUBLISHER]

A low-leakage electrostatic discharge power clamp with adjustable triggering voltage ( Vt1) is proposed in this paper. By enabling the static detection path using the transient one, the proposed clamp achieves a wide range of adjustable Vt1 while maintaining low standby leakage current ( I\text {leak}) , which overcomes the flaw of traditional static clamps. Besides, the adjustable Vt1 with low I\text {leak} is attractive for nanoscale applications. Moreover, the proposed clamp achieves enhanced false-triggering immunity over traditional transient clamps. The proposed clamp is successfully verified in a 65-nm CMOS process. Aside from silicon verifications, detailed comparisons with prior arts and practical application concerns are also addressed in this paper. [ABSTRACT FROM PUBLISHER]