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HfO2 based ferroelectric field-effect transistors (FeFETs) are promising for low-power and high-speed non-volatile memories. However, FeFETs can be susceptible to write disturbs due to their accumulative switching behavior, which limits their application in large scale memory arrays. Here we show that FeFETs with a thin HfO2 based ferroelectric and SiNx interfacial layer are immune to pulsed write disturbs under both ${V}_{\textit {dd}}$ /2 and ${V}_{\textit {dd}}$ /3 inhibit schemes, but not to continuous write disturb. This contrasts with previous reports which found no difference between pulsed and continuous write disturbs. Our findings suggest that accumulative polarization switching is not an intrinsic property of HfO2 based FeFETs, but might be related to charge trapping dynamics instead. [ABSTRACT FROM AUTHOR]

The ferroelectric field-effect transistor (FEFET) is an emerging nonvolatile memory technology that can offer ultra-scalability, fast operation, and reduced power consumption. However, a limited understanding of FEFET physics poses challenges for optimum device design. In this article, we provide physical insights into the operation of FinFET-based FEFETs (FEFinFETs) using a phase-field framework built on time-dependent Landau–Ginzburg (TDGL) thermodynamic theory. We exploit the source–drain fringing field to stabilize a monodomain configuration in the OFF state of short channel FEFinFETs. Based on recent experiments, we first analyze the switching dynamics of FEFinFETs with low remnant polarization (${P}_{r}$) and high coercive field (${E}_{c}$) hafnium zirconium oxide (HZO) FE. We find that the switching in these FEFinFETs occurs via domain nucleation and growth from the gate metal edges at the source–drain spacers. We also show that a non-zero drain bias can be used for dynamically modulating the memory window (MW) of FEFinFET to lower its power consumption. Furthermore, we find the spacer permittivity to be a crucial design parameter to control the MW and show that a lower spacer permittivity can significantly increase the MW. Finally, we show that the commonly held idea that a large ${P}_{r}$ leads to a large MW is not always valid. For a large ${P}_{r}$ , the formation of multiple domains in the FE layer can lead to a significant reduction in the MW. In addition, these devices can suffer from low write endurance due to exposure of the interfacial oxide layer to high electric fields. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistors (FeFETs) based on HfO2 are promising for low-power and high-speed non-volatile memory devices. However, most reported FeFETs show limited write endurance and significant read-after-write delay due to parasitic charge trapping. Here we show that n-type FeFETs with SiNx interfacial layer and high write endurance also exhibit immediate read-after-write behavior due to negligible charge trapping. This overcomes one of the major challenges faced by FeFET technologies today. [ABSTRACT FROM AUTHOR]

This work investigates the S-curve engineering by exploiting the anti-ferroelectric (AFE)/ferroelectric (FE) stack negative-capacitance FinFET (NC-FinFET) to improve both the subthreshold swing and ON-state current ($I_{\text {ON}}$). The capacitance matching and ON-state performance are evaluated using a short-channel AFE/FE stack NC-FinFET model. Our study indicates that the AFE/FE gate-stack can theoretically achieve surprising improvements to the OFF-state current ($I_{\text {OFF}}$) and $I_{\text {ON}}$ relative to International Roadmap for Devices and Systems (IRDS) projections. There is a significant long-term advantage to integrated circuit (IC) power consumption and speed if materials with certain AFE and FE characteristics can be developed and introduced into IC manufacturing. [ABSTRACT FROM AUTHOR]

We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 1010 cycles. The ferroelectric transistors (FeFETs) incorporate a high- $\kappa $ interfacial layer (IL) of thermally grown silicon nitride (SiNx) and a thin 4.5 nm layer of Zr-doped FE-HfO2 (HZO) on a ~30 nm silicon on insulator (SOI) channel. The device shows a ~1V memory window (MW) in a DC sweep of just ± 2.5V, and can be programmed and erased with voltage pulses of $\text {V}_{\text {G}}= \pm \,\,3\text{V}$ at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability. [ABSTRACT FROM AUTHOR]

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and 2 μm, in an inverter circuit. At 2-μm gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors. [ABSTRACT FROM AUTHOR]

Measurements on ultrathin body negative-capacitance (NC) field-effect transistors are shown to display subthreshold behaviors that cannot be explained as a classical MOSFET. Subthreshold swing (SS) at low drain bias decreases with increased gate bias for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the SS relative to control devices shows a nonmonotonic dependence on the gate length. Using a Landau–Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, we show that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement. The model predicts substantial scaling improvement at the end of the roadmap. [ABSTRACT FROM AUTHOR]

Gate-All-Around Field Effect Transistors (GAAFETs) for the future technology nodes will have highly confined channel cross-sections. Effects like subband separation and geometry dependent density of states result in kinks, peaks and valleys appearing in terminal characteristics like capacitance and transconductance. This has significant effect on the circuit linearity performance, in analog and RF domains. In this paper, we have proposed a design rule for the maximum allowed overdrive voltages or minimum silicon body width for a given body thickness so that the effects of subband separation may be avoided. Effect of corner radius has also been included. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate highly scaled, non-volatile memory transistors with ferroelectric Zr-doped HfO2(HZO) as gate insulator. ${\Omega }$ -gate transistors with gate length ~30 nm and width ~85 nm were fabricated on ~20 nm thick SOI. We demonstrate robust memory operation with ≤100 ns program and erase speed at ±5 V, projected memory retention time up to 10 years at 85 °C, and ~0.5 V memory window after 108 endurance cycles. The impact of ${V} _{\text {D}}$ on erase speed provides insights into the importance of holes on memory operation. [ABSTRACT FROM AUTHOR]

Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency (Ft) by ~10% and minimum number of substacks and minimum substack spacing should be used. [ABSTRACT FROM AUTHOR]

In this article, we will analyze and provide new insights into the polarization gradient effect of a ferroelectric using TCAD simulation and demonstrate how to model the polarization gradient effect using the negative capacitance FET (NCFET) compact model based on the BSIM framework. A larger value of g (the coefficient of polarization gradient effect) results in improved subthreshold slope, smaller OFF-current, smaller drain-induced barrier lowering (DIBL), and smaller output conductance. Inclusion of the polarization gradient effect in the NCFET compact model improves usability because it accurately captures the effects of negative DIBL and negative output conductance. [ABSTRACT FROM AUTHOR]

This article reports that the enhanced forward gate bias time-dependent dielectric breakdown (TDDB) reliability and interface quality are achieved in 5-nm ferroelectric Hf0.5Zr0.5O2 (HZO) technologies by using the NH3 plasma interfacial layer (IL) treatment and microwave annealing (MWA). An orthorhombic crystalline phase is observed in the annealed HZO film with NH3 plasma IL treatment and MWA, and NH3 plasma IL treatment can suppress Hf/Zr interdiffusion. Metal-oxide-semiconductor capacitors (MOSCAPs) subjected to NH3 plasma IL treatment and 2100-W MWA also have a higher extrapolated operating voltage for a ten-year lifetime at 0.01% failure and lower interface state density (Dit) compared to the devices subjected to only rapid thermal annealing (RTA) at 600 °C. Therefore, NH3 plasma treatment and MWA are effective for improving the TDDB reliability and interface quality of the ultrathin ferroelectric HZO. [ABSTRACT FROM AUTHOR]

The Negative Capacitance Field Effect Transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOSFET theory. This benefit arises from an effect which acts similarly to decreasing the equivalent-oxide thickness at short gate lengths. The effect is observed in both TCAD simulations and experiments, and is explained by the conjunction of the source/drain inner fringing field and the nonlinear polarizability of ferroelectric materials. The results present a sharp contrast to conventional scaling theory and bode well for extending the MOSFET gate length scaling limit. [ABSTRACT FROM AUTHOR]

The ability to partially switch an FeFET could enable their use as an embedded low-voltage memory and as analog weight storage in artificial neural networks (ANNs). We report on memory characterization of FeFETs gated with 5.5-nm Hf0.8Zr0.2O2, fabricated on fully depleted silicon-on-insulator using a self-aligned, gate last process. We find that for a single device, excellent elevated temperature retention, program/erase endurance, and read endurance are obtained; however, there is significant device to device variability in the response of the ferroelectric to a partially switching program pulse, which may require the use of feedback in programming. [ABSTRACT FROM AUTHOR]

We report on negative capacitance FETs (NCFETs) with a 1.8-nm-thick Zr-doped HfO2 gate oxide layer fabricated on an FDSOI wafer. Hysteresis-free operation is demonstrated. When compared to a baseline that uses HfO2 gate oxide with the same thickness, a subthreshold swing (SS) steeper by more than 20 mV/decade and larger than 10X reduction in the OFF current (${I}_{ \mathrm{OFF}}$) is observed at 30-nm channel length at constant ${I}_{ \mathrm{\scriptscriptstyle ON}}$. On the other hand, at matched ${I} _{ \mathrm{\scriptscriptstyle OFF}}$ , the NCFET provides a larger ON current at constant ${V}_{\mathrm {DD}}$. Our results indicate that the beneficial characteristic offered by the NCFETs can be obtained at scaled channel lengths, while using oxide layers whose thickness is comparable to the high- ${K}$ oxide layer used in ultra-scaled nodes. [ABSTRACT FROM AUTHOR]

1/ ${f}$ noise is characterized on thick and thin-gate oxide-based FinFETs for different channel lengths. The devices exhibit gate bias dependence in 1/ ${f}$ noise even in the weak-inversion region of operation which cannot be explained by the existing flicker noise model. We attribute this phenomenon to the non-uniform oxide-trap distribution in energy or space. Based on our characterization results for n- and p-channel FinFETs, we have improved the BSIM-CMG industry standard compact model for the FinFETs. The improved model is able to capture the 1/ ${f}$ noise behavior over a wide range of biases, channel lengths, fin numbers, and number of fingers. [ABSTRACT FROM AUTHOR]

The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate capacitance but also the drain current due to the additional gate control from the outer fringing field. It is found that in a heavily loaded circuit although the fin corner spacer improves the inverter propagation delay of the baseline FinFET, the NC-FinFET requires the fin selective spacer with the spacer height up to the ferroelectric thickness for better capacitance matching. When the wire capacitance is ~3 times larger than the gate capacitance, the inverter propagation delay of the NC-FinFET with the fin selective spacer can be improved by ~8% against the full spacer design. However, with the consideration of process complexity, the air spacer may still be attractive in the NC-FinFET, since it does not suffer from the amplified gate capacitance. [ABSTRACT FROM AUTHOR]

A new design to overcome the nonuniformity of capacitance matching along the channel of a negative capacitance field-effect transistor is presented in this letter. By introducing nonuniform oxidation, the thickness of SiO2 at the edge regions of the channel can be increased while maintaining the thickness of SiO2 at the center region of the channel. As a result, the capacitance along the channel becomes more uniform, and better capacitance matching between the dielectric and ferroelectric can be achieved. The Sentaurus TCAD results show improvement of matching in the center region and a significant boost of ON-current (20% improvement). [ABSTRACT FROM AUTHOR]

We investigate the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node. The 8-/7-nm technology node of the p-type body NC-FinFET is modeled using the Sentaurus technology-aided design (TCAD), which couples Poisson with Landau equations. It is found that the NC effect is beneficial for device scaling. The OFF current is well suppressed in short-channel devices (64.4% reduction at LG = 16 nm) because the inner fringing field induces negative gate charges and decreases the channel potential. For longer channel devices, the influence of inner fringing field disappears, and the depletion charges dominate the subthreshold characteristics. As reducing remnant polarization, the ON current is boosted (11.4% improvement at LG = 16 nm) for all lengths due to better matching between MOSFET and ferroelectric capacitances. In comparison with FinFET, the drain-induced barrier lowering of NC-FinFET is also well controlled (50% reduction at LG = 16 nm) due to the inner fringing field-induced gate charges, showing the scaling capability of NC-FinFET. Furthermore, a compact model to capture the spatial distribution of the inner fringing field is also proposed based on the Gaussian quadrature method, and it is validated with the TCAD simulated data with multiple gate lengths and remnant polarizations. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance (${C}_{\textsf {fe}}$) and the underlying MOS transistor (${C}_{\textsf {MOS}}$). Since both ${C}_{\textsf {MOS}}$ and ${C}_{\textsf {fe}}$ have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of ${C}_{\textsf {fe}}$. The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-threshold swing as well as lower power supply ${V}_{\textsf {dd}}$ compared with a prototype single-layer negative-capacitance field-effect transistor. [ABSTRACT FROM AUTHOR]

A lumped-circuit nonquasi-static (NQS) model, that is applicable for both large-signal transient simulations and a small-signal ac analysis, is developed in this paper. An improved physical equivalent circuit, capturing NQS effects in the millimeter waveband, is derived using a transmission line model, by incorporating the high-frequency longitudinal gate electrode and a channel distributed RC network. The proposed model is implemented in a BSIM-BULK MOSFET model and validated with dc and RF data, obtained from technology computer-aided design device simulations and experimental data. The proposed model is in very good agreement with the data up to ${50}{f}_{t}$. The transient currents, for a gate-voltage switching rate of ${5}\times {10}^{{10}}$ V/s, show excellent match with the data. The dc, transient, and ac simulations using the proposed model are much faster than a 10-segmented MOSFET model. This shows that the proposed model is better than other computationally complex compact models, for most RF applications. [ABSTRACT FROM AUTHOR]

We propose a new scheme to consider the dielectric (DE) phases inside polycrystalline ferroelectric (FE) materials. The scheme is used to extract material parameters from experimental polarization-electric field (P-E) measurements from the literature. A Sentaurus TCAD structure is constructed with the extracted parameters, and the simulated P-E curve is in a good agreement with the experimental data. Furthermore, variation of the device performance in a negative capacitance field-effect transistor (NCFET) due to the spatial distribution of DE and FE phases is studied using Sentaurus TCAD. It is found that the resultant variations of on and off currents can be up to 14.44% and 30.23%, respectively, thus showing the impact of inhomogeneous crystalline phases of the FE material on device performance. [ABSTRACT FROM AUTHOR]

Negative capacitance field-effect transistors (NCFETs) boost the electric field at the semiconductor-channel interface by virtue of the gate voltage amplification effect of a ferroelectric (fe) layer. NCFETs should be designed in such a way that this elevated field does not exceed the maximum electric field ( ${E}_{\max}$ ) determined by the reliability limit of the interfacial dielectric or NBTI/PBTI reliability. In this letter, a compact model-based methodology is presented to determine the NCFET design space considering several variables of the fe-layer and the baseline transistor, including the fe-layer thickness ( ${T}_{\mathrm {fe}}$ ), coercive field ( ${E}_{c}$ ), remnant polarization ( ${P}_{r}$ ), baseline transistor equivalent oxide thickness, supply voltage ( ${V}_{\mathrm {dd}}$ ), threshold voltage ( ${V}_{\mathrm {th}}$ ), and ${E}_{\max}$. Using this methodology, an NC-FDSOI transistor is designed in TCAD, and the result shows that even without raising the maximum interface field as compared with the baseline transistor, NCFET achieves much better ${I}_ \mathrm{\scriptstyle ON}/{I}_ \mathrm{\scriptstyle OFF}$ ratio and sub-threshold swing while operating at lower ${V}_{\mathrm {dd}}$. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

This letter presents a remote NH3/N2 plasma treatment after gate oxide deposition for improving the electrical characteristics and the reliability of In0.53Ga0.47As FinFET. The plasma treatment enhanced drive current ( I\textsf {DS} ), transconductance ( Gm ), subthreshold swing (SS), flicker noise, and positive bias temperature lifetime, suggesting that this plasma treatment significantly improves the quality of the etched In0.53Ga0.47As channel interface. In0.53Ga0.47As FinFETs and gate-all-around FETs were fabricated with the proposed in situ remote-plasma treatment and characterized. [ABSTRACT FROM PUBLISHER]

Negative capacitance (NC) FETs with channel lengths from 30 nm to 50~\mu \textm , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse drain induced barrier lowering characteristics of the NC operation. [ABSTRACT FROM PUBLISHER]

We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-annealing is necessary to induce the formation of the ferroelectric phase in this oxide stack, the integrity of the oxide/silicon interface must be preserved after high-temperature processing. As such, we show that a nitrided interlayer provides an improved midgap interface state density among all interfacial oxides investigated. Furthermore, we quantify the interface states using the ac conductance technique and model the interface trap distribution across the silicon bandgap in order to explain and verify the experimental measurements. [ABSTRACT FROM PUBLISHER]

The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data. [ABSTRACT FROM PUBLISHER]

We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 106, a read endurance of >10^10 read cycles, and a program/erase endurance of 107 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated. [ABSTRACT FROM PUBLISHER]

We present a compact model for source-to-drain tunneling current in sub-10-nm gate-all-around FinFET, where tunneling current becomes nonnegligible. Wentzel–Kramers–Brillouin method with a quadratic potential energy profile is used to analytically capture the dependence on biases in the tunneling probability expression and simplify the equation. The calculated tunneling probability increases with smaller effective mass and with increasing bias. We at first use the Gaussian quadrature method to integrate Landauer’s equation for tunneling current computation without further approximations. To boost simulation speed, some approximations are made. The simplified equation shows a good accuracy and has more flexibility for compact model purpose. The model is implemented into industry standard Berkeley Short-channel IGFET Model-common multi-gate model for future technology node, and is validated by the full-band atomistic quantum transport simulation data. [ABSTRACT FROM PUBLISHER]

In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases. [ABSTRACT FROM PUBLISHER]

Use of the Mo/Ti/AlN/HfO2 metal/dielectric stack to increase the permittivity of HfO2 for low power consumption InGaAs-based MOSFET is investigated in this letter. The dielectric constant of HfO2 was found to increase by 47%, from 17 to 25, after Ti doping without affecting the interface trap density around the mid-gap of the MOSCAPs. A strong inversion behavior with low leakage current for the MOSCAP was also observed. The gate voltage needed to tune the Fermi level of InGaAs channel was found to be smaller for the Ti-doped HfO2 sample as compared with the sample with un-doped HfO2. The increase of the dielectric constant of HfO2 after Ti doping combined with the use of Ti gate metal, which has the work function level near the conduction band edge of InGaAs, makes the proposed Mo/Ti/HfO2 (Ti) stack ideal for future lowpower consumption InGaAs-based NMOS applications. [ABSTRACT FROM AUTHOR]

We fabricate n-channel silicon bulk FinFET with silicon nitride (Si3N4) high- \kappa , silicon nitride/silicon dioxide dual- \kappa , and silicon dioxide (SiO2) low- \kappa spacers, and compare their performance using measurements and TCAD simulations. While all the three devices show similar dc performance, the ac and transient performance of low- \kappa spacer FinFET is better due to lower parasitic capacitance ( {C}_{\mathrm {par}} ). We show that {C} _{\mathrm {par}} in SiO2 spacer FinFET is about half of that with Si3N4 spacer. When the gate length is scaled, the contribution of C \mathrm {par} compared with the intrinsic capacitance ( C \mathrm {ox} ) increases. For FinFET with Si3N4 spacers, C \mathrm {par}/C \mathrm {ox} increases from 36% at 30-nm gate length to 105% when the gate length is scaled to 10 nm, while for FinFET with SiO2 spacers, the ratio changes from 19% to 55% making the latter more suitable for scaling. For SiO2 spacer FinFET, inverter delay is about 13% and 25% lower than Si3N4 spacer FinFET for gate lengths of 30 and 10 nm, respectively. [ABSTRACT FROM PUBLISHER]

We experimentally demonstrate n-channel bulk FinFET with encased air-gap spacers. Encased air gap in the spacer region is formed by depositing carbon sidewalls, encasing them with silicon nitride (SiN) film and finally removing carbon using mild oxygen plasma. We show that the drive current of air-spacer FinFET is improved by about 40% compared with the baseline bulk FinFET with SiN spacers likely due to enhanced tensile stress in the channel. The parasitic capacitance and ring oscillator delay of FinFET with air-spacers is about 25% and 40% lower compared with that with SiN spacers. [ABSTRACT FROM PUBLISHER]

To achieve low power consumption for CMOS devices, the gate metals must have effective work function (EWF) aligned with the band edges of the channel material and have a small WF variation (WFV). The multilayer TiNi alloys have been successfully applied as the gate metals for HfO2/In0.53Ga0.47As MOS devices in this paper. The EWF of TiNi alloys was found to increase from 4.41 eV for as-deposited sample to 4.62 eV after the alloy was annealed due to the diffusion of Ni atoms into Ti layer. The multilayer TiNi alloy remained amorphous phase with small WFV until annealed at 600 °C. The TiNi alloy is thermally more stable as compared with either Ti or Ni metal, because the TiOxNi interfacial layer prevents the diffusion of Ni atoms into HfO2 film and the further reaction of Ti with HfO2. The results can be applied for InGaAs nMOS fabrication. [ABSTRACT FROM PUBLISHER]

An electrostatic nonuniformity in the cantilever vertical tunneling FETs intrinsically exists in the InAs/GaSb junction to InAs cantilever transition region. The effects of the coupling ratio (CR) nonuniformity are investigated in this paper. The results show that the switching characteristics are degraded by the CR nonuniformity, especially in the case of large InAs/GaSb band offset. This paper also reveals that the nonuniformity in InAs/GaSb vertical tunneling FETs can be mitigated with the optimized band offset of heterojunction, scaling of oxide thickness, and acute angle etching profile. [ABSTRACT FROM AUTHOR]

In-situ plasma-enhanced atomic layer deposition (PEALD) technique was employed for device passivation to realize a high-performance inversion-mode HfO2/In0.53Ga0.47As metal–oxide–semiconductor field-effect transistor (MOSFET). Excellent quality of gate dielectric is enabled by utilizing the PEALD-aluminum nitride as a pre-gate interfacial layer, followed by a post-gate remote-plasma gas treatment. In-situ PEALD treatment led to enhanced dc characteristics, such as drain current, peak transconductance, subthreshold swing, OFF leakage current, and effective electron mobility. X-ray photoelectron spectroscopy analysis indicates a reduction of In- and Ga-related signals. Furthermore, small drain current hysteresis and low-interface state density ( $D_{{\mathrm {it}}}$ ) value confirm a high interfacial quality for the high-k/III–V structure. Overall, the PEALD passivation for HfO2/In0.53Ga0.47As interface shows a remarkable improvement on the MOSFET performance. [ABSTRACT FROM PUBLISHER]

We demonstrate p-channel gate-source/drain underlapped silicon FinFET with HfO2 high- $\kappa $ spacer and compare it with its counterpart having SiO2 low- $\kappa $ spacer. The HfO2 spacer structure reduces series resistance in the underlap regions due to the large capacitive coupling between the gate and the underlap regions. Both drain current and transconductance of p-channel FinFET are higher than those of the SiO2 spacer device by about $3\times $ when biased in the saturation region, and about $1.6\times $ and $2\times $ , respectively, when biased in the linear region. Subthreshold swing and drain-induced barrier lowering are also improved by incorporating the HfO2 spacer. [ABSTRACT FROM PUBLISHER]

In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained. [ABSTRACT FROM AUTHOR]

We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source–drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage ( V\mathrm{ DS}) , gate-to-source voltage ( V\mathrm{ GS}) , gate length ( LG) , substrate doping concentration ( N\mathrm{ sub}) , and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data. [ABSTRACT FROM AUTHOR]

We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length Lg=100 nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We show that a self-consistent simulation scheme based on Berkeley SPICE Insulated-Gate-FET Model:Common Multi Gate model and Landau–Devonshire formalism could quantitatively match the experimental NC-FinFET transfer characteristics. This also allows a general procedure to extract the effective $S$ -shaped ferroelectric charge–voltage characteristics that provides important insights into the device operation. [ABSTRACT FROM PUBLISHER]

We present a physics-based model of charge density and capacitance for III–V channel double-gate nMOSFETs. The developed model accurately accounts for the impact of quantum capacitance on gate capacitance with applied gate voltage including the steplike behavior with sub-band population. The presented model is in excellent agreement with the self-consistent Schrödinger–Poisson simulation data of InGaAs channel double-gate MOSFET. [ABSTRACT FROM AUTHOR]

We present a charge-based compact model for induced gate thermal noise for a fully depleted silicon-on-insulator transistor. The model uses front- and back-gate charges as well as the respective mobilities for the development of analytical expression. The model is implemented in Verilog-A and validated with experimentally calibrated TCAD simulations. The model predicts the high-frequency behavior with good accuracy while capturing the back-bias dependence. [ABSTRACT FROM AUTHOR]

A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm-thin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The overlap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 μA/μm2 at $V_{{\rm GS}} = V_{{\rm DS}} = 0.4$ V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K. [ABSTRACT FROM PUBLISHER]

By integrating 3-D nonplanar fins and 2-D ultrathin bodies, wavy FinFETs merge two formerly competing technologies on a silicon-on-insulator platform to deliver enhanced transistor performance compared with conventional trigate FinFETs with unprecedented levels of chip-area efficiency. This makes it suitable for ultralarge-scale integration high-performance logic at and beyond the 10-nm technology node. [ABSTRACT FROM PUBLISHER]

In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently. An experimental NC-FinFET device is accurately modeled and the experimentally calibrated parameters are used to analyze the NC-FinFETs device performance and its dependence on several key parameters. [ABSTRACT FROM PUBLISHER]