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In this letter, we present a compact model of ferroelectric field-effect-transistor (FEFET). The model consists of a ferroelectric (FE) capacitor model and a Berkeley Short-channel IGFET Model (BSIM), a standard SPICE MOSFET model. The FE model, similar to the nucleation-limited-switching model, is based on the statistical multidomain dynamics of FE materials. The charge equality between FE and MOSFET is satisfied through the SPICE simulator. The model reproduces the steep switching in the reverse bias region observed in experimental FEFETs and the current drop at both major loop and minor loop switching. A versatile inverted-memory-window (IMW) model can model the IMW behavior of FEFET that may be caused by charge trapping. We demonstrate that the reported model can accurately fit the published data of Fin-FEFET and FDSOI-FEFET under different bias conditions. [ABSTRACT FROM AUTHOR]

In this work, we propose using deep learning to improve the accuracy of the partially-physics-based conventional MOSFET current-voltage model. The benefits of having some physics-driven features in the model are discussed. Using a portion of the Berkeley Short-channel IGFET Common-Multi-Gate (BSIM-CMG), the industry-standard FinFET and GAAFET compact model, as the physics model and a 3-layer neural network with 6 neurons per layer, the resultant model can well predict IV, output conductance, and transconductance of a TCAD-simulated gate-all-around transistor (GAAFET) with outstanding 3-sigma errors of 1.3%, 4.1%, and 2.9%, respectively. Implications for circuit simulation are also discussed. [ABSTRACT FROM AUTHOR]

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and 2 μm, in an inverter circuit. At 2-μm gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors. [ABSTRACT FROM AUTHOR]

Measurements on ultrathin body negative-capacitance (NC) field-effect transistors are shown to display subthreshold behaviors that cannot be explained as a classical MOSFET. Subthreshold swing (SS) at low drain bias decreases with increased gate bias for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the SS relative to control devices shows a nonmonotonic dependence on the gate length. Using a Landau–Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, we show that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement. The model predicts substantial scaling improvement at the end of the roadmap. [ABSTRACT FROM AUTHOR]

Drain-extended MOSFET (DEMOS) with halo implant induced laterally asymmetric channel doping shows anomalous characteristics across bias and temperature that cannot be captured by existing models. The transconductance (gm) maxima in the linear region is found to be not only a function of the peak mobility but also the halo doping density. In the saturation region, the gm characteristics show a nonmonotonic “hump” induced by the halo-region/channel-region junction barrier. Another key care-about for analog design - the drain current (ID) mismatch, also exhibits unique characteristics with excess mismatch in the weak-inversion (WI) region, in particular at low temperature. In addition, the anomalous flicker noise (1/ƒ noise) trends in the presence of high-trap density in the halo region of halo-implanted DEMOS are also discussed. In this work, we propose an analytical model based on the equivalent conductance and impedance field theory to capture these effects. The proposed model is in good agreement with measurements and numerical device simulations using technology computer-aided design (TCAD) of DEMOS across a different oxide thickness, geometry, bias, and temperature. [ABSTRACT FROM AUTHOR]

Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits. The proposed metric can be used to gauge advances in future generations of semi-conductor technologies in a holistic way, by accounting for the progress in logic, memory, and packaging/integration technologies simultaneously. [ABSTRACT FROM AUTHOR]

We report Negative Capacitance nFETs with a ~ 1 nm effective oxide thickness (EOT) gate stack. Experimental measurements show a clear steepening of the slope of the ID-VG characteristic in the weak inversion regime, indicating that a capacitance matching takes place there. This leads to non-linear behavior of the current in the log scale, which is not observed in conventional devices. Such steepening in the weak inversion regime leads to a significant increase in the achievable current at a constant VDD. At LG = 50 nm, our transistors show a larger than 2X increase in the ON current. [ABSTRACT FROM AUTHOR]

The Negative Capacitance Field Effect Transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOSFET theory. This benefit arises from an effect which acts similarly to decreasing the equivalent-oxide thickness at short gate lengths. The effect is observed in both TCAD simulations and experiments, and is explained by the conjunction of the source/drain inner fringing field and the nonlinear polarizability of ferroelectric materials. The results present a sharp contrast to conventional scaling theory and bode well for extending the MOSFET gate length scaling limit. [ABSTRACT FROM AUTHOR]

A lumped-circuit nonquasi-static (NQS) model, that is applicable for both large-signal transient simulations and a small-signal ac analysis, is developed in this paper. An improved physical equivalent circuit, capturing NQS effects in the millimeter waveband, is derived using a transmission line model, by incorporating the high-frequency longitudinal gate electrode and a channel distributed RC network. The proposed model is implemented in a BSIM-BULK MOSFET model and validated with dc and RF data, obtained from technology computer-aided design device simulations and experimental data. The proposed model is in very good agreement with the data up to ${50}{f}_{t}$. The transient currents, for a gate-voltage switching rate of ${5}\times {10}^{{10}}$ V/s, show excellent match with the data. The dc, transient, and ac simulations using the proposed model are much faster than a 10-segmented MOSFET model. This shows that the proposed model is better than other computationally complex compact models, for most RF applications. [ABSTRACT FROM AUTHOR]

We present an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature. It is shown that the variation in drain current in different gate bias regimes results from the random-dopant fluctuations (RDFs) in different spatial regions across the channel of the device with nonuniform channel doping. Such effects cannot be captured by existing compact models. Using the impedance field method to calculate the relative contributions of the RDF in the higher doped halo region and the lower doped channel region, we demonstrate, for the first time, an analytical model that can successfully capture the drain current mismatch from subthreshold to strong inversion. We also report for the first time the unique temperature dependence of matching of the drain current in halo-implanted devices and propose a model to capture this behavior. The model is validated using extensive technology computer-aided design analysis and experimental data and is can be extended to the framework of the industry standard BSIM-BULK (formerly BSIM6) MOS model. [ABSTRACT FROM AUTHOR]

Presents information on a study which investigated the origin of the substrate current of a metal-oxide semiconductor field-effect transistor when the gate oxide undergoes Fowler-Nordheim stress. Experimental details; Results and discussion; Conclusions.

Presents information on hot-carrier-induced degradation of metal-oxide-semiconductor filed-effect transistors. Electron and hole trapping and interface-trap generation; Overview of electron-trapping efficiency of the group one device gate oxide; Generation of oxide traps by electron-hole recombination in the oxide.

This letter presents a remote NH3/N2 plasma treatment after gate oxide deposition for improving the electrical characteristics and the reliability of In0.53Ga0.47As FinFET. The plasma treatment enhanced drive current ( I\textsf {DS} ), transconductance ( Gm ), subthreshold swing (SS), flicker noise, and positive bias temperature lifetime, suggesting that this plasma treatment significantly improves the quality of the etched In0.53Ga0.47As channel interface. In0.53Ga0.47As FinFETs and gate-all-around FETs were fabricated with the proposed in situ remote-plasma treatment and characterized. [ABSTRACT FROM PUBLISHER]

The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data. [ABSTRACT FROM PUBLISHER]

In this paper, we report anomalous behavior of transconductance ( gm ) in halo implanted MOSFET for linear and saturation regions across both gate and body biases. The gm characteristics undergo sharp change of slope in saturation which cannot be modeled by conventional compact models. The cause of such behavior is identified and explained using the TCAD simulations of source side halo, drain side halo (DH), both side halos, and uniformly doped transistors. An analytical model, based on the equivalent conductance of the halo device, is developed to understand the gm behavior. It is shown that the commonly used approach where only the DH region is considered in saturation, is insufficient to model the atypical gm behavior. The effect of oxide thickness ( T\text {ox} ) variation on gm is also studied, which demonstrates a deviation from the conventional gm behavior for halo implanted devices with thicker T\text {ox} . A computationally efficient SPICE model is proposed to model gm characteristics which shows excellent matching with the measured data. [ABSTRACT FROM PUBLISHER]

We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau–Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET. [ABSTRACT FROM PUBLISHER]

In-situ plasma-enhanced atomic layer deposition (PEALD) technique was employed for device passivation to realize a high-performance inversion-mode HfO2/In0.53Ga0.47As metal–oxide–semiconductor field-effect transistor (MOSFET). Excellent quality of gate dielectric is enabled by utilizing the PEALD-aluminum nitride as a pre-gate interfacial layer, followed by a post-gate remote-plasma gas treatment. In-situ PEALD treatment led to enhanced dc characteristics, such as drain current, peak transconductance, subthreshold swing, OFF leakage current, and effective electron mobility. X-ray photoelectron spectroscopy analysis indicates a reduction of In- and Ga-related signals. Furthermore, small drain current hysteresis and low-interface state density ( $D_{{\mathrm {it}}}$ ) value confirm a high interfacial quality for the high-k/III–V structure. Overall, the PEALD passivation for HfO2/In0.53Ga0.47As interface shows a remarkable improvement on the MOSFET performance. [ABSTRACT FROM PUBLISHER]

We demonstrate p-channel gate-source/drain underlapped silicon FinFET with HfO2 high- $\kappa $ spacer and compare it with its counterpart having SiO2 low- $\kappa $ spacer. The HfO2 spacer structure reduces series resistance in the underlap regions due to the large capacitive coupling between the gate and the underlap regions. Both drain current and transconductance of p-channel FinFET are higher than those of the SiO2 spacer device by about $3\times $ when biased in the saturation region, and about $1.6\times $ and $2\times $ , respectively, when biased in the linear region. Subthreshold swing and drain-induced barrier lowering are also improved by incorporating the HfO2 spacer. [ABSTRACT FROM PUBLISHER]

In this paper, RF modeling and step-by-step parameter extraction methodology of the BSIM-IMG model are discussed with experimental data. BSIM-IMG is the latest industry standard surface potential based model for fully depleted silicon-on-insulator (FDSOI) transistors. The impact of gate, substrate, and thermal networks is demonstrated with S-parameter data, which enable the BSIM-IMG model to capture RF behavior of the FDSOI transistor. The model is validated over a wide range of biases and frequencies and excellent agreement with the experimental data is obtained. [ABSTRACT FROM AUTHOR]

We present a phenomenological model for subsurface leakage current in MOSFETs biased in accumulation. The subsurface leakage current is mainly caused by source–drain coupling, leading to carriers surmounting the barrier between the source and the drain. The developed model successfully takes drain-to-source voltage ( V\mathrm{ DS}) , gate-to-source voltage ( V\mathrm{ GS}) , gate length ( LG) , substrate doping concentration ( N\mathrm{ sub}) , and temperature ( $T$ ) dependence into account. The presented analytical model is implemented into the BSIM6 bulk MOSFET model and is in good agreement with technology-CAD simulation data. [ABSTRACT FROM AUTHOR]

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source–drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node. [ABSTRACT FROM PUBLISHER]

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX. [ABSTRACT FROM AUTHOR]

Reports the concept, design and demonstration of 50 nanometer thin-body silicon-on-insulator p-channel metal oxide semiconductor field effect transistors. Enhancement in drive current due to the incorporation of silicon-germanium in the channel; Device design considerations; Device fabrication; Device characterization.

We review the development of the anode hole injection (AHI) model for reliability projection of the silicon dioxide gate dielectric. The experimental and theoretical foundation of the AHI model is presented. Recent development and implications for the reliability of ultra-thin oxides are discussed. AHI is used to illuminate the questions of E versus 1/E models and field-driven versus voltage-driven models. Building on the concept of effective thinning, the AHI model is applied for the interpretation of defect-induced breakdown data and for optimizing oxide screening conditions. Circuit level reliability projection as a function of operating time, temperature, and power supply voltage is also illustrated. [ABSTRACT FROM AUTHOR]

Studies the high-performance P metal-oxide semiconductor field-electric transistors (PMOSFET) with sub-50-nanometer gate-length. Dimensions of FinFET structure; FinFEt device fabrication process; Device performance and discussions; Conclusions.

In this letter, we model future generation SiGe FinFETs using the industry standard compact model BSIM-CMG. BSIM-CMG is enhanced to model these aggressively scaled devices. It is found that in these narrow fin (fin width W\textrm {fin} = 12 nm) devices spacer region resistance behaves nonlinearly with drain-current. This nonlinear resistance behavior arises due to the saturation of carrier velocity in the spacer region. Accurate modeling of spacer region nonlinearity is important to predict the drain-current and the device transconductance. The developed model captures this phenomenon very well and produces excellent agreement with experimental data. [ABSTRACT FROM AUTHOR]

Studies the sub-quarter micron metal-oxide semiconductor field effect transistors (MOSFET's) and ring oscillators at supply voltage that can be predicted from a universal mobility model. Discussion of the development of analytical equations of electron and hole mobility; Prediction and interconnect loading effect; Conclusions.

In this letter, a macromodel for normally-off (enhancement mode) AlGaN/GaN-based FinFET (2-DEG channel at top with two MOS like sidewall channels) is proposed. AlGaN/GaN-based FinFET devices have improved gate control on the channel due to additional sidewall gates compared with planar structures, but device characteristics exhibit strong nonlinear dependence on fin-width. The proposed model captures both 2-DEG and sidewall channel conduction as well as the fin-width dependency on device characteristics. Model shows excellent agreement with state-of-the-art experimental data. [ABSTRACT FROM AUTHOR]

Investigates two process techniques, resist ashing and oxide hard mask trimming, which produce sub-30-nanometer metal-oxide semiconductor field-effect transistors (MOSFET) gate. Experiments and results; Conclusion.

A stack structure for the gate electrode of metal-oxide-semiconductor (MOS) transistors is proposed, analyzed, and simulated. The stack consists of a very thin polycrystalline silicon (polysilicon) layer and metal. By changing the thickness of the polysilicon layer, one can change the effective work function of the gate. Thus, the stacked-gate structure allows for a method to continuously adjust MOS field-effect transistor threshold voltage through gate work-function engineering while retaining the proven SiO[sub 2]/polysilicon interface. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

A simulator using a coupled Schro¨dinger equation, Poisson equation and Fermi–Dirac statistics to analyze inversion layer quantization is shown to match the measured capacitance versus voltage data of thin oxide gate metal-on-insulator capacitance closely. The effects of bias voltage, oxide thickness and doping concentration on the charge centroid are presented. A simple empirical model for the alternating current charge centroid of the inversion layer is proposed. This model predicts the in-version layer capacitance or charge centroid in terms of T[sub ox] (oxide thickness), V[sub t] (threshold voltage), and V[sub g] (gate voltage) explicitly. © 1998 American Institute of Physics. [ABSTRACT FROM AUTHOR]

In this paper, flicker noise behavior of lateral non-uniformly doped MOSFET is studied using impedance field method. Our study shows that Klaassen Prins (KP) method, which forms the basis of noise model in MOSFETs, underestimates flicker noise in such devices. The same KP method overestimates thermal noise by 2–3 orders of magnitude in similar devices as demonstrated in Roy et al. (2007). This apparent discrepancy between thermal and flicker noise behavior lies in origin of these noises, which leads to opposite trend of local noise power spectral density vs doping. We have modeled the physics behind such behavior, which also explain the trends observed in the measurements (Agarwal et al., 2015). [ABSTRACT FROM AUTHOR]

In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C – V and I – V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction. [ABSTRACT FROM AUTHOR]

Abstract: A turnkey, production circuit simulation ready compact model for cylindrical/surround gate transistors has been developed. The core of the model contains an enhanced surface potential based description of the charge in the channel. Analytical expressions for channel current and terminal charges have been derived. A method to account for quantum confinement in the cylindrical structure in a compact model framework is described. For the first time we present calibration results of such a model to a cylindrical gate technology that also exhibits asymmetric I–V characteristics. [Copyright &y& Elsevier]

Abstract: In this paper a computationally efficient surface-potential-based compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates is presented. A fully-depleted SOI MOSFET with a back-gate is essentially an independent double-gate device. To the best of our knowledge, existing surface-potential-based models for independent double-gate devices require numerical iteration to compute the surface potentials. This increases the model computational time and may cause convergence difficulties. In this work, a new approximation scheme is developed to compute the surface potentials and charge densities using explicit analytical equations. The approximation is shown to be computationally efficient and preserves important properties of fully-depleted SOI MOSFETs such as volume inversion. Drain current and charge expressions are derived without using the charge sheet approximation and agree well with TCAD simulations. Non-ideal effects are added to describe the I–V and C–V of a real device. Source-drain symmetry is preserved for both the current and the charge models. The full model is implemented in Verilog-A and its convergence is demonstrated through transient simulation of a coupled ring oscillator circuit with 2020 transistors. [Copyright &y& Elsevier]

Abstract: Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling and this leakage current density continues to increase for every process generation. Accurate compact models for gate-tunneling current and its source/drain partition are extremely critical to valid circuit performance in the 90nm technology or beyond. Gate current partition has been studied by several authors [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8; R. van Langevelde et al., Gate current: modeling, ΔL extraction and impact on RF performance, in IEDM Tech. Dig., Washington, DC, Dec. 2001. p. 289–92; Shih W-K, et al., “A general partition scheme for gate leakage current suitable for MOSFET compact models,” in IEDM Tech. Dig., Washington DC., Dec. 2001. p. 293–6]. In this paper, an insight on the common/difference of these different gate leakage current partition schemes into source/drain has been provided and the accuracy of BSIM4 [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8] partition scheme is confirmed with comparing to the new derived equation, which incorporates the gate current into the inhomogeneous term calculation. [Copyright &y& Elsevier]

This paper describes a unified framework to model the floating-body effects of various SOI MOSFET operation modes, including body-contacted mode, partially depleted mode and fully depleted mode. As the operation mode is dimension and bias dependent, different modes can co-exist in a single SOI technology. A smooth transit from one type of operation mode to another is thus essential and has been included in the model. In addition, the floating-body effects can couple to a number of other SOI specific phenomena such as heating assisted impact ionization, gate tunneling induced dynamic behavior, and operation mode dependent small signal output resistance. A methodology to model the overall SOI MOSFET behavior due to the combination of multiple floating-body related effects will also be described. [Copyright &y& Elsevier]

Normalized mutual integral difference operator (NMIDO), a novel experimental method for extracting the threshold voltage of MOSFETs, is presented in this paper. The basic principle of this method is to use the extreme spectrum characteristics of the NMIDO to find the threshold voltage. We have demonstrated numerically that this method is applied in the extraction of the threshold voltage of MOSFETs with different effective channel length and different parasitic series resistance cases. It has been shown that this method is sensitive to the channel length variation while insensitive to the parasitic resistance component. The extracted results on the threshold voltage of MOSFETs have also been compared with those obtained by the second-derivative method and the good agreement has been found, showing the advantage of the method presented here. [Copyright &y& Elsevier]