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In this work, a wafer-scale fabrication of biologically sensitive Si nanowire FET is demonstrated for pH sensing and electrical detection of DNA hybridization. Based on conventional “top-down” CMOS compatible technology, our bioFETs explore a wide range of design (nanowires [NW], nanoribbons [NR], and honeycomb [HC] structures) with opening access scaled down to only 120 nm. After device fabrication, I DS -V BG transfer and I DS -V DS output characteristics show a conventional n-type FET behavior with an I ON /I OFF value higher than 105, as well as an increase of threshold voltage as the NW width is reduced. Then, using a capacitive coupling in our dual-gated Si bioFETs, the pH sensitivity is enhanced with a pH response up to 600 mV/pH. Finally, the increase of threshold voltage of n-type SiNWs due to hybridized target DNA molecules is successfully detected.

In this paper, we experimentally demonstrate, for the first time, gate-all-around (GAA) nanosheet transistors with a record number of stacked channels. Seven levels stacked nanosheet (NS) GAA transistors fabricated using a replacement metal gate process, inner spacer and self-aligned contacts show an excellent gate controllability with extremely high current drivability $(3\mathrm{mA}/\mu \mathrm{m}\ \mathrm{at}\ \mathrm{V}_{\mathrm{DD}}=1\mathrm{V})$ and a 3 x improvement in drain current over usual 2 levels stacked- NS GAA transistors.

In this contribution, we report on the growth of Ge inside extremely thin 16-nm thick cavities through selective lateral growth of Ge on 300 mm silicon-on-insulator (0 0 1) substrates. We showed that the density of defects depends on the cavity shape, with extended defects such as micro-twins and stacking faults observed on the top surface along the 〈1 1 0〉 directions when the Si/Ge growth interface is along the 〈1 1 0〉 directions. The optimization of the cavity shape, by tuning the etching conditions, leads to a significant reduction of the defects in the Ge nanostructures, and this approach paves the road towards the co-integration of Si and Ge based devices.

3D sequential integration motivates the development of low temperature technological modules. Alternatively to classical non-selective annealing techniques, sub-microsecond laser annealing allows high temperature treatment of a sub-micrometer surface region while keeping the underneath structures at much lower temperature. In this contribution, we present recent advances in ultra-violet nanosecond laser annealing targeting monolithic 3D integration. Emphasis will be put on the demonstration of dopant activation in thin implanted SOI structures, simulating source and drain regions. Cu / ULK interconnects stability upon nanosecond laser annealing is also investigated.

For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high- $\kappa$ metal gate process and self-aligned-contacts. Back-biasing is herein efficiently used to highlight a drastic improvement of electrostatics in the upper GAA Si channels. Advanced electrical characterization of these devices enabled us to calibrate a new version of physical compact model (LETI-NSP) in order to assess the performance of ring oscillators for different configurations of GAA FETs integrating up to 8 vertically stacked Si channels.

In this contribution, we report on the growth of horizontal Ge nanowires inside extremely thin tunnels surrounded by oxide. This is achieved through selective lateral growth of Ge on silicon-on-insulator (001) substrates. The 16 nm high tunnels are formed by HCl vapor etching of Si followed by Ge growth in the same epitaxy chamber. First, the benefit of growing the Ge nanowires at high temperature was highlighted to homogenize the length of the nanowires and achieve a high growth rate. Afterwards, we showed that increasing the tunnel depth led to a significant reduction in the growth rate. Finally, transmission electron microscopy showed that no defects were present in the Ge nanowires. These results are encouraging for the planar co-integration of heterogeneous materials on Si.In this contribution, we report on the growth of horizontal Ge nanowires inside extremely thin tunnels surrounded by oxide. This is achieved through selective lateral growth of Ge on silicon-on-insulator (001) substrates. The 16 nm high tunnels are formed by HCl vapor etching of Si followed by Ge growth in the same epitaxy chamber. First, the benefit of growing the Ge nanowires at high temperature was highlighted to homogenize the length of the nanowires and achieve a high growth rate. Afterwards, we showed that increasing the tunnel depth led to a significant reduction in the growth rate. Finally, transmission electron microscopy showed that no defects were present in the Ge nanowires. These results are encouraging for the planar co-integration of heterogeneous materials on Si.

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

In this paper, we demonstrate low junction leakage for Fully Depleted Silicon On Insulator (FDSOI) devices fabricated with a low thermal budget (⩽650 °C), which commonly exhibit leakage problems due to the presence of defects in or close to depletion regions. We show through both experimental data and Kinetic Monte Carlo (KMC) simulations that the reduction of the film thickness and Raised Source Drain (RSD) allow the elimination of defects in critical regions in spite of the reduced thermal budget in the very early stage of the anneal. KMC simulations also show that defects are annealed-out in this critical region even for 500 °C anneals. Low temperature process appears then as a suitable process for advanced devices.

In this paper, the energy process window of nanosecond (ns) laser annealing for junctions activation has been determined for several dopants (As, P, BF2). The different recrystallization states observed when tuning laser energy density are explained by numerical simulations. Within these conditions, the laser impact on the thermal stability of ULK/copper inter-tiers interconnections has been evaluated for a 28nm node backend metal 1 design rules technology both from morphological and electrical perspectives. This study highlights the interest of ns laser anneal for CoolCube™ 3D integration.

In this brief, the hole transport properties of narrow-width germanium-on-insulator (GeOI) pMOSFETs are investigated. We report, for the first time, +65% low-field hole mobility enhancement in narrow-width (0.29-mum effective widthW eff) versus large-width (10- mum W eff) GeOI mesa-isolated devices. The observed enhancement, which is independent of the device length down to 90 nm, is attributed to improved sidewall transport properties resulting in higher hole mobility on the sides than on the top of the devices. At high inversion charge density N inv~ 1013 cm-2, + 55% hole effective mobility improvement is preserved. The top and side low-field mobilities ( mutop and muside, respectively) were extracted, showing + 90% mobility improvement at the sides (mutop = 125 cm2/V middots-1 and muside= 240 cm2/V middots-1).

P. Batude, M. Vinet, L. Clavelier, A. Pouydebasque, C. Tabone, A. Roman, L. Baud, V. Carron, F. Nemouchi, L. Sanchez, and S. Deleonibus. CEA-LETI, Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. perrine.batude@cea.fr 3D integration is regularly mentioned for its potential in decreasing interconnection delay, and for the density gain brought by stacking several transistors layers. An additional benefit of 3D integration lies in an independent optimization of n-FET and p-FET allowed by stacking entire p-FET onto n-FET layers. In this integration scheme, connecting the layers at the transistor scale is absolutely mandatory. 3D monolithic integration, with its high alignment performance fulfils this requirement whereas parallel integration falls short in this aspect (best alignment performance at 1 sigma ~0.5μm). To achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low TB (Thermal Budget) top FET still have to be solved. In this paper, a 3D monolithic process flow relying on molecular Wafer Bonding (WB) (fig.1) is proposed and breakthroughs in the critical steps are presented. It allows full enhancement of n and p-FET performance through material choice, strain options, surface and channel orientation and metal workfunction tuning. Note that WB, contrary to other techniques for upper thin film realisation based on recristallisation, offers the possibility to co-integrate different surface and channel orientations. Furthermore this mature process step leads to a high quality crystalline top film with low TB. For the top crystalline layer realization, a Ge or Si on insulator substrate is bonded at room temperature on the fully processed bottom transistor layer after planarization of its topology (fig.1(b)). A low temperature anneal (200°C) is performed to strengthen the bonding interface before mechanical substrate removal. The bonding is found of excellent quality with bonding energy of 900 mJm (mazzara method) and clean acoustic and infrared characterisation as shown in figure 2 (a,b) . Note that the Inter Layer Dielectric (ILD) thickness (fig.2(c)) is thinned down to 100 nm and allows dense 3D contacts. Indeed this additional depth, specific to 3D technology must be minimized to enable the contact scalability as its etching and filling become critical. To spare the bottom FET from high temperature anneal for top transistor dopant activation, which would have detrimental impact on its performance, SPE (Solid Phase Epitaxial) on thin SOI films (

session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube™) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.

Thanks to ultimate Si nMOSFETs with physical gate length down to 16 nm, the main challenges related to conventional transistors have been estimated. Short channel effect control is difficult below 40 nm due to the large TED of BF 2 halos. Nevertheless drain current higher than 800 μA/μm @ V d =1.5 V can be reached. Such performance is not a consequence of non-stationary effects since these are limited by the degradation of the low longitudinal field mobility on conventional short transistor. Ultimate transport is also analysed thanks to short and narrow devices. At low temperature, these MOSFETs are shown to operate like single electron transistors.

session: FDSOI; International audience; Low temperature (LT) activation on Fully Depleted Silicon On Insulator by SPER is needed for 3D sequential integration and also provides interest to obtain highly doped abrupt junctions in the standard planar technology. In this work, through the confrontation of electrical data and KMC process simulation we identify the efficient lever to optimize the low temperature device performance. This work evidences that the most suitable integration for LT FET implies a LDD implantation before the first spacer and the raised source drain epitaxy.

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

session 8: Beyond CMOS; International audience; We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si 1-x Ge x (x=0, 0.2, 0.25) nanowires, Si 0.7 Ge 0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W -3 dependence of ON current (I ON ) per wire. The fabricated devices exhibit higher I ON than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

This paper reviews how the evolution of FDSOI planar architecture towards Trigate Nanowires leads to a natural Single Electron Transistor and Field Effect Transistor convergence at room temperature. On one hand, this convergence sets up technological specifications to preserve CMOS operation. On the other hand it opens the path to room temperature hybrid circuits based on single electron transistors and MOSFETs. Further on, single electron effects can be downscaled to the ultimate single atom transistors and we demonstrate the practical performance of electron pumps for metrologic applications.

session Novel Process and Devices S8-04; International audience; In this paper, we address the problem of junction formation with a low temperature processing (≤ 600°C) through Solid Phase Epitaxial Regrowth. We present the main experimental achievements and suggest solutions to optimize the junctions. In particular, atomistic simulations based on kinetic Monte Carlo (kMC) method allow getting insight into the complex physical phenomena that take place during junction formation.

Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-/spl mu/m gate transistors up to 0.6-mm/sup 2/ capacitors). CVD TiN film as a damascene gate electrode shows excellent properties for MOS performances and gate oxide integrity even on ultrathin gate oxide (2-nm SiO/sub 2/).

We present in this letter the most aggressive dimensions reported to date in Ge-channel transistors: pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm). By improving both the Ge-enrichment technique and the transistor fabrication process, we demonstrate devices with controlled threshold voltage (Vth) and excellent short-channel effects. Moreover, the low defectivity and the very low thickness of the Ge film lead to a record drain OFF-state leakage for Ge-channel devices (< 1 nA/?m at VDS = -1 V) and thus, to the best ON-state to OFF-state current ratio (ION/IOFF ~5 × 105), even at Lg = 55 nm.

Thanks to a well-controlled CMOS FDSOI technology we have recently been able to demonstrate breakthroughs in the combined use of field effect and Coulomb blockade phenomena. On one hand, we have demonstrated room temperaturehybrid circuits based on single electron transistors and MOSFETs. On the other hand, we have shown the practical performance of electron pumps designed with a single silicided Coulomb island and MOSFETs as tunable barriers for metrologic applications.

In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.

Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

We report on ultrascaled (LG = 23 nm) compressively strained SiGe-based FDSOI pMOSFET with ultrathin body. The devices have been fabricated using a high-K metal gate (TiN/HfSiON) process flow. SiGe channels (3.4 nm) have been epitaxially grown on 3-nm thick 300-mm SOI wafers and combined with embedded Si0.7Ge0.3(:B) raised source and drain (RSD) for Vth,p tuning and smart strain management. Indepth electrical characterizations point out the +120-mV Vth,p tuning, the excellent short-channel, and DIBL control (similar to SOI reference), and show for the first time extremely low variability for SiGe-based FD pMOSFETs. Furthermore, we investigate hole-transport properties as a function of gate length and temperature and demonstrate 60% Raccess reduction with SiGe RSD and +330% mobility enhancement at 23-nm gate length with respect to 7-nm thick SOI reference.

We demonstrate the first Single Electron Transistor (SET) with high-k/metal gate operating at room temperature (at V D =0.9 V) cointegrated with fully depleted SOI (FDSOI) MOSFET (with 20 nm gate length) to realize a hybrid SET-FET circuit. Our resulting circuit exhibits typical SET oscillations upto record milliampere range. We also demonstrate a SET-FET based Negative Differential Resistance (NDR) device with 104 peak-valley-current-ratio and also a literal gate for multivalued logic applications.

For the first time we evidence the transition from a MOSFET operation to Single Electron Transistor (SET) behavior at 300 K in scaled nanowires (down to 5 nm width). In this paper we show that on scaling nanowire width from 20 nm down to 5 nm regime, together with achieving excellent short channel effect control (DIBL=12 mV/V for L G =20 nm), we hit a dramatic transition in transport mechanism from monotonously increasing to periodically peaked I D -V G 's. This transition is brought about by process induced channel potential variability (due to disorder) in nanowires and poses a challenge to further scaling. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at V D =±0.9 V!) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of beyond Moore devices.

We review the current status on DualChannel CMOS based on compressively strained SiGe channels for p-type and Si channels n-type MOSFETs: from the integration on fully depleted SOI wafers to the electrical performance (threshold voltage shift, low access resistance, large carrier mobility values...). Moreover SiGe layers are beneficial for tunnel FETs, specially for improving the ON current densities and the subthrehold slope.

We present for the first time Tunnel FETs obtained with a FDSOI CMOS process flow featuring High-K Metal Gate, ultrathin body compressively strained Si 1-x Ge x (x from 0 to 30%) based channels, and Si 0.7 Ge 0.3 Raised SD. We analyse the tunnelling improvements due to the different technological injection boosters: ultrathin body & EOT, strain, low band gap source, and low temperature SD anneal. For the first time, TFETs with large ON current (up to 428µA/µm) are demonstrated (with >x1000 I ON gain vs. SOI).

The main challenge of Low Temperature (LT) Solid Phase Epitaxy (SPE) is the dopant deactivation during post activation anneal. For the first time, we demonstrate that, for LT-SPE activated Boron (B) on thin SOI substrates, B deactivation can be well controlled during post anneal at 400 °C–600 °C. This is achieved by locating the preamorphization induced end of range defects close to the Buried OXide (BOX), thus benefiting from the defect cutting off and sinking effect of the BOX. This offers the opportunity to use LT-SPE activation for dopant activation of the bottom and top FETs in LT 3D sequential integration. In addition, this allows ultra shallow junction to effectively beneficiate from an activation which is higher with LT SPE than with conventional high temperature (HT) spike anneal (1050°C). LT SPE B-doped ultra shallow junction (∼10nm) with a sheet resistance of 900 Ω/┚ was achieved, fulfilling the ITRS requirement for device scaling, down to 22nm node (1100 Ω/┚).

International audience; In this paper, we demonstrate low junction leakage for devices fabricated at low temperature (≤ 650°C). This is explained by the reduced channel thickness of our device (6 nm). We show this through both experimental data and KMC simulations that enable to understand the origin of the leakage reduction.

A dual mode device has been realized with FDSOI MOSFET technology implementing both a single electron transistor (SET) and a field effect transistor (FET). The silicon substrate is used as a back gate to choose between these two functionalities. We show in this paper that the behavior of the device is determined by the position of the electron gas in the silicon mesa: the device is a SET if the electron gas is created by the top gate, and behaves as a FET when the back gate induces a electron gas at the bottom of the silicon mesa. This opens the possibility to design hybrid circuits exploiting both advantages of FETs and SETs.

We hereby present for the first time a successful integration of ultrathin (3.2nm) c-Si 0.8 Ge 0.2 layers in Fully Depleted (FD) SOI pMOSFETs (total body thickness: 7.8nm) combined with Si 0.7 Ge 0.3 (:B) Raised Source-Drain. Comparisons with SOI devices show that the c-Si 0.8 Ge 0.2 /SOI channels enable to tune the threshold voltage by +120mV (with excellent variability performance A Vt =1.47mV.µm) without SCE or DIBL degradation (60mV/V @ L=23nm). Moreover c-Si 0.8 Ge 0.2 /SOI combined with Si 0.7 Ge 0.3 (:B) RSD leads to significant gain in Access resistance (−60%), transconductance and I sat (+170% & +220% @ L=23nm).

Although single dopant signatures have been observed at low temperature [1–2], the impact on transistor performance of a single dopant atom at room temperature is not yet well understood. Here, for the first time, we provide an in-depth understanding of single dopant influence on NMOSFETs characteristics by linking low and room temperature transport. We demonstrate that, for gate length of 30 nm and below (channel length down to 10 nm), the presence of a single dopant dramatically alters the subthreshold behaviour when the dopant is located in the middle of the channel. Moving the dopants away from the channel leads to enhanced variability above the threshold voltage V t .

International audience; For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.

We fabricated SOI nanowire MOSFETs with a very small channel volume and few dopants between the highly doped source and drain. The ionization energy of these isolated As dopants can be extracted. We found a much higher energy than calculated value for As in bulk Si. This enhancement is due to the so-called dielectric confinement, because of the proximity of the buried oxide. Transport through this single dopant also enables probing the fluctuations of local density of states in the contacts.

For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4A of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.

We hereby report the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20nm. A wide range of experimental data for various device architectures (Single Gate, Single Gate on Ultra Thin Buried Oxide, Double Gate), S/D metallizations (Pt, Ni, Er, Yb), and doping conditions at the S/D-channel interfaces are analyzed in order to evaluate the trade-off between performance and Short-Channel Effects (SCE) control of metallic S/D MOSFETs for the sub-22nm nodes. We demonstrate pFET devices with promising electrical behavior (ION=790µA/µm; I OFF =60nA/µm @ V DS =-1.2V; L g =30nm), suitable for high performance applications. Excellent SCE control is also reported down to 30nm (DIBL=50mV/V), through the use of Double Gate transistors.

For the first time, an analytical model of an Accumulation-Mode Suspended-Gate MOSFET is proposed. For very low power operation, adhesion energies of gate and gate oxide as low as 130µJ/m2 are required as well as sub-2.3N/m doubly clamped gate. Experimentally a 0.2N/m suspended silicon nanowire was processed, opening perspectives for device downscaling.

We report in this paper the fabrirication and the characterirization of FDSOI pMOSFETs with metallic source and drain exhibiting the best performance obtained so far on metallic source/drain devices, with Ion=345µA/µm and Ioff=30nA/µm at −1V for a 50nm gate length device. These results have been achieved thanks to a careful optimization of the source/drain to channel contacts, which can allow specifific contact resistivities as low as 0.1 Ω.µm2.

We report here experimental investigations on GeOI pMOSFET: Besides the +65% mobility enhancement in narrow channel GeOI pMOSFETs as compared to wide channels, attributed to improved sidewall transport properties, 〈100〉 channel orientation transport is investigated for the first time in Ge (001): unlike Si, no current gain is observed compared to 〈110〉 channel orientation. Finally, ballisticity rates (BR) and source injection velocities (v inj ) were extracted, demonstrating 22% higher v inj in Ge than in Si.

With respect to Silicon-on-Diamond approaches as an alternative to SOI where diamond is used as the buried dielectric, we have in recent works demonstrated the feasibility of a novel approaches where the CVD diamond layer is grown on silicon using Bias Enhanced Nucleation (BEN) over large area substrates, then smoothed and assembled to successfully enable the fabrication of first prototypes of silicon-on-diamond substrates. The key novelty to those SOD substrates were that only a very thin box dielectric diamond layer is used (typically from 150 to 500nm thick), as required by the current SOI technology. However we had also observed that the silicon-diamond interface quality to be sensitive to the nature of the nucleation interface. Thus the current contribution here studies the chemical nature of various capping materials used to solve the issue of electrical defects in case of direct silicon-diamond interface and at the same time to enable the whole system to benefit from the high thermal conductivity of diamond when compared to other standard electrical insulating materials.

We report for the first time experimental investigations on SOI, Si1-xGexOI & GeOI Tunnel FET (TFET). These devices were fabricated using a Fully Depleted SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS. We successfully solve the TFET bipolar parasitic conduction by a novel TFET architecture, the Drift Tunnel FET (DTFET), with improved OFF state control. Concerning the ON current issue, we improve the SOI p (resp. n) TFET ION by a factor 55 (resp. 8) by source-drain profiles optimization (via spacers & extensions). Moreover, we demonstrate for the first time functional TFET & CMOS devices on Si1-xGexOI (x=15-30-100%) co-integrated with the same SOI process flow, enabling TFET ION continuous improvement with Ge content increase: ION x2700 for GeOI (compared to SOI).

We design and fabricate single-electron transistors and electron pumps within an industrial CMOS platform. Based on silicon nanowire transistors, these devices allow very simple and stable single-electron control thanks to doping modulation along the wire.

7th International Conference on Ultimate Integration on Silicon, Grenoble, FRANCE, APR 20-21, 2006; International audience; With the constant reduction of the transistor dimensions, new transport mechanisms in the conduction channels must be taken into account, as the quasi-ballistic transport. To realize how close to the ballistic limit a nanoFET operates, calculating the ratio of the mean-free-path to the critical length at the top of the source-to-channel barrier becomes an interesting investigation. After an introduction concerning the ballistic transport into the current devices, we will present the electrically characterized architectures and the methodology used to extract the backscattering coefficient (r(SAT)) for different gate lengths (10, 20 and 70 nm) and with temperatures ranging from 100 K to 290 K. We found that although the gate length is very small, the Double-Gate MOSFETs (DGMOSFETs) are not so close to the ballistic frontier (r(SAT) = 0). (c) 2007 Elsevier Ltd. All rights reserved.

Symposium on VLSI Technology 2007, Kyoto, JAPAN, 2007; International audience; For the first time, we have extracted the ballisticity rates of strained and unstrained n-Fully Depleted Silicon On Insulator devices with gate lengths down to 10nm. Thanks to a new fully experimental extraction methodology taking into account multi-subband population, we demonstrate that strain takes actively part in quasi-ballistic drain current improvement thanks to a 22% injection velocity enhancement, which will become the predominant transport parameter for the next generation of CMOS devices. In addition, we find that strained channel ballisticity rates are slightly greater than unstrained ones whatever the considered temperature and gate length. This rate improvement can be closely related to the mobility gain for short channel architectures.