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Due to severer transistor aging at nanoscale, circuit design margin becomes extremely tight for advanced technology nodes. Thus, reliability-aware circuit design is urgently needed. In this article, a new framework to perform aging-aware static timing analysis (STA) is presented for reliability analysis. The key parts of aging-aware STA flows are workload analysis and aged delay/transition calculation. For the workload analysis, a new analytical stress probability (SP) calculation model is proposed, which considers the floating effect and signal correlations. For aged delay/transition calculation, a new aging-aware model is developed, which is accessible to large industrial libraries. The results show that the proposed model achieves high accuracy in the degradation estimation and aged-path-delay calculation. Due to its high accuracy and scalability, the proposed framework is a promising solution that is compatible with commercial Electronic Design Automation (EDA) tools.

As CMOS devices become smaller, process and aging variations become a major issue for circuit reliability and yield. In this paper, we propose a new two-phase gate sizing approach in order to improve the reliability of the circuit considering the joint effect of process variation and transistor aging. In the first stage, the initial delay of the circuit is optimized to improve the timing yield of the circuit. Then, in the second stage, we reduce the delay degradation induced by aging and process variations. To this end, two novel concepts called aging probability and delay degradation-aware gate criticality are introduced which enable us to perform gate sizing efficiently using an adaptive multi-objective ranking approach. Experimental results based on ISCAS’85 and EPFL benchmark circuits show that, the proposed method achieves the 95 percent timing yield constraint and the 10 percent timing guard-band as the lifetime reliability constraint at the expense of 13.72 percent area overhead, on average. In comparison with the state-of-the-art methods, the proposed approach imposes lower area overhead with acceptable runtime.

Objectives: To study the use of simulation tool to understand the circuit behavior in presence of faulty component and use of part stress method for failure rate computation. Methods/ statistical analysis: The behavior of circuit under test (CUT) is studied in normal and faulty conditions using MATLAB simulation tool. Diode open circuit and short circuit faults are separately introduced to study the circuit performance. In developed prototype real faulty diode is purposely connected to verify the performance. After that reliability computation, part failure rates of components are estimated using military handbook MIL-HDBK- 217F of the CUT. Findings: In this work, a method is presented in which circuit performance in presence of faulty component is studied and individual component failure rates are estimated for reliability understanding. Close match in results of simulation tool and hardware prototype is observed. Such approach is good choice for understanding the behavior of power electronics circuit. Novelty/Applications: The proposed technique is useful in fault modeling of power supplies and power stations. Semiconductor power electronics devices are prone to failure, therefore reliability oriented designs of power supplies, converters, inverters and other power converting circuits is important issue. The component failure rates and circuit reliability should be estimated by using part stress method or suitable reliability estimating software. Individual component failure rates provide idea about long lasting behavior; fault precursors and fault signatures help to understand the circuit performance in presence of faulty component. Keywords: Component level fault study; simulation based fault diagnosis; simulation based fault signatures; component failure rate estimation; diode fault in rectifier

Bias Temperature Instability (BTI) is one of the most crucial reliability issues in modern CMOS technology. It leads to shift in device parameters, which eventually affect circuit performance. SRAM is a widely used circuit which occupies a considerable area in microprocessors. Hence it is important to understand the impact of BTI on performance/stability of SRAM. As device degradation due to BTI depends on gate activity, SRAM performance strongly depends on the data stored in the cell. In this paper, the gate activity is incorporated by activity factor ‘α’ which takes into account the various data patterns stored in the cell. Although many studies have reported the impact of BTI on SRAM performance, none focused on the worst degradation scenario. Our analysis with varying activity factor ‘α’ provides an opportunity to identify the data pattern for worst case degradation. Shift in threshold voltage due to BTI is modelled according to continuous and non-continuous applied gate bias, using physics-based compact model. Process variability is incorporated using Monte Carlo (MC) simulations and worst-case degradation at distribution tail is identified. In this paper, we consolidate various SRAM performance metrics from literature over the last three decades and demonstrate the impact of BTI and process variability with activity factor ‘α’ on these metrics.

Computing systems are conventionally designed to operate as accurately as possible. However, this trend faces severe technology challenges, such as power consumption, circuit reliability, and high performance. For nearly half a century, performance and power consumption of computing systems have been consistently improved by relying mostly on technology scaling. As per Dennard’s scaling, the size of a transistor has been considerably shrunk and the supply voltage has been reduced over the years, such that circuits operate at higher frequencies but nearly at the same power dissipation level. However, as Dennard’s scaling tends toward an end, it is difficult to further improve performance under the same power constraints. Power consumption has been a major concern, and it is now an industry-wide problem of critical importance. In addition to power, reliability deteriorates when the feature size of complementary metal–oxide–semiconductor (CMOS) technology is reduced below 7 nm, because parameter variations and faults at advanced nanoscales become difficult to control and prevent. Thus, to ensure the complete accuracy of signals, logic values, devices, and interconnects, manufacturing and verification costs will increase significantly.

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

Very Large Scale Integration (VLSI) based neuromorphic circuits also known as Silicon Neurons (SiNs) emulate the electrophysiological behavior of biological neurons. With the advancement in technology, neuromorphic systems also lead to various reliability issues and hence making their study important. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are the two major reliability issues present in VLSI circuits. In this work, we have investigated the combined effect of BTI and HCI on the two types of integrate-and-fire based SiNs namely (a) Axon-Hillock and (b) Simplified Leaky integrate-and-fire circuits using their key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. Proposed reliability-aware designs show negligible deviation in performance parameters after aging. The time-zero process variability analysis is also carried out for proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.

With the introduction of FinFET transistors, the Self-Heating Effect (SHE) became a major reliability challenge. In this work, we present an automated SHE estimation method integrated within a circuit reliability framework. It allows designers to study SHE in analogue and digital circuits. For accurate analysis, we employ electrically and thermally calibrated 14nm FinFET transistor models. To demonstrate the capabilities of our framework, we study SHE in standard cells and report a considerable dependence on the cell topology. We show how SHE can induce 15% delay increase in AND3 logic gate, highlighting the importance of taking SHE into account. Otherwise, reliability cannot be sustained during the circuit’s operation.

Due to the aggressive scaling of transistor dimensions, which took place in the last decades, chip devices are exposed to high electric fields and current densities during normal operation. These working conditions trigger degradation phenomena that compromises the device functionality and rises questions regarding circuit reliability. In this paper we present a simulation based methodology that incorporates the aging phenomena, which might allow to address the reliability aspects during the design phase and pave the way for further life-time projections at the design stage. Piecewise-linear functions are used to model the propagation delays and estimate the correlation between the different degradation mechanisms and the PVT variations.

With CMOS technology shrinking into nanoscale, the circuit design margin has become extremely tight due to the severer transistor aging and process variations. To relieve the circuit reliability problems, many design optimization methods have been proposed. In essence, all these methods trade off area/power /performance for reliability. In this paper, we present a new perspective to enhance design reliability: using emerging computing paradigms. As the preliminary attempts, three reliability-enhanced design flows based on approximate computing and/or stochastic computing are demonstrated. The results show that some emerging computing paradigms are inherently robust, or can trade off computing accuracy for reliability, which provides the designers with much more flexibility. It also indicates that emerging computing paradigms are very promising for circuit design with ultimately scaled CMOS and beyond CMOS devices.

This chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timing-critical components under severe impact of runtime variations. As flip-flops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the overall system lifetime. In the proposed method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe Bias Temperature Instability (BTI) impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop critical flip-flops of the circuit with optimized versions to improve the timing and reliability of the entire circuit in a cost-effective way. Simulation results show that incorporating the optimized flip-flops in a processor can prolong the circuit lifetime by 36.9%, which translates into better reliability.This chapter is organized as follows. Section 1 introduces wide-voltage operation reliability issues and motivates the proposed selective flip-flop optimization approach. The impacts of runtime variations on flip-flops are explained in Sect. 2. Consequently, Sect. 3 presents cell-level optimization of the flip-flops. The proposed selective flip-flop optimization methodology is described in Sect. 4, and optimization results are discussed in Sect. 5. Finally, Sect. 7 concludes the chapter.

Printed Circuit Board (PCB) plays an essential role as a basic unit of electronic products to realize certain functions. Therefore, it is necessary to evaluate its reliability in an accurate way to promote the design improvement for electronic products. In this paper, a Physics of Failure (PoF) based reliability simulation on a PCB product is carried out by using the RISA-PofEra software developed by Beihang University, China. During the simulation analysis, thermal and vibration stress profiles over the PCB were exerted to provide inputs of a couple of PoF models for the reliability calculations of semiconductor devices on that PCB. Meanwhile, with the consideration on geometrical uncertainties in semiconductor packages, the Meantime Time to Failure (MTTF) of the PCB is calculated from the lifetimes of its weakest semiconductor device by using a Monte-Carlo method.

With the dimension of transistor scaling down to 3nm, device and circuit reliability attract increasing attentions in digital and analog design. Self-heating effects must be taken into account due to the introduction of FinFET structure, which will be more serious with thinner and higher Fin shape optimization and future GAA device. Self-heating related qualification is also critical, since it may impact the HCI, EM and TDDB. In addition, layout dependent effect is another important issue and is found to be more serious in smaller dimension. Finally, aging induced variation has also been shaving away the design margins, especially in SRAM, this effect is studied systematically in this paper.

The growth in Artificial Intelligence, advanced 5G wireless network, cloud computing, safety-critical automotive electronics and mainstream adoption of FinFET technologies have resulted in significant increase in IC design robustness challenges. IC designers must contend with advanced circuit complexity with stringent requirements on performance, low power, design robustness for safety, and reliability such as electro-migration and device-aging. For safety-critical applications such as Autonomous Driving, ADAS, and Connected Car, IC designers are now looking to adopt rigorous and systematic methodologies to meet functional safety standard. In this paper, we will discuss the models used on circuit reliability verification, and application of these models to assess IC reliability and variability for targeted requirements with latest Synopsys' AMS solution for robust design.

In the past few years, Time-Dependent Variability has become a subject of growing concern in CMOS technologies. In particular, phenomena such as Bias Temperature Instability, Hot-Carrier Injection and Random Telegraph Noise can largely affect circuit reliability. It becomes therefore imperative to develop reliability-aware design tools to mitigate their impact on circuits. To this end, these phenomena must be first accurately characterized and modeled. And, since all these phenomena reveal a stochastic nature for deeply-scaled integration technologies, they must be characterized massively on devices to extract the probability distribution functions associated to their characteristic parameters. In this work, a complete methodology to characterize these phenomena experimentally, and then extract the necessary parameters to construct a Time-Dependent Variability model, is presented. This model can be used by a reliability simulator.

Total ionizing dose tolerance is one of the essential features of the electronic devices used to control and monitor the vital operations in extreme environments. Most of today’s commercial off-the-shelf systems do not have this capability unless they are shielded with at least 10 cm of tungsten. Hence, application-specific integrated circuits (ASICs) are developed to achieve the desired performance in extreme environments. In this paper, a new ASIC structure with self-repair capability has been proposed using the field-programmable nanowire interconnect architecture. Our proposed structure includes a nonprogrammable part as circuit functionality and a reconfigurable part to improve the circuit reliability. The performance of the proposed structure is compared with some static and dynamic fault-tolerant approaches. According to the simulation results, the proposed structure can tolerate several permanent faults during the run time with minimum delay, power consumption, and area overhead.

Fast Orbit Feedback System (FOFB) can be installed in a synchrotron light source to eliminate undesired disturbances and to improve the stability of beam orbit. The design and implementation of an accurate and reliable Fast Corrector Power Supply (FCPS) is essential to realize the effectiveness and availability of the FOFB. A reliability assessment for the FCPSs in the FOFB of Taiwan Photon Source (TPS) considering MOSFETs’ temperatures is represented in this paper. The FCPS is composed of a full-bridge topology and a low-pass filter. A Hybrid Pulse Width Modulation (HPWM) requiring two MOSFETs in the full-bridge circuit to be operated at high frequency and the other two be operated at the output frequency is adopted to control the implemented FCPS. Due the characteristic of HPWM, the conduction loss and switching loss of each MOSFET in the FCPS is not same. Two of the MOSFETs in the full-bridge circuit will suffer higher temperatures and therefore the circuit reliability of FCPS is reduced. A Modified PWM Scheme (MPWMS) designed to average MOSFETs’ temperatures and to improve circuit reliability is proposed in this paper. Experimental results measure the MOSFETs’ temperatures of FCPS controlled by the HPWM and the proposed MPWMS. The reliability indices under different PWM controls are then assessed. From the experimental results, it can be observed that the reliability of FCPS using the proposed MPWMS can be improved because the MOSFETs’ temperatures are closer. Since the reliability of FCPS can be enhanced, the availability of FOFB can also be improved.

In this study a careful analysis of the device and the circuit level variability and reliability are presented. Planar 20 nm System on Chip (SoC), 16 nm FinFET (16FF) and 10 nm FinFET (10FF) devices are studied to understand the time-zero process variability and Bias Temperature Instability (BTI) stress induced (time dependent) threshold voltage (VT) variations to evaluate the device degradation. Moreover, to understand the circuit level variability, the 6-Transistor (6T) SRAM performance is assessed in terms of the static noise margin (SNM) degradation under the influence of BTI stress. Finally, the product level SRAM performance is studied in terms of the minimum SRAM operating voltage (Vmin) degradation.

With the downscaling of CMOS devices, dynamic variability induced by negative bias temperature instability (NBTI) has become a critical issue. In addition to the time-dependent device-to-device variation (DDV) of NBTI degradation, the cycle-to-cycle variation (CCV) originated from random trap occupation is found non-negligible and should be added into the total dynamic variation. This paper summarizes our recent studies on NBTI-induced dynamic variability, focusing on the CCV effect, with more details on the statistical modeling, circuit reliability simulation methodologies and experimental results. By adding the random trap occupation into consideration, a statistical model for total dynamic variation (DDV + CCV) is proposed. The effective occupancy probability peff is introduced as a key parameter for modeling and circuit reliability simulation. With the statistical trap response (STR) method and modified on-the-fly method, the proposed model is validated by the experimental evidence under both DC and AC NBTI. According to the model and experimental results, circuit reliability simulation framework is proposed for both long-term quasi-static and short-term transient performance evaluation with the additional impact of CCV. Two representative digital circuit units, ring oscillator (RO) and SRAM cell, are simulated under different conditions, indicating it necessary to consider the evident influence of the CCV in accurate circuit reliability evaluation. The results are helpful for the reliability/variability-aware circuit design in nanoscale technology.

Resistive switching memories (RRAMs) are one of the most promising alternatives for nonvolatile storage and nonconventional computing systems. However, their behavior, and therefore their reliability, is limited by technology intrinsic constraints. Standard CMOS reliability analyses do not take into account RRAM-related misbehaviors. Consequently, new and more thorough characterization approaches are needed. Even more important, as RRAM is proposed to become a key piece in aerospace solutions, new radiation and temperature analyses should also be considered in reliability-oriented methodologies. This work presents a solution that completely characterizes RRAM and CMOS hybrid circuits under the combined effects of both technology and environmental error sources. The analysis strategy is based on three pillars: the definition of suitable models, the application of user-defined metrics to measure both circuit reliability and performance, and the efficient definition of the design space. These concepts are used by a powerful simulation framework, achieving automatic characterization of RRAM-based circuits by simultaneously considering multiple error sources. As a case of study, a thorough analysis of an RRAM read driver, including RRAM lifetime, circuit temperature, CMOS and RRAM variability, and radiation—both accumulated dose and single particle impacts—highlights the proposed approach capabilities.

In this study, a single-stage quasi-resonant (QR) AC–DC converter based on buck–boost and flyback circuits is proposed. The forestage buck–boost circuit works in discontinuous conduction mode to achieve a high-input power factor (PF), and the backstage flyback converter, working in QR mode, is responsible for energy transfer. The QR switch mode can improve the efficiency of the converter by decreasing the switch turn-on losses. The single-stage topology can reduce the cost and raise the reliability of the system. The detailed design process is described in this study, and a 50 W prototype was developed that has a maximum PF higher than 0.99 and a maximum efficiency of 90.91% in nominal working conditions.

Reliability mechanisms are undesirable from a product lifetime point of view, but their unique characteristics enable novel applications such as one-time-programmable memory, secure chip odometers, and physical unclonable functions (PUFs). In this invited paper, we will discuss how reliability mechanisms can be leveraged for the aforementioned applications, and then introduce a novel SRAM PUF design where the power up state of the SRAM cell is programmed into a local metal fuse using the electromigration phenomenon for improved stability.

CMOS wear-out mechanisms, especially bias temperature instability (BTI), cause growing concerns about circuit reliability. For a logic circuit, the BTI effect increases signal delays, eventually leading to timing violations. Due to the increased demand for circuit density, logic synthesis is currently a significant EDA process to design a circuit with many millions of transistors. Traditional synthesis process does not specifically consider the ageing effects. To ensure reliable operations during the expected lifetime of a circuit, it is necessary to incorporate BTI analysis and optimizations into logic synthesis. This chapter presents case studies about how state-of-the-art techniques can be used to enhance BTI lifetime reliability during synthesis and discusses the advantages and drawbacks of each type of methods.

Logic circuits based on Resistive RAM (RRAM) devices and the material implication logic (IMPLY) are promising solutions for low-power logic-in-memory (LiM) architectures. Still, their diffusion is limited by their high design complexity resulting from device and circuit non-idealities. These non-idealities are usually overlooked in the design phase when using simplified RRAM models, thus leading to unreliable designs. In this work, we derive correct design strategies for reliability of RRAM-based LiM circuits and quantitatively evaluate circuit performances using a physics-based compact model.

Negative bias temperature instability (NBTI) is an significant reliability problem that can affect circuit performance. This paper presents an investigation of reliability on standard cell library circuit performance based on R-D model. Predictive Technology Model (PTM) and HSPICE MOSRA were used for circuit reliability study. Low Power (LP) PTM model of 32nm was used in this simulation. The delay time, threshold voltage and average power were investigated with the existence of the NBTI problems. The time exponent of the threshold voltage shift shows that the defect mechanisms consist of interface trap, Nit or combination of Nit and oxide trap, Not. The propagation delay increased as the aged year increased. The average power not affected due to the NBTI effect.

High voltage tole rant IO interface provides an efficient and flexible solution for integrated multimedia application. In this paper, we studied the design for reliability of IO interface in advanced technology node. Three different approaches, which is from device, layout and circuit point of view, to enhance the IO overdrive circuit (IP) reliability are investigated. We successfully develop a LDMOS that is compatible with advanced process and provides good reliability. However, new device development is a time consuming process. To reduce time-to-market, two solutions are proposed. 1) Taking the advantage of reverse body bias effect to reduce HCI damage on IP level. It can be achieved by implementing deep N-well. 2) Reducing the overstress voltage on devices by bias tracing circuit. Finally, we compared the IO interface performance and area of each solution. The solution with bias tracing circuit exhibits good reliability to sustain 5V stress and provides 66% area reduction.

In this paper, the NBTI-induced circuit frequency degradation is found having a non-monotonic bias dependence, thus an optimal V DD can be assessed based on this reliability tradeoff. As a demonstration, based on our recently-developed compact aging model and circuit reliability simulator, NBTI-induced frequency degradation in inverters are simulated, in terms of various V th and V DD , considering two typical stress waveforms. The results show the relationships between the optimal V DD of circuit and various stress conditions, which are useful to the reliability-aware V DD optimization for CMOS technology.

For modern semiconductor product design, reliability aspects have to be considered not only for technology process development but inevitable also during circuit design phase. Electronic design automation tools (EDA) have to support circuit designers to analyze the impact of device and interconnect reliability on the circuit behavior. The designers task is to ensure the specified characteristic of the circuits throughout the entire lifetime of the product. Meanwhile there are many different tools available for this task. They can be categorized according to their basic reliability assessment approach.

With technology scaling, the susceptibility of circuits to different reliability degradations is steadily increasing. Aging in transistors due to bias temperature instability (BTI) and voltage fluctuation in the power delivery network of circuits due to IR-drops are the most prominent. In this paper, we are reporting for the first time that there are interdependences between voltage fluctuation and BTI aging that are nonnegligible. Modeling and investigating the joint impact of voltage fluctuation and BTI aging on the delay of circuits, while remaining compatible with the existing standard design flow, is indispensable in order to answer the vital question, “what is an efficient (i.e., small, yet sufficient) timing guardband to sustain the reliability of circuit for the projected lifetime?” This is, concisely, the key goal of this paper. Achieving that would not be possible without employing a physics-based BTI model that precisely describes the underlying generation and recovery mechanisms of defects under arbitrary stress waveforms. For this purpose, our model is validated against varied semiconductor measurements covering a wide range of voltage, temperature, frequency, and duty cycle conditions. To bring reliability awareness to existing EDA tool flows, we create standard cell libraries that contain the delay information of cells under the joint impact of aging and IR-drop. Our libraries can be directly deployed within the standard design flow because they are compatible with existing commercial tools (e.g., Synopsys and Cadence). Hence, designers can leverage the mature algorithms of these tools to accurately estimate the required timing guardbands for any circuit despite its complexity. Our investigation demonstrates that considering aging and IR-drop effects independently , as done in the state of the art, leads to employing insufficient and thus unreliable guardbands because of the nonnegligible (on average 15% and up to 25%) underestimations. Importantly, considering interdependences between aging and IR-drop does not only allow correct guardband estimations, but it also results in employing more efficient guardbands.

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS technologies for digital, analogue and RF designs. However, it has been demonstrated by several researchers that TFET circuits face increased on-state Miller capacitance effect, which leads to poor transient characteristics with large overshoots and undershoots. This would minimise the reliability of TFET circuits though energy efficient. This work gives more design insights (optimal sizing, number of stages, supply voltage) into TFET circuit reliability and proposes a TFET based circuit interaction design approach for ultra-low power and reliable ring oscillator circuit design. It has been shown that TFET circuit designs without proper reliability enhancement techniques such as circuit interaction or co-design approach exhibits very large undershoots/overshoots (∼20–50%). The proposed TFET circuit co-design approach (i.e. differential topology based design in comparison with the complementary static TFET logic designs) enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade-off in operating frequency and power consumption.

As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability-related variability) is an emerging concern that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects. The properties of gate oxide defects are discussed. It is further shown how in particular the electrical properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits.

Metal gate/high-k stacks are in CMOS manufacturing since the 45 nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.

An assessment on magnetic tunnel junction (MTJ)/CMOS hybrid circuit reliability is given from the designers point of view, with an advanced fully depleted silicon-on-insulator (FD-SOI) and bulk CMOS. Selected nonvolatile circuit blocks are investigated with respect to power efficiency, sensing latency, process variation and aging degradation. By integrating physical models of reliability issues, related CMOS aging behavior and MTJ compact model are compatibly simulated. The performance fluctuations and degradations of hybrid MRAM circuits are estimated. Simulation results reveal that MRAM-on-FDSOI structure with reliability knobs show improved energy efficiency comparing to MRAM-on-bulk CMOS. The proposed circuit-level design strategies are effective to enhance the performance especially for MRAM-FDSOI integration, which can alleviate process variation and aging induced failure probability.

In current CMOS advanced technology nodes, accurate extraction of transistor parameters affected by time-dependent variability, like threshold voltage (Vth) and mobility (μ), has become a critical issue for both analog and digital circuit simulation. In this work, a precise VTH0 and U0 BSIM parameters extraction methodology is presented, together with a straightforward IDS to VTH0 shift conversion, to allow the complete study of device aging effects for reliability circuit simulation.

One of the most interesting challenges in power electronics is increasing the circuit reliability. This can be achieved by reducing the power losses and, therefore, increasing the power conversion efficiency. Conduction and switching losses in power MOSFETs are the major contributions to the converter overall power loss, which becomes a serious problem in high-power conversion applications. Resonant converters, which represent an interesting solution to reduce switching losses, are based on a resonant tank composed of inductors and capacitors tuned to resonate at a specific frequency. The resonance forms the voltage and/or current waveforms so that, under optimal conditions, the MOSFET turns on at zero-voltage switching (ZVS) and zero-derivative switching (ZCS). This drastically reduces the switching losses. Also, new semiconductor materials such as SiC or GaN are capable to operate at an increased switching frequency and reduced both conduction and switching losses. In this paper, the reliability of a Class-E resonant inverter is analyzed to identify the most critical elements of the circuit. The reliability prediction has been carried out based on MIL-HDBK-217 handbook. The Mean Time Between Failures (MTBF) and the failure rate λp are derived. Voltage and current values of all components utilized in this analysis are based on data achieved by experimental results.

The degradation predicted by classical DC reliability methods, such as bias temperature instability (BTI) and hot carrier injection (HCI), might not translate sufficiently to the AC conditions, which are relevant on the circuit level. The direct analysis of circuit level reliability is therefore an essential task for hardware qualification in the near future. Ring oscillators (RO) offer a good model system, where both BTI and HCI contribute to the degradation. In this work, it is qualitatively shown that the additional off-state stress plays a crucial role at very high stress voltages, beyond upper usage boundaries. To yield an accurate RO lifetime prediction a frequency measurement setup with high resolution is used, which can resolve small changes in frequency during stress near operation conditions. An ACDC conversion model is developed predicting the resulting frequency change based on DC input data. From the extrapolation to 10 years of circuit lifetime the model predicts a very low frequency degradation below 0.2% under nominal operation conditions, where the off-state has a minor influence.

VK: Orponen, P.; NC Due to its programmable nature, DNA nanotechnology is currently one of the most advanced and most reliable self-assembly-based methodologies for constructing molecular-scale structures and devices. This makes DNA nanotechnology a highly promising candidate for generating radically new manufacturing technologies. Our specific interest is in the use of DNA as a template and scaffold for the self-assembly of carbon-nanotube field effect transistor (CNFET) circuits. In this paper, we introduced a novel high-level design framework for self-assembling CNFET circuits. According to this methodology, the elements of the circuits, i.e., CNFETs and the connecting carbon nanotube wires, are affixed on different rectangular DNA scaffolds, called tiles, and self-assemble into the desired circuit. The introduced methodology presents several advantages, both at the design level, and for analyzing the reliability of these systems. We make use of these advantages and introduce a new fault-tolerant architecture for CNFET circuits. Then, we analyze its reliability both by computer simulations and by analytical methods.

Thermal management is one of the important issues of 3D IC integration. So, effective thermal management methodologies and solutions are needed for widespread use of 3D IC integration. The thermal analysis is an important as from the thermal and stress distribution, layout modification can be done and thus enhance the circuit reliability. The thermal issue of a 3D IC is much severer than that of a 2D IC. The cause is that the ambient environment of the die of a 2D IC is the cooling material, but the ambient environment of a die within a 3D IC may be another die that also generates heat. Therefore, Thermal management in 3D ICs is critical for maintaining required reliability, performance, and power dissipation target. Therefore, new cooling techniques must be innovated to ensure that the chip can operate at temperatures and performance required for reliability. This paper presents a survey on 3D-ICs modeling, analysis, and management techniques.

Device variability and reliability are becoming increasingly important for nano-CMOS technology and circuits, due to the shrinking circuit design margin with the downscaling supply voltage (V dd ). Therefore, robust design should have the awareness of both variability and reliability. In FinFET technology, strong correlation between the variations of device electrical parameters is found, due to the larger impacts of line-edge roughness (LER) in FinFET structure. Accurate compact models and new design methodology for random variability in FinFETs were proposed for the variation-and correlation-aware design. For the reliability awareness, the impacts of BTI-induced temporal shift and the layout dependent aging effects should be taken into account for the optimization of end-of-life (EOL) performance/power/area (PPA). New-generation aging model and circuit reliability simulator for FinFETs were proposed and developed in industry-standard EDA tools. Future challenges are also pointed out, such as statistical BTI and RTN. The results are helpful for the robust and resilient design for 16/14nm and beyond.

In this paper, hot carrier degradation (HCD) in FinFET is studied for the first time from trap-based approach rather than conventional carrier-based approach, with full Vgs/Vds bias characterization and self-heating correction. New HCD time dependence is observed, which cannot be predicted by traditional models. A trap-based HCD compact model is proposed and verified in both n- and p-type FinFETs, which is unified across different Vgs/Vds regions with different carrier transport mechanisms. Impacts of HCD on analog circuits is also demonstrated, showing bias runaway effect. The results provide new insights of HCD in FinFET, which are helpful to circuit design for reliability.

Due to the shrinkage of CMOS technology, wear-outmechanisms such as Bias Temperature Instability (BTI) haveraised growing concerns for circuit reliability. BTI can causea threshold voltage shift in CMOS devices and consequentlyincrease circuit delay. This paper presents an ageing-aware gate-leveloptimization approach that can be used in a modernsynthesis process. It aims to optimize a circuit to give improvedlifetime reliability under given area and timing constraints. A newsensitivity metric is proposed as a function of area increase, delayreduction, degradation reduction and design constraints. Thissensitivity metric can be adjusted to select the most favourablegates in terms of circuit timing, lifetime or both. By iterativelyup-sizing the gates with the highest sensitivity, our proposedoptimization flow can meet any realizable area and timingconstraints, to give up to 3.3x lifetime improvement.

We postulate that BEOL dielectric breakdown can be described by the nucleation and subsequent growth of percolation defects. We develop a semi-empirical model to describe the statistics of post-breakdown current growth and eventual hard breakdown. The model predicts experimentally accessible interconnect lengths will exhibit a Poisson length dependence of the time to hard breakdown, and a percentile-dependent length dependence of the growth time. At the low percentiles of failure time distributions relevant to circuit reliability, the growth time is independent of the interconnect length, and as a result the reliability of circuits is dominated entirely by growth times. These findings provide the basis of new methodology for prediction of dielectric reliability that exhibits substantial increases compared to current industry standard methods.

This paper introduces an In-Circuit Reliability Test System (ICRTS) for SiC MOSFETs and diodes that can test a large number of high-voltage devices by emulating real life voltage and current stress to get statistical endurance test results. One challenge of testing a large number of devices under real life stress is the unrealistic amount of power consumption. To overcome this challenge, the ICRTS system uses the proposed pump-back converter topology. With this approach, the ICRTS system can stress the devices to their rated voltage and current conditions during each switching event and continuously switch the devices with appropriate switching frequency for an extended time while dramatically reducing the total power consumption to just the system loss. This system's concept was based on a single test unit board to verify its capability of energy cycling and device stressing while minimizing the power consumption. Another unique feature is the system running in open loop mode that enables real time feedback of any shift in the active device parameters. Simulation and experimental test results are provided to verify the operation of the proposed pump-back converter and its capability of operating in open loop mode and accommodate normal device and system variations when this is scaled to large number of parallel systems. To enable long term and safe operation of the test system, various voltage, current and temperature sensors and integrated in the test board that monitor the health in real time and shuts it off when any of the parameters cross a pre-determined threshold. A system level design is presented that can enable these individual converters to be operated in parallel. These features allow for independent test unit board shutdown, replacement, and failure analysis.

Negative bias temperature instability (NBTI) is an aging effect that can cause the threshold voltage to be shifted hence reduce the drain current. This will subsequently leads to main aging effect in sub-micron CMOS circuits. The NBTI defect mechanisms consist of interface trap generation and hole trapping effect. The main objective of this work was to study the impact of NBTI effect on the circuit performance based on different defect mechanisms. The percentage of how the performance affected in terms of delay by different defect mechanisms will be evaluated based on mirror full adder circuit. To study the reliability issues on circuit, model cards based on 45nm, 65nm and 90nm Predictive Technology Model (PTM) have been used along with the MOSRA model. The impact of NBTI on this circuit were evaluated based on the performance of the circuit which is the propagation delay. To understand the effect of different defect mechanism, analysis at the device level was conducted where the threshold voltage shift o...

Circuit reliability issues such as bias temperature instability, hot carrier injection, time-dependent dielectric breakdown, electromigration, and random telegraph noise have become a growing concern with technology scaling. Precise measurements of circuit degradation induced by these reliability mechanisms are a key aspect of robust design. This article reviews several unique test-chip designs that demonstrate the benefits of utilizing on-chip logic and a simple test interface to automate circuit aging experiments. This new class of compact on-chip sensors can reveal important aspects of circuit aging that would otherwise be impossible to measure, facilitate the collection of reliability data from systems deployed in the field, and eventually lead us down the path to real-time aging compensation in future processors.

This paper is introducing a multi-physics reliability simulation approach for solid state lighting (SSL) electronic drivers. This work explores the system-level degradation of SSL drivers by means of applying its components reliability information into a system level simulation. Reliability information of the components such as capacitor, and inductor, defines how a component electrical behavior changes with temperature, and also with time. The purpose of this simulation is to understand the thermal–electrical behavior of SSL electronic drivers through their lifetime. Once the behavior of the device during its lifetime is understood, the real cause of the failure can be distinguished and possibly solved.

Intensive scaling for VLSI circuits is a key factor for gaining outstanding performance. However, this scaling has huge negative impact on the circuit reliability, as it increases the undesired effect of aging degradation on ultradeep submicrometer technologies. Nowadays, Bias Temperature Instability (BTI) aging process has a major negative impact on VLSI circuits reliability. This paper presents a comprehensive framework that assists in designing the fortified VLSI circuits against BTI aging degradation. The framework contains: 1) the novel circuit level techniques that eliminate the effect of BTI (these techniques successfully decrease the power dissipation by 36% and enhance the reliability of VLSI circuits); 2) the evaluation of the reliability of all circuit level techniques used to eliminate BTI aging degradation for 16 nm CMOS technology; and 3) the comparison between the efficiency of all circuit level techniques in terms of power consumption and area.

Reliability Evaluation Tool of Universitat Autonoma de Barcelona (RELAB), a new simulation tool for circuit reliability evaluation, is presented. Based on the physical models of the phenomena (with experimentally determined parameters), RELAB allows considering MOSFETs threshold voltage shifts (due to process variability and/or degradation mechanisms) and gate leakage current increase after dielectric breakdown during the SPICE circuit simulation.

Technology scaling challenges for flash memory beyond 30 nm exacerbated as device fundamental limits are fast approaching. Nitride-based charge trap flash (CTF) is one of the most viable alternatives to eclipse floating gate flash in the market by leveraging the existing materials as compared with other exploratory nonvolatile memory devices. However, postcycled threshold voltage instability in the form of charge loss (CL) mechanisms remains as critical reliability challenges to further improve long-term data retention performance. This paper focuses on long-term data retention reliability issues with an emphasis on major CL mechanisms of nitride-based CTF memory. It encompasses comprehensive reviews and discussions on major CL mechanisms due to intrinsic and extrinsic causes. This paper would serve as a good reference for the future development of nitride-based CTF memory.

In this paper, we investigate the design of binary tree multipliers based on multi-input counters using hybrid MOS and single-electron transistors (SETs). Our focus is on the design of phase-modulated counters which can be implemented with only a few MOSFETs and multi-gate SETs. In order to address some practical issues associated with SET/MOS hybrid circuits, we present an enhanced version of the counters to deal with temperature effect, reliability improvement, and operating speed with multipliers. Simulation results with the proposed phase-modulated (7:3) counter show that it is able to work at room temperature with a delay of 1.5 ns, power dissipation of 4.1 μW at frequency of 100 MHz, and maximum tolerable background charges of up to 0.2e with the worst-case delay of 3 ns.