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In this work, the dynamic behavior of gallium nitride on silicon high electron mobility transistors (GaN/Si HEMT) with carbon doped buffer is modeled using a finite state machine embedded into the core Advanced SPICE Model for High Electron Mobility Transistor (ASM-HEMT). The model is based on the physics of trapping and detrapping of electrons in carbon at nitrogen-site acceptor trap (denoted here as $\text{C}_{N}$ ) and does not require an equivalent Resistance-Capacitance circuit. The model is validated against three off-state stress drain voltages of 50 V, 100 V, and 150 V using only $\text{C}_{N}$ as trap species.

Coupling of light from off-chip into highly complex silicon-based devices is currently focus of efforts and research. In this work, the experimental demonstration of a −0.50 dB (89%) coupling efficiency in the C-band with the help of an aperiodic grating coupler design in a 250 nm silicon-on-insulator (SOI) technology is shown. Further, this work reports about the latest results regarding focusing grating couplers with footprints of only 30 μ m × 30 μm and a measured coupling efficiency of up to −0.93 dB (81%) at 1549 nm. Efficient grating coupler arrays are realized by using an expanded backside metal mirror-strip for the application of fiber arrays. In addition, this work presents aperiodic silicon grating couplers with an enhanced bandwidth to overcome the limited usability of grating couplers in wavelength division multiplexing (WDM) systems.

A flexible and adaptive energy-efficient high-speed wireless hub is developed in polymer foil as a Hybrid System-in-Foil (HySiF) using Chip-Film Patch (CFP) technology. In this matter, the SiGe BiCMOS silicon chips (2.39 × 1.65 mm2) are thinned down to 45 μm and are embedded face-up inside a two-polymer CFP carrier. The active pads of the embedded silicon chips inside foil are extended to the surface of the foil to interconnect to the antenna on the foil. The integrated hybrid system has a signal transmission at 5–6 GHz frequency band. The overall thickness of the system is below 100 μm and its bendability is down to 4 mm radius of curvature. The designed and fabricated PA silicon chips operate at 50 mA with a 1.5 V supply voltage. Therefore, in addition to the high lateral thermal resistance of the thinned chip, self-heating loop inside polymer due to the low thermal conductivity of the embedding polymer raises the system temperature. Consequently, the thermal behavior and RF performance of the PA chip under different conditions are investigated. Moreover, the antenna with the required carrier frequency is simulated, fabricated, and measured on top of the polymer foil as a stand-alone system in the flexible CFP.

Current applications of silicon photonic devices are strongly limited by waveguide performance. Rough sidewalls scatter electromagnetic radiation and lead to significant losses. Prototyping of state-of-the-art silicon photonic devices on full wafer scale requires maskless manufacturing. Therefore, variable shaped electron-beam lithography in chemically amplified photoresists and anisotropic etching processes are used. As a result, size and roughness errors in the photoresist structures are directly transferred to the silicon-waveguides. In this study a high-resolution chemically amplified negative photoresist for electron-beam writing was run in and optimized for photonic device manufacturing successfully. The investigation of the photoresist contrast and critical dimensions enabled the production of smooth and critical dimension stable lines in photoresist, which exhibit vertical sidewalls as well as a resolution limit far below 100 nm.

Towards a biocompatible HySiF, in this work a customized Chip-Film Patch system is presented, in which an ultra-thin silicon chip is embedded in spin-coated polyimide. In addition, packaged with ceramic encapsulation layers, using atomic layer deposition (ALD) method thus achieving a prolonged long-term performance of the sensors. We have thoroughly investigated ALD coated polyimide foils with varying sequential metal oxide layers. More specifically, Al2O3-TiO2 thin-film layers are deposited on polyimide foils in the range from 20 nm –to 80 nm thickness. ALD thin-film is investigated with means of scanning electron microscopy and atomic force microscopy. Intrinsic stress of Al2O3-TiO2 thin-films on polyimide foils has been investigated and the water vapor transmission rate (WVTR) of the compound layers have been determined to assess hermeticity of the ALD layers. The long-term electrical leakage performance of the CFP substrates is evaluated, in physiological environment under cyclic mechanical load. The results provide a basis for processing flexible Hybrid Systems-in-foil for long-term utilization.

For some of the more demanding applications envisioned for organic transistors, lateral device dimensions of less than 1 μm may be necessary or should at least be explored in order to evaluate the scalability of organic transistors. Using stencil lithography based on high-resolution silicon stencil masks and employing two small-molecule organic semiconductors with good long-term air stability, we have fabricated organic p-channel and n-channel transistors with a channel length of 0.3 μm. Owing to the small channel length, the transistors have large channel-width-normalized transconductances (1.5 S/m for the p-channel and 0.2 S/m for the n-channel transistors). In addition, the transistors have steep subthreshold slopes (80 and 200 mV/decade) and large on/off current ratios (106).

Flexible Hybrid Systems-in-Foil (HySiF) allow the combination of large-area thin-film electronics with ultrathin, high performance silicon chips. Monitoring and determining the long-term reliability, and robustness, especially for biomedical application, is crucial. Biocompatible materials such as polyimides and noble metals are required, in order to prevent from side effects and to reduce the risk of rejection reactions. Based on the previously published data from our group, the scope of this work is to present the ongoing improvements of the process using a low stress polyamic acid based polyimide. The advantage over other organic materials is its low thermal expansion coefficient (CTE), which is close to that of silicon, resulting in reduced stress in the system, particularly, during the manufacturing process. However, unlike benzocylobutene based polymers, polyimide PI2611 shows poor planarizing behavior, leading to more inhomogeneous substrate layers and thus, affecting process steps, such as, photolithography, silicon chip embedding, metal etching, via opening and, direct laser writing, especially in terms of accuracy. To address those issues, we have investigated the homogeneity of multiple polymer layers using both spectroscopic reflectometry and surface profilometry. Based on a fabricated HySiF demonstrator, the crucial process steps are discussed and the reliability of the system is verified by thorough measurements under biological conditions.

Current electronic systems and circuits possess approximately 80 % of passive components. Thus, high performance integrated silicon-based passive components with high density are required to reduce the overall cost and bulkiness of the systems. This paper presents the development of high-density ultra-thin 3D capacitors in silicon, one of the important passive components exploited in approximately all the circuits for SiP, 3D-integration and flexible systems. The 3D structure is achieved by using deep reactive ion etching (DRIE) process. The substrate and the polysilicon act as the two electrode plates with silicon dioxide as the dielectric. Two designs with different pitches are investigated with successful back-grinding of the substrate to 50$\mu$ m thin and 22$\mu$ m ultra-thin singulated capacitors. Capacitive densities of 36.25 nF/mm 2 and 28.75 nF/mm 2 over a frequency bandwidth of 100 KHz are presented. The reduced thickness and flexible nature of these ultra-thin capacitors (

Hybrid System-in-Foil (HySiF) complements the merits of the very-large scale integration of silicon ICs with the largerarea electronics [1] , [2] . Both worlds/concepts are integrated on mechanically flexible substrates using, in our case, ChipFilm Patch technology (CFP) [3] . In this work, two CFP-compatible components, namely a temperature sensor and an ultra-thin microcontroller IC, are electrically and thermally characterized. The thin-film temperature sensor is fabricated using platinum metal resistor. The extracted temperature coefficient ranges from 2 m to 3 m (Ω/Ω)/°C depending on the substrate composition. In addition, the CMOS microcontroller IC is back-thinned to 30 µm using the dicing-before-grinding process sequence (DBG) [4] . The on-chip temperature sensor, 10-bit analog-to-digital converter (ADC) and RC oscillators are then characterized and compared to a reference design. The extracted ADC performance in terms of linearity remained within the datasheet specifications. A slight drop in the on-chip temperature sensor sensitivity from 3.6 to 3.5 mV/°C is observed. Finally a shift in the absolute frequency of the lowfrequency oscillator is detected, and the period jitter of the high-frequency oscillator degraded significantly.

In this work we present the first time to our knowledge a large area Si-energy filter for ion implantation based on a 150 mm SOI Wafer Flow Process. The filter consists of a microstructured 125 mm diameter Si-membrane with 6.5 μm thickness supported by the remaining silicon wafer ring. These filters are of large importance in the cost effective doping of SiC for high power device fabrication. We will present in this work the Si-energy filter fabrication process, characterization results of single process steps and SIMS depth profiles after ion implantation which are in good accordance to the calculated simulation model. Additionally the impact of defects on the substrate is discussed in this work and mandatory steps are described to reduce the amount of holes in the finished membrane.

Hybrid System-in-Foil exploits the complementary benefits of integrating embedded silicon chips with on-foil passive and active electronic components. In this work, the design, fabrication and characterization of three on-foil components, namely a humidity sensor, near field communication antenna and organic thin-film transistors, are investigated.

This paper reports on a design methodology and measurement results of a fully integrated low noise amplifier (LNA) on a thinned substrate for Internet of Things (IoT) applications. Several key RF performance parameters of the LNA with different substrate thickness are evaluated through full-wave electromagnetic (EM) simulations. The proposed LNA operating at 5.5 GHz is fabricated in a cost-effective 0.25 μm SiGe BiCMOS technology (IHP process SGB25V; ft = 75 GHz). The Si chip is thinned to ~38 μm in order to be embedded seamlessly into a flexible foil system. The small-signal gain of the LNA, measured on the chuck is 14.32 dB before thinning. The measured center frequency on the thin silicon (thickness of 38 μm) is shifted about 700 MHz towards higher frequencies compared to the thick silicon due to the image mirror currents within the conducting material at the backside of the chip. The measured noise figure (NF) with the thick and thin substrate on the conducting material is around 3.36 dB at 5.5 GHz and 3.74 dB at 6.3 GHz., respectively.

a flexible and adaptive energy-efficient high-speed wireless hub is developed as a Hybrid System-in-Foil (HySiF) using CMOS compatible Chip-Film Patch (CFP) technology. In this matter, the SiGe BiCMOS silicon chips (2.39 × 1.65 mm2) are thinned down to 45 µm and are embedded face-up inside a two-polymer CFP flexible foil carrier. The active pads of embedded silicon chips inside foil are extended to the surface of the foil and interconnected to the antenna fabricated on the foil using an adaptive layout technique. A thin chip power amplifier (PA) is embedded in flexible polymer foil and is interconnected to the antenna with a signal transmission at 5.5 GHz. The overall thickness of system is below 100 µm and, thus, has bendability down to 4 mm radius of curvature.

This paper presents S-parameter characterization and a corresponding physics-based small-signal equivalent circuit for organic thin-film transistors (OTFTs). Furthermore, the impact of misalignment between the source/drain contacts and the patterned gate on the dynamic TFT performance is explored and a simple method to estimate the misalignment from the measured S-parameters is proposed. An excellent fit between theoretical and experimental S-parameters is demonstrated. For this study, OTFTs based on the air-stable organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) having a channel length of 1 μm and a gate-to-contact overlap of 5 or 20 μm and being operated at a supply voltage of 3 V are utilized. The intentional asymmetry between gate-to-source and gate-to-drain overlaps is precisely controlled by the use of high-resolution silicon stencil masks.

Made primarily from nonsilicon organic and inorganic semiconductors, including polymers and metal oxide semiconductors, flexible chips are an exciting alternative to rigid silicon circuits in simple products like photovoltaic cells and television screens, because they can be made for a fraction of the cost. But today's flexible electronics just don't perform as well as silicon chips made the old-fashioned way.

The micro-hybrid system in foil (HySiF) involves ultra-thin chips embedded and interconnected in polymer foil for diverse flexible electronic applications. In this paper, the concepts and results of wafer level embedding and interconnection of ultra-thin dies in polymers are presented. The significant achievement of the presented HySiF is the accurate interconnection between a pair of functional chips at wafer level based on an adaptive interconnect layout, thus allowing for a small wire pitch on and off the chip. As a result, contact pads can be abandoned from the chip, which leads to reduced silicon area and, thus, lower cost. In addition, misalignment of embedded chips can be compensated by the adaptive layout, thus allowing for far higher I/O count. In this paper, this novel embedding technique is demonstrated with a metal pitch less than 108 µm and for a pair of functional chips spaced in the range of 200–1000 µm.

In this work we demonstrate, for the first time, the advantages of GaN HEMTs on bulk GaN substrates over similarly processed devices on Sapphire and Silicon substrates, intended for power applications, in terms of on-state and off-state operation as well as reliability, where self-heating, off-state leakage, and trapping effects are minimal. MIS-HEMTs with breakdown voltage of ∼670 V and off-state leakage current below 1 µA/mm are obtained in spite of the very basic and simple device design and technology used.

A new technology for thin-film MEMS encapsulation based on a monocrystalline silicon membrane and interfacial bonding is presented. The thickness of the membrane, used here, is 36 μm. It is produced on a dedicated wafer using a further development of the “Advanced Porous Silicon Membrane (APSM)” Process. The membrane wafer is attached on waferlevel to a MEMS wafer by glass-frit bonding. Before and during bonding the membrane is mechanically connected to its substrate by vertical anchors. Finally, the substrate is detached by cracking the anchors. Detaching the substrate is optimized by a variation of the lateral and the vertical anchor geometries. The new encapsulation technology enables a very low sensor height by a hermetically sealed monocrystalline MEMS-Cap while using well known technologies from mass production. Hence, a cost-efficient all-purpose thin-film encapsulation is presented. We demonstrate the new encapsulation technology by a capped absolute pressure sensor.

Ultra-thin chip technology has potential to provide solutions for overcoming bottlenecks in silicon technology and for leading to new applications. This, however, requires new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. Therefore, ultra-thin chips and the related applications represent a new paradigm in silicon technology. The paper highlights the prominent applications of ultra-thin chips, alerts to the related technological issues and compares the candidate enabling technologies.

System-in-Foil (SiF) is an emerging field of large-area polymer electronics that employs new materials such as conductive polymers and electrophoretic micro-capsules (E-Ink) along with ultra-thin and thus flexible chips. In flexible displays, the integration of gate and source drivers onto the flexible part increases the yield and enhances the reliability of the system. In this work we propose a high-voltage ChipfilmTM lateral diffused MOS transistor (LDMOS) structure on ultra-thin single-crystalline silicon chips. The fabrication process is compatible with CMOS standard processing. This LDMOS structure proves to be well suited for providing adequately large switching voltages in spite of the thin (

This paper addresses the properties of a surface-passivated (enhanced) high-resistivity silicon (HRS) substrate for use in monolithic microwave technology. The detrimental effects of conductive surface channels and their variations across the wafer related to the local oxide and silicon/silicon-dioxide interface quality are eliminated through the formation of a thin amorphous layer at the wafer surface. Without passivation, it is found that the surface channels greatly degrade the quality of passive components in HRS by masking the excellent properties of the bulk HRS substrate and by causing a spread in parameters and peak values across the wafer. Moreover, it is seen that the surface passivation leads to excellent agreement of the characteristics of fabricated components and circuits with those predicted by electromagnetic (EM) simulation based on the bulk HRS properties. This is experimentally verified for lumped (inductors and transformers) and distributed (coplanar waveguide, Marchand balun) passive microwave components, as well as for a traveling-wave amplifier, through which also the integration of transistors on HRS and the overall parameter control at circuit level are demonstrated. The results in this paper indicate the economically important possibility to transfer microwave circuit designs based on EM simulations directly to the HRS fabrication process, thus avoiding costly redesigns.

Add-on process modules as enhancements for standard high-frequency silicon integration processes are discussed. Such modules can cost-effectively be added without any interference with the core process before (pre-process modules), during (mid-process modules), or after (post-process modules) the circuit integration. In addition, layout options providing a most cost-effective means of enhancement are discussed. High-resistivity silicon substrates, ferromagnetic thin-film integration, bulk micromachining, saddle-add-on metallization, spacer-substrate integration, and metal layer shunting are presented as examples in those categories.

This review of design principles for implementation of a spiral inductor in a silicon integrated circuit fabrication process summarizes prior art in this field. In addition, a fast and physics-based inductor model is exploited to put the results contributed by many different groups in various technologies and achieved over the past eight years into perspective. Inductors are compared not only by their maximum quality factors (Q/sub max/), but also by taking the frequency at Q/sub max/, the inductance value (L), the self-resonance frequency (f/sub SR/), and the coil area into account. It is further explained that the spiral coil structure on a lossy silicon substrate can operate in three different modes, depending at first order on the silicon doping concentration. Ranging from high to low substrate resistivity, inductor-mode, resonator-mode, and eddy-current regimes are defined by characteristic changes of Q/sub max/, L, and f/sub SR/. The advantages and disadvantages of patterned or blanket resistive ground shields between the inductor coil and substrate and the effect of a substrate contact on the inductor are also addressed in this paper. Exploring optimum inductor designs under various constraints leverages the speed of the model. Finally, in view of the continuously increasing operating frequencies in advancing to new generations of RF systems, the range of feasible inductance values for given quality factors are predicted on the basis of optimum technological features.

Manufacturing ultra-thin chip is an emerging field in semiconductor technology that is driven by 3-D integrated circuits and flexible electronics. Unlike bulk silicon (Si) chips with thickness greater than 400 μm, the thermal management of ultra-thin Si chips with thickness smaller than 20 μm is challenging due to the increased lateral thermal resistance implying stringent cooling requirements. Therefore, a reasonable prediction of temperature gradients in such chips is necessary. In this work, a thermal chip is implemented in an ultra-thin 0.5 μm CMOS technology to be employed in surface steady-state and transient temperature measurement. Test chips are either packaged in a Pin Grid Array (PGA) ceramic package or attached to a flexible polyimide substrate. The experimental results show an on-chip temperature gradient of ∼15 °C for a dissipated power of 0.4 W in the case of the PGA package and ∼30 °C for the polyimide substrate. The time constants are ∼50 s and ∼1 s for the PGA and the polyimide packages respectively. The measurements are complemented by FEM simulations using ANSYS 14.5 workbench and spice simulations using an equivalent lumped-component thermal circuit model. The lumped-element thermal circuit model is then used for the surface temperature prediction, which is compared to measurement results.

The organic semiconductor DNTT (dinaphtho-[2,3-b:2',3'-f]thieno[3,2-b]thiophene) and its didecyl- and diphenyl derivatives C 10 -DNTT and DPh-DNTT [1-3] have recently shown exceptionally large field-effect mobilities together with excellent air stability [4]. Here we present a detailed analysis of the mobility, contact resistance, air stability and signal delay (measured in unipolar as well as complementary ring oscillators) of low-voltage (~3 V) thin-film transistors (TFTs) based on these semiconductors with channel lengths down to 0.5 μm on flexible plastic substrates. The TFTs were fabricated with an inverted staggered device structure and with Al gate electrodes, a gate dielectric composed of a plasma-grown AlO x layer (3.6 nm thick) and a tetradecylphosphonic acid self-assembled monolayer (SAM), a vacuum-deposited organic semiconductor layer (25 nm), and Au source and drain contacts [4]. The fabrication of organic TFTs with channel lengths as short as 0.5 μm was accomplished using high-resolution silicon stencil masks [6,7]. All measurements were performed in ambient air.

This paper presents a novel two-level silicon bulk micromachining for integration of RF devices. The RF devices are fabricated at the frontside of Si(100) wafers using conventional IC technology. A post-processing module is applied from the wafer backside with precise alignment to the frontside. This module can provide a blanket ground plane at an optimum position beneath the wafer surface, a frontside contact from the wafer surface to that ground plane, and trenches to suppress crosstalk through the conductive silicon by adding two mask levels. An extension to four masks allows for an integration of large passive components beneath circuitry for a much reduced chip area, lowering chip size and cost. The feasibility of the novel post-process module is demonstrated through the fabrication of microstrip transmission lines, conductor-backed spiral inductors, trench-barriers against crosstalk through the conductive silicon substrate, and high-quality subsurface spiral inductors.

The current research and development activities in silicon radio-frequency (RF) technologies are first reviewed, accompanied by an illustration of the most pronounced shortcomings of conventional silicon technology in the integrability of RF functions at high GHz frequencies. In the discussion on active RF devices mainly CMOS is investigated due to great interest in this mass-production technology. Issues related to the integration of spiral inductors on silicon are addressed, stressing in particular the difficulty of RF substrate potential definition. Silicon micromachining techniques are highlighted as potential solutions to the integration of RF passives and to reduce substrate losses and cross-talk on silicon. It is explained that micromachining techniques are the best introduced to the silicon mainstream by using post-processing and minimum process complexity.

The status of the integration, the modeling, and the layout of spiral inductors on silicon substrates for rf circuits are reviewed. A summary of the current research activity in this field is presented. The possible inductor implementations are categorized either as conservative, following the silicon main stream, or as innovative approaches. It is concluded that the spiral inductor on silicon is a feasible device and finds extensive use in the design of future silicon-based rf circuits. © 1998 John Wiley & Sons, Inc. Int J RF and Microwave CAE 8: 422–432, 1998.

Spiral inductors and different types of transmission lines are fabricated by using copper (Cu)-damascene interconnects and high-resistivity silicon (HRS) or sapphire substrates. The fabrication process is compatible with the concepts of silicon device fabrication. Spiral inductors with 1.4-nH inductance have quality factors (Q) of 30 at 5.2 GHz and 40 at 5.8 GHz for the HRS and the sapphire substrates, respectively. 80-nH inductors have Q's as high as 13. The transmission-line losses are near 4 dB/cm at 10 GHz for microstrips, inverted microstrips, and coplanar lines, which are sufficiently small for maximum line lengths within typical silicon-chip areas. This paper shows that inductors with high Q's for lumped-element designs in the 1-10-GHz range and transmission lines with low losses for distributed-element designs beyond 10 GHz can be made available with the proposed adjustments to commercial silicon technology.

A fabrication process for a thermo-diode microbolometer array is presented. The process is based on a sintered porous silicon (sPS) technique adopted from Chipfilm™ technology to enable vertical thermal insulation of the pixels. In addition, the process offers the possibility to have more than one diode per pixel connected in series. It is demonstrated that this boosts the temperature sensitivity of the device.

Here, we present a flexible sensor based on a stack of two ultra-thin IC-chips, exploiting the excellent chip thickness control in Chipfilm™ technology. The sensor consists of an almost stress-compensated bottom chip and a stress-sensitive top chip that are in good mechanical and thermal contact. Moreover, for the first time, we demonstrate that the chip thickness can be reduced to 10 μm, with the bulk Si body measuring only 7 μm, thus allowing for flexible chipstacks measuring only 20 μm in height. Furthermore, we demonstrate a self-aligned Through-Silicon Via (TSV) process in Chipfilm™ enabling 3D integration of such ultra-thin flexible chip pairs.

Spiral inductors and metal-to-metal capacitors for microwave applications, which are integrated on a silicon substrate by using standard 0.8 /spl mu/m BiCMOS technology, are described. Optimization of the inductors has been achieved by tailoring the vertical and lateral dimensions and by shunting several interconnect metal layers together. Lumped element models of inductors and capacitors provide detailed understanding of the important geometry and technological parameters on the device characteristics. The high quality factors of nearly 10 for the inductors are among the best results in silicon, particularly when using standard silicon technology.

Surface passivation of high-resistivity silicon (HRS) by amorphous silicon thin-film deposition is demonstrated as a novel technique for establishing HRS as a microwave substrate. Metal-oxide-silicon (MOS) capacitor measurements are used to characterize the silicon surface properties. An increase of the quality factor (Q) of a 10-nH spiral inductor by 40% to Q=15 and a 6.5-dB lower attenuation of a coplanar waveguide (CPW) at 17 GHz indicate the beneficial effect of the surface passivation for radio frequency (RF) and microwave applications. Regarding CPW attenuation, a nonpassivated 3000-/spl Omega//spl middot/cm substrate is equivalent to a 70-/spl Omega//spl middot/cm passivated substrate. Surface-passivated HRS, having minimum losses, a high permittivity, and a high thermal conductivity, qualifies as a close-to-ideal radio frequency and microwave substrate.

Here, we present a new concept for enabling the formation of TSVs in ultra-thin chips fabricated by using the ChipfilmTM technology. In this technology a buried cavity is created underneath a Si-membrane which is attached to the substrate by vertical silicon anchors. By applying thermal oxidation, the side walls of these anchors and the narrow cavity are passivated. Due to the high selectivity of the silicon via etching process the oxidized silicon anchors and chip backside can be exploited for creating self-aligned TSVs. Accordingly, a seamless oxide isolation at the chip backside and inside the TSVs is provided.

Ultra-thin silicon (Si) chips fabricated using the recently developed ChipfilmTM technology feature three distinct manufacturing issues, which are discussed in this paper. In Chipfilm™ technology a thin Si membrane is firmly attached to a conventional bulk Si wafer by vertical Si micro-anchors which, however, in the end are controllably fractured to make the thin chips detachable. The associated mechanical stability window is widened by adjusting the arrangement of the micro-anchors, so that chip detachment yields exceeding 99% are achieved. Another not yet reported issue relates to the process temperature and temperature uniformity within the membrane areas, which are thermally connected to the bulk substrate only by the anchors and at the chip edges during processing. Using rapid thermal oxidation and the local oxide thickness as a temperature monitor an on-chip oxide thickness variation of ±3 % is determined. Finally, the inherent deformation (warpage) of free-standing ultra-thin chips due to internal stresses is analyzed and their surface height variation is reduced to only ±4 μm using stress compensation techniques.

A series of microstrips with patterned Ni/sub 78/Fe/sub 22/ ferromagnetic cores have been investigated for RF applications. The devices have been integrated onto a silicon substrate by using a fully IC-compatible process. The Ni/sub 78/Fe/sub 22/ films were deposited by electroplating onto Si at room temperature and were structured into rectangular prisms with large aspect ratios, i.e., 10:1 and 40:1. Measurements have been performed using a network analyzer. Voltage attenuation of 19 dB/cm has been obtained at 3.9 GHz on a 2-mm-long strip line. The propagating wavelength is reduced by 60% compared to a control device without ferromagnetic core.

A complementary silicon bipolar technology offering a substantial improvement in power-delay performance over conventional n-p-n-only bipolar technology is demonstrated. High-speed n-p-n and p-n-p double-polysilicon, self-aligned transistors were fabricated in a 20-mask-count integrated process using an experimental test site designed specifically for complementary bipolar applications. N-p-n and p-n-p transistors with 0.50- mu m emitter widths have cutoff frequencies of 50 GHz and 13 GHz, respectively. Two novel complementary bipolar circuits-AC-coupled complementary push-pull ECL, and NTL with complementary emitter-follower-display a significant advantage in power dissipation as well as gate delay when compared to conventional n-p-n-only ECL circuits. Record power-delay products of 34 fJ (23.2 ps at 1.48 mW) and 12 fJ (19.0 ps at 0.65 mW) were achieved for these unloaded complementary circuits, respectively. These results demonstrate the feasibility and resultant performance leverage of high-speed complementary bipolar technologies. >

A new additive ultra-thin chip fabrication process is presented, utilizing an array of vertical anchors that mechanically connect silicon membrane chips to a standard silicon wafer. The process is demonstrated down to 8 µm silicon chip thickness, with a chip thickness control better than ±0.2 µm and a surface topography with average roughness < 7 nm. Such pre-processed wafers can be used for CMOS manufacturing like any conventional silicon substrate. A wide process window with yield figures exceeding 99% is achieved by proper management of the built-in and externally applied stress on the anchors. The excellent mechanical flexibility and stability of these ultra-thin chips make them particularly suitable for system-in-foil applications.

The International Technology Roadmap for Semiconductors (ITRS) projects decreasing chip thickness in support of three-dimensional integrated circuit (3D IC) solutions. The 3D IC technology potential is not yet fully leveraged due to insufficient scaling of the through-silicon via (TSV) pitch. Since technological limits restrict the TSV ratio at about 10:1, minimum chip thickness enables us to take full advantage of the 3D IC concept in support of continued miniaturisation (More Moore). Moreover, the excellent mechanical properties of silicon qualify ultra-thin chips for applications of silicon technology for added functionality (More than Moore).

Silicon-on-insulator (SOI) is a wafer substrate technology with potential to fabricate ultra-thin silicon layers and thus ultra-thin chips. The high cost of SOI wafers and technical difficulties to derive ultra-thin chips from SOI substrates so far have hindered the industrial exploitation of SOI technology for thin chip manufacturing. This chapter provides an overview of the present and past SOI technologies, a discussion about the technical difficulties in thin-chip fabrication based on SOI, and a former industrial approach as a related example.

Ultra-thin chip warpage is believed to have significant impact on electrical behavior of devices and circuits when the chips are glue attached to a flexible substrate. In this paper, we have investigated this packaging related issue by comparing ultra-thin silicon chips of similar thickness (∼ 20 µm) obtained from two fundamentally different fabrication technologies. We show that in spite of considerable structural and process-related differences, both type of chips exhibit the same degree of warpage. The electrical device characteristics on both chip type are almost identical. We also show that the degree and shape of warpage depends primarily on the chip layout and surface topology.

Apparently anomalous and transient piezoresistive effects are observed from CMOS transistors and diffused resistors fabricated on 20 µm thin, flexible chips for system-in-foil (SiF) applications. We show that this effect results from a transformation of uniaxial to biaxial stress according to the Poisson ratio of the visco-elastic epoxy glue used for chip attachment. This effect is further analyzed through current mirror circuits composed of orthogonally oriented transistors.

Ultra-thin chip technology has potential to provide solutions for overcoming bottlenecks in silicon technology and for leading to new applications. This, however, requires new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. Therefore, ultra-thin chips and the related applications represent a new paradigm in silicon technology. The paper highlights the prominent applications of ultra-thin chips, alerts to the related technological issues and compares the candidate enabling technologies.