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We propose an 8 by 8 dynamic true-single-phase-clock (TSPC) circuit based on low-temperature polycrystalline silicon (LTPS) technology to perform high speed dynamic memory cell. The proposed method allows the memory access rate to reach 25 MHz, in contrast to the traditional LTPS memory, with static circuit design, that operates at a low frequency of only about 6 MHZ. The 8 by 8 dynamic TSPC LTPS memory cell can be applied in high speed circuits. The experimental results show that the proposed 8 by 8 dynamic TSPC LTPS memory cell, operating at 25 MHz, can achieve high speed effectively. We believe it will be the most suitable technology to realize high speed memory for system on a panel (SOP) together with IC chip technology. Index Terms--Clocked storage elements (CSE), low-temperature poly-silicon (LTPS), system on panel (SOP), true-single-phase-clock (TSPC).

In this paper, low-temperature poly-silicon (LTPS) thin-film transistors (TFT) are used for LTPS memory on glass substrates. System on panel (SOP), combined with memory, controller, and driver circuits on a glass substrate, will be the most suitable applications for TFT panels in the near future. Recently, the low-temperature poly-silicon thin-film transistors prepared on glass substrates have been studied extensively. Compared to amorphous silicon TFT (a-Si TFT), the LTPS TFT has electron mobility that is several orders of magnitude higher. Therefore, it is possible to integrate the LTPS TFT with peripheral circuits on the same glass substrate for advanced flat panel display applications. We use LTPS technology to achieve a high-speed memory cell that adopts a true single phase clocking (TSPC) circuit. Finally, the experimental results show that the high-speed TSPC LTPS-TFT memory operates at 24 MHz and accomplishes the SOP design target. Index Terms--Amorphous silicon (a-Si), low-temperature poly-silicon (LTPS), system on panel (SOP), thin-film transistors (TFT).

A new, systematic way of coupling low-frequency finite-element (FE) models with circuit systems is proposed using a modified nodal analysis framework. Solid and filamentary conductors can be equally treated as magnetic vector potential-controlled voltage sources. Their matrix contributions to the coupled system are basically the same, leading to a natural way of adding conductors to arbitrary circuit topologies. Algebraic equations of the same type describe the coupling between FE and circuit models, for both massive and illamentary conductors. Any class of independent and dependent source can be considered as well as resistances, inductances, capacitances, transformers, auto-transformers and magnetically-coupled branches. The resulting matrix for the coupled problem is symmetric if the circuit configuration does not contain voltage- or current-controlled sources. The methodology is developed for the general nonlinear time-harmonic problem, but it can be extended to the transient case. An induction motor test case is employed to show the power of the new coupling approach. Comparison of the results against a well-known, validated commercial software (Flux2D) shows that the code developed in this work performs efficiently. Index Terms--Coupling circuit-field equations, modified nodal analysis, time-harmonic finite-element models.

Biomolecular computing is the computational method that uses the potential of DNA as a parallel computing device. DNA computing can be used to solve NP-complete problems. An appropriate application of DNA computation is large-scale evaluation of parallel computation models such as Boolean Circuits. In this study, we present a molecular-based algorithm for evaluation of Nand-based Boolean Circuits. The contribution of this paper is that the proposed algorithm has been implemented using only three molecular operations and the number of passes in each level is decreased to less than half of previously addressed in the literature. Thus, the proposed algorithm is much easier to implement in the laboratory. Key words: DNA computing, simulation, Boolean circuit, parallel computation, modeling, complexity, INTRODUCTION Molecular computing was emerged in 1994 by original paper of Adleman (8). He proposed an algorithm for solving Hamiltonian Path Problem using molecular operations. Adleman's experiment ushered in a [...]

In this paper, it is shown that every architecture proposed for modulo [2.sup.n] + 1 addition of operands that follow the diminished-1 representation can also be used in the design of modulo [2.sup.n] + 1 adders for operands that follow the weighted representation. This is achieved by the addition of a constant-time operator composed of a simplified carry-save adder stage. The experimental results indicate that many architectures already proposed for the diminished-1 case, lead to very efficient adders for weighted operands, under this unifying approach. Index Terms--Diminished-1 representation, modulo [2.sup.n] + 1 addition, residue arithmetic, residue number system.

This paper proposes a novel velocity observer which uses neural network and sliding mode for unknown mechanical systems. The neural observer in this paper has two stages: 1) a dead-zone neural observer assures that the observer error is bounded and 2) a super-twisting second-order sliding-mode is used to guarantee finite time convergence of the observer. With sliding mode compensation, the two-stage neural observer ensures finite time convergence, and reduces the chattering during its discrete realization. Index Terms--Finite time convergence, neural observer, second-order sliding mode.

Average-value modeling of dc-dc converters has been an area of active research for many years. Developing accurate average-value models of higher order converters is further complicated by the presence of parasitics and waveform nonlinearity. This paper extends the numerical state-space averaging to the fourth-order capacitor-based switching stages. The proposed model takes into account conduction losses associated with switching-stage components and is scamlessly functional in all operational modes. The proposed model is validated with a hardware prototype and detailed simulation and is shown to accurately predict large-signal time-domain transients as well as small-signal frequency-domain characteristics. Index Terms--Average-value modeling, Cuk converter, dynamic characterization, PWM dc-dc converters.

A method to solve the stationary state probability is presented for the first-order bang-bang phase-locked loop (BBPLL) with nonzero loop delay. This is based on a delayed Markov chain model and a state flow diagram for tracing the state history due to the loop delay. As a result, an eigenequation is obtained, and its closed form solutions are derived for some cases. After obtaining the state probability, statistical characteristics such as mean gain of the binary phase detector and timing error variance are calculated and demonstrated. Index Terms--Bang-bang phase-locked loop (BBPLL), delayed Markov chain, nonzero loop delay.

This paper studies the bounds of the response of a class of nonlinear systems with sinusoidal inputs. The unknown nonlinear system is assumed to have a unique steady-state response for a given input under different initial conditions. The sufficient condition of this assumption is given, and the bounds of the transient response and the steady-state response are derived in the sense of 2-norm and [L.sup.2] norm, respectively. A simulation example is presented to demonstrate the results. Index Terms--Sinusoidal input, steady-state response, transient response, bound.

A neutral-type delayed projection neural network is proposed to deal with nonlinear variational inequalities. Compared with the existing delayed neural networks for linear variational inequalities, the proposed approach apparently has the larger application domain. By the theory of functional differential equation, a delay-dependent sufficient stability condition is derived. This stability condition is easily checked, and can guarantee that the proposed neural network is convergent to the solution of nonlinear variational inequality problem exponentially, which improves the existing stability criteria for the neutral-type delayed neural network. Moreover, many related problems, such as the projection equation and optimization problems, can also be dealt with by the proposed method. Finally, simulation examples are given to illustrate the satisfactory performance of the proposed method. Index Terms--Neutral-type delay, projection neural network, variational inequality (VI).

This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of [2.sup.7] - 1, [2.sup.10] - 1, [2.sup.15] - 1, [2.sup.23] - 1, and [2.sup.31] - 1 b according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 [ps.sub.rms], and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18-[micro]m CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators. Index Terms--Clock multiplier unit (CMU), parallel feedback shift register (PFSR), psuedorandom word generator (PRWG), SerDes.

Laterally double-diffused metal-oxide-semiconductor (LDMOS) transistors subjected to hot-electron stress effects are evaluated. Findings reveal an increase in the gate charge of the LDMOS and a decline in the power efficiency of the full-bridge dc-dc converter after hot-electron stress.

In this paper, we show how a cellular nonlinear network with 1-bit weight programmability can be used for processing black and white image data. When using such a binary-programmable network, some templates need to be processed algorithmically, in other words, divided into subtasks that are processed consecutively. We classify templates into groups based on their properties and give guidelines as to how the division into subtasks (when applicable) is performed. A large collection of templates suitable for the proposed model is shown. We also describe one possible cell structure that realizes the binary-programmable model. The cell is modeled with Matlab and selected template simulations are shown. Index Terms--Analog processing circuits, cellular neural networks (CNNs), image processing, parallel architectures, threshold logic.

The stabilization problem for a simple (unstable) planar system in the presence of input and output quantization and saturation is addressed. It is shown that global stability to a terminal set, the size of which can be arbitrarily reduced, is achieved by means of a hybrid output feedback control law, which reads out the plant only three values and delivers a control action composed of three values. Directions to extend the proposed results to a class of n-dimensional systems are also provided. Simulation results complete the work. Index Terms--Observability, planar systems, saturation, stability.

A new discrete-domain method is proposed for the beamforming of temporally broad-band bandpass plane waves (PWs) using a real-coefficient 2-D spatio-temporal (ST) finite-impulse response (FIR) filter having a novel rectangularly symmetric double-trapezoidal-shaped passband. The arriving temporally broad-band-bandpass ST PWs are received by a 1-D uniformly distributed sensor array. The sensor signals are pre-filtered, down-shifted to the intermediate frequency (IF) band, low-pass filtered and synchronously sampled by the real IF tri-stage temporal sampler array, resulting in a real-valued 2-D sampled sequence. The beamforming operation is then carried out on this 2-D sampled sequence using the real-coefficient 2-D FIR double-trapezoidal filter. Arithmetic complexity in the hardware implementation of the 2-D FIR double-trapezoidal filter is significantly reduced by using an array of real-coefficient polyphase 1-D FIR filters. Experimental results have confirmed that this method is capable of enhancing the desired temporally broad-band-bandpass ST PWs according to their directions of arrival under severe co-channel interference. Index Terms--2-D filter, beamforming, broad-band bandpass signals, double-trapezoidal-shaped passband, finite-impulse response (FIR), polyphase, spatio-temporal (ST) plane waves (PWs).

An arithmetic unit (AU) that performs all basic arithmetic operations in the finite field GF([2.sup.m]) is presented, where m is an arbitrary integer. The presented finite field AU consists of an arithmetic processor, an arithmetic logic unit, and a control unit. The proposed AU has low circuit complexity and is programmable, so that any error-correcting decoder that operates in GF ([2.sup.m]) can be easily implemented with this AU. Index Terms--Arithmetic unit (AU), error-correcting codes, finite field.

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q, mismatch effects using a complex sigma-delta ([SIGMA][DELTA]) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass [SIGMA][DELTA] cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex [SIGMA][DELTA]/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q, mismatch. Index Terms--Bandpass analog-to-digital converter (ADC), data converter, complex ADC, digital calibration, digital intermediate frequency (IF) receiver, in-phase and quadrature (I/Q) mismatch, sigma-delta ([SIGMA][DELTA]).

The minimum attainable noise figure for scaled-CMOS low-noise amplifiers (LNAs) is limited by impedance mismatches such as the well-known noise/power tradeoff. In this paper, we show that a power-constrained optimization of the device noise resistance parameter, [R.sub.n], significantly reduces the impact of mismatches and variations and leads to an almost simultaneous noise and power match. This process, called desensitization, makes the design largely immune to measurement and modeling errors and manufacturing variations, and significantly reduces frequency-dependent noise mismatches in wide-band LNAs. Measured data from devices and desensitized LNAs designed on 180-nm and 90-nm CMOS processes shows that: 1) a device size selected for optimum [R.sub.n] is less sensitive to source impedance mismatches and provides a wide-band noise match; and 2) LNAs approach a simultaneous input and noise match, and exhibit significant improvements ([greater than or equal to] 2x) in their wide-band noise performance. Index Terms--CMOS, desensitization, low-noise amplifier (LNA), noise, noise figure, noise parameters, scaling.

This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40-kS/s A/D converter (ADC) with an active die area of 0.041 [mm.sup.2] is implemented in a 0.13-[micro]m CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4-[micro]W power dissipation, the ADC achieves 80.2-dB spurious-free dynamic range and 63.3-dB signal-to-noise and distortion ratio. Index Terms--Accelerometer, algorithmic analog-digital (A/D) converter, low power, ratio independent, sensor.

One of the main contributions of this paper is to highlight the feasibility of analog realization of a chaotic observer-based communication system. The system is composed of a chaotic Colpitts oscillator considered as transmitter and a sliding-mode observer used as receiver. The method used in this realization is based on the synchronization of two chaotic systems (transmitter-receiver). Moreover, another originality of this work is the application of a sliding-mode observer to a Colpitts oscillator, which has a totally different structure with respect to it. Nevertheless, the proposed structure of the observer is designed particularly for this type of oscillator. Only one of the states of the transmitter (chosen according to theoretical criteria) is sent to the receiver which is designed to reconstruct all of the states of the transmitter knowing only the transmitted state. In order to show an application of this work, a message signal is injected into the transmitter using the so-called inclusion method. The message is then recovered by the receiver once all of the transmitter states are reconstructed. Thus, the so-called left inversion problem is resolved experimentally. The whole system (transmitter-observer) is realized using simple and standard analog components, and practical results close to simulations are obtained. Index Terms--Chaotic synchronization, data transmission, sliding-mode observer.

Layered approximately regular (LAR) low-density parity-check (LDPC) codes are proposed, with which one single pair of encoder and decoder support various code lengths and code rates. The parity check matrices of LAR-LDPC codes have a 'layer-block-cell' structure with some additional constraints. An encoder architecture is then designed for LAR-LDPC codes, by making two improvements to the Richardson-Urbanke approach: the forward substitution operation is entirely removed and the dense-matrix-vector multiplication is handled using feedback shift-registers. A partially parallel decoder architecture is also designed for LAR-LDPC codes, where a layered modified min-sum decoding algorithm is used to trade off among complexity, speed, and performance. More importantly, the interconnection network, which is inevitable for partially parallel decoders, has much lower hardware complexity compared with that for general LDPC codes. Both the encoder and decoder architectures are highly flexible in code length and code rate. Index Terms--Code construction, encoder, decoder, hardware architecture, low-density parity check (LDPC).