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The structure of this review frames the discussion over three time periods; (1) the 4 decades since the mid-1970’s with the introduction and growth of Si-based ICs, first as bipolar and then MOS devices, focusing on the MOS scaling models developed by Robert Dennard at IBM, (2) a brief look at scaling issues for bulk planar CMOS in the late 2000’s, as limits of gate length shrinks became major problems and (3) an examination of channel length and width scaling for fully-depleted CMOS in the last decade. This note concludes with a mention of the challenges to further scaling presented by line-edge roughness and quantum confinement for the industry-standard form of bulk finFETs.

Monolithic 3D technology (M3D) is a promising alternative to takle the loss of Moore's Law scaling beyond 22 nm node. By stacking different circuit layers thanks to nano-scale 3D Monolithic Inter Tier Via (MIV), it will be possible to offer a level of circuit integration never reached before, allowing advanced node scaling again as well as mixing heterogeneous technologies. M3D integrates sequentially different layers of transistors, with an ultra-fine pitch, in the 100 nm range, which is 200x smaller than state-of-the-art Through Silicon Vias (TSV) or 50x smaller than Copper to Copper Hybrid bonding (Cu-Cu HB). This high density 3D integration will pave the way towards new architectures, such as neuro- and bio-inspired applications, ultra-high density computing cube and smarter mixed signal devices within low power constraints. This paper presents an overview of M3D technology and potential applications, and in more detail its associated design challenges, respectively on physical implementation aspects and on thermal dissipation.

This paper reports on gate-all-around silicon nanowire field-effect transistors (FETs) built in a lateral configuration, which represent the ultimate scaling limit of triple-gate finFET devices and allow a less disruptive CMOS scaling path in terms of processing and circuit layout design. We address several of their critical technological challenges, looking in particular at doping strategies. A comprehensive review of junctionless versus inversion-mode type of transistors is here presented, evaluating the impact on the devices' operation mode and on device properties such as: variability, reliability, noise, DC and analog/RF performance. We also discuss the potential for further manufacturable co-integration options.

This work investigates the impact of CMOS scaling on the DC effective drive current, $I_{eff}$ [1], $I_{eff}=1/2\times(I_{high}+I_{low})=1/2\times [d_{s}(V_{gs}=0.5V_{dd},V_{ds}=V_{dd})+(V_{gs}=V_{dd},V_{ds}=V_{dd}/2)$ ] of aggressively scaled MOSFETs down to 7nm node technology. FinFET and Nanosheet (NSFET) architectures [2], [3] behave similarly, and $l_{eff)}$ continues to predict the intrinsic delay for aggressively scaled MOSFETs for both device architectures, even for supply-voltages $(V_{dd})$ as low as ~0.2V, where these devices operate in the subthreshold regime. The ratio of $l_{eff}/I_{on}, I_{on}=I_{ds}(V_{ds}=V_{gs}=V_{dd})$ , as a function of $V_{dd}$ , and threshold voltage $(V_{th})$ ) show that this ratio can be significantly modulated about a typical value of ~0.5, in a manner that can be easily related to classical MOSFET behavior.

The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework. Through a double level access it offers a structural scaling of both standard cells (SDC) and SRAM by 50%. The proposed process flow requires accurate control of the elevation dimension for manufacturability. Based on TCAD analysis, the CFET can eventually outperform the finFET device and meet the N3 targets in power and performance. To achieve that, the dominating parasitic resistance of the deep vias needs to be reduced by the introduction of advanced MOL contacts featuring thin barriers.

We look at several scaling boosters necessary to accomplish CMOS area scaling towards the 2nm node. We consider aspects of standard cell area scaling, transistor architecture, SRAM, and BEOL. We also demonstrate integrated flows and hardware feasibility for such scaling boosters.

Imec is a research centre located in Belgium. Specialising in nanoelectronics, it is mostly known for advanced lithography and CMOS scaling research. However, building on that equipment and material knowledge, Imec works in a number of different application-oriented domains. Hyperspectral imaging, to which this article is devoted, is one of them.

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules.

High-performance radio frequency integrated circuit (RF ICs) is the core of wireless systems. While CMOS scaling and integration have been beneficial to modern RF ICs, future RF ICs call for More-Than-Moore technologies. This paper reviews recent advances in developing enabling 3D heterogeneous integration technologies for next-generation RF ICs, including vertical magnetic-cored inductors, through-back-end-of-line (BEOL) metal wall crosstalk isolation and above-IC graphene switch electrostatic discharging (ESD) protection.

Dissertation, Rheinisch-Westfälische Technische Hochschule Aachen, 2018; Aachen 1 Online-Ressource (x, 114 Seiten) : Illustrationen, Diagramme (2018). = Dissertation, Rheinisch-Westfälische Technische Hochschule Aachen, 2018, The progress of state-of-art electronics requires CMOS technology to be more powerful and power efficient. CMOS scaling is the way to achieve the goals in the past decades. However, the scaling tends to end. 3D stacking lateral and vertical nanowire MOSFETs have been proposed for further increasing the transistor density. Junctionless nanowire MOSFETs (JNT) are suited for the 3D integration because its source, drain and channel are uniformly doped which eliminates the complex process for junction formation. However, it is difficult to reduce power through the 3D integration. To reduce the power supply voltage, negative capacitance (NC) MOSFETs were proposed to improve the subthreshold swing (SS). In a NC MOSFET, NC effect is utilized to internally amplify the gate voltage, while the NC effect comes from the ferroelectric gate oxide in the device. With the motivations we investigated NC MOSFETs and JNTs, and present the results in the thesis. The fabrication of NC MOSFETs requires CMOS compatible ferroelectrics. We explored different alloys of hafnium oxides with elementary substances. HfY0.03Ox was found to show better ferroelectricity than HfGd0.05Ox and Hf0.5Zr0.5Ox. Besides, Pulsed Laser Deposition (PLD) deposited HfGd0.05Ox was found to show a self-rectifying low current resistive switching. To explore NC MOSFETs, MFMIS (metal-ferroelectric-metal-insulator-semiconductor) MOSFETs with Hf0.5Zr0.5Ox and HfGd0.05Ox ferroelectrics, and MFIS (metal-ferroelectric-insulator-semiconductor) MOSFETs with HfY0.03Ox ferroelectric were fabricated and characterized. In MFMIS MOSFETs, effect of pulse charging of the floating gate was observed instead of the NC effect. The low current resistive switching of the HfGd0.05Ox layer causes a sudden injection of free charge into the floating gate, which improves SS. The ferroelectric polarization switching of the Hf0.5Zr0.5Ox layer quickly induced more charge in the floating gate, which also improves SS. The pulse charging effect was clarified by developing a modified formula of SS. In MFIS MOSFETs, sub-thermal SS was observed in the reverse sweep following a high gate voltage application. The sub-thermal SS extends for 2.5 decades with average SS of 30 mV/dec and minimum SS of 8 mV/dec. The influence of trap charging on the stability of sub-thermal SS was investigated. Based on our analysis the sub-thermal SS was attributed to the transient NC effect. JNTs with the gate length of 80~120 nm and nanowire width of 10 nm were fabricated and characterized. Geometries of gated source drain (GSD), where the gate overlaps with the source drain pads, and source drain extension (SDE), where the gate underlaps with the nanowires, were designed. GSD JNTs show improved on current, SS, DIBL (drain induced barrier lowering) and variability than SDE JNTs. However, GSD JNTs also show larger capacitance. To characterize the tradeoff between capacitance and on current, cutoff frequency (f_t) of the JNTs were characterized. The GSD JNT shows a f_t of 30 GHz compared to the 11 GHz of the SDE JNT. The results indicate that GSD JNT is a competitive alternative to the future MOSFET., Published by Aachen

▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power consumption.

With the growing need to pack more functionality into a smaller form factor while providing significant power-performance benefits, future electronics will need fairly disruptive solutions to overcome the mounting limits of Si CMOS scaling. At the core of the hardware innovations will be new process technologies that allow for not only more power-efficient CMOS transistors but also specialized devices to enable new on-chip functionality, for example, sensors, high-speed I/O, optoelectronics, power management, and RF.

In this section, firstly, a brief background is presented to explain the issues connected with CMOS scaling and breakdown voltage. Secondly, the research objectives, scope, plan and a brief methodology of this project are expressed.

As CMOS scaling approaches the fundamental limits, the search for beyond-CMOS switches has intensified. After more than a decade of research on the “next switches” to replace CMOS, it is generally recognized that CMOS will continue to be the platform technology while beyond-CMOS devices may augment CMOS by improving performance, efficiency, or functionality via their unique characteristics. Cooptimization of these devices with novel architecture designs will be essential for achieving optimal system performance and efficiency. This learning has guided beyond-CMOS research toward system-oriented directions built upon device-architecture cooptimization.

International audience; We present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results.

Consumer demand for low-power mobile ICs has propelled CMOS scaling to arrive at the fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The compact three-dimensional structure of the finFET offers superior short-channel control that achieves digital power reduction while increasing device performance for a given area. As system-on-chip technology remains driven by logic and SRAM scaling needs, designers of analog/mixed-signal subsystems must continue to adapt to new technology constraints. We attempt to summarize the challenges and technology considerations encountered when we port analog/mixed-signal designs to a finFET node. At 16/14 nm and beyond, designers also face many implications from scaling innovations leading to the finFET.

The time-based ADC (TB-ADC) is gaining attention as a key technology to solve challenges concerning CMOS scaling; however, it cannot achieve high speeds and a high resolution at the same time. We proposed a TB-ADC architecture combining a flash ADC and TDC to achieve both high speeds and a high resolution. The flash ADC and the ADC using a VTC and TDC are pipelined to enhance the conversion speed. The charge steering amplifier is used for the low-power residue transfer. Moreover, the Vernier TDC using the dynamic delayer enables low-power operation. An 8-bit ADC test chip fabricated using 65-nm CMOS technology demonstrated a high sampling frequency of 900 MHz and a low-power consumption of 3.5 mW. The FOM was 32 fJ/conv.-step.

Huge efforts are put into CMOS scaling to push the limits of Moore’s law. Semiconductor ICs manufacturing companies are currently ramping up 16-nm/14-nm FinFET processes, with 7 and 5 nm just around the corner.

Over decades, MOSFET gate length scaling has been the main source of progress in semiconductor electronics. Today, however, the motivation of the industry to continue gate length scaling is declining. On the other hand, researchers still spend considerable efforts on reducing the gate length and on developing ultimately scaled MOSFETs. To this end, both new device architectures and alternative channel materials are explored. In the present paper, the future of CMOS scaling in the light of emerging 2D channel materials is discussed.

As it was mentioned in the introduction, one possibility to continue with CMOS scaling is the substitution of the Si channel with high mobility semiconductors, such as III–V materials.

Artificial neural networks are intensively used to perform cognitive tasks such as image classification on traditional computers. With the end of CMOS scaling and increasing demand for efficient neural networks, alternative architectures implementing neural functions efficiently are being studied. This study leverages the demonstrated frequency tuning capabilities of compact nano-oscillators and their synchronization dynamics to implement a neuron using a pair of synchronized oscillators, and which features an unconventional response curve. We show that this compact neuron can naturally implement generic logic gates, including XOR. A simulated oscillator-based neural network is then shown to achieve results equivalent to standard approaches on two reference classification tasks. Finally, the performance of the system is evaluated in the presence of oscillator phase noise, an important issue of oscillating nanodevices. These results open the way for the design of alternative architectures adapted to efficient neural network execution., Comment: IEEE Nano 2017 Conference

Conventional scaling of planar CMOS devices has reached a practical electrostatic design limit at roughly 25nm gate lengths, corresponding to the 20nm node. The double-gate transistor has long been known to offer the potential to extend electrostatic scaling and in the last dozen years, workers around the world, in academia and industry, have applied a vertical fin-like embodiment of the double-gate FET, most popularly referred to as the 'FinFET,' to tackle the challenges of process, device, and product design, and accomplish the introduction of double-gate FETs into main-stream manufacturing. A view of these challenges and their solution leads to a projection that this FinFET structure will prove scalable to at least the atomic limit of CMOS scaling.

In this work, we will review the advantages and challenges of vertical devices which are seen as possible candidates to continue CMOS scaling. Different integration schemes will be discussed, also addressing the use of novel channel materials like III-V that could benefit from a vertical architecture to relax both gate length and wire diameter. Next to that, layout efficiency and the benefits of vertical MOSFETs for SRAM will be highlighted.

Conventional CMOS scaling and the Moore's law have been the cornerstone of progress in computing hardware technology. However, with dimensional scaling expected to end soon, there is a pressing need to find the next transistor solution that can continue to support the technology revolution. Will this hardware solution be an enhanced or an augmented version of MOSFET or a switch based on a radically new switching mechanism. Ultimately, do we require a complete deviation from the Boolean paradigm itself? In this invited paper, we will review some of the actively pursued state-of-the-art transistor and related concepts. While it remains unclear which of these options will eventually make it into commercial products, we will argue-based on lessons learnt from the past two decades of transistor development-that sustained and systematic research with careful benchmarking remains the key to success in the quest for the new switch.

This keynote talk discusses challenges and directions for research on silicon and silicon-like devices as the industry approaches the end of the CMOS scaling era.

Fully depleted SOI (FDSOI) has become a viable technology not only for continued CMOS scaling to 22 nm node and beyond but also for improving the performances of legacy technology when retrofitting to old technology nodes. In this paper, we provide an overview of FDSOI technology, including the benefits and challenges in FDSOI design, manufacturing, and ecosystem. We articulate that FDSOI is potential cornerstone for China to catch up and leapfrog in semiconductor technology% .

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress and reduced variability. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will be introduced to make it possible.

The superior transport properties of III-V materials makes them attractive choices to enable improved performance at low power. This paper examines the module targets and challenges for III-V materials to be successfully integrated for high performance/low power logic at or beyond the 11 nm technology node. A VLSI compatible, self-aligned, III-V on 200mm Si MOSFET process flow is presented using an industry standard toolset. Statistically significant data shows that III-V devices can be processed on a Si line with controlled contamination, good uniformity and yield. The Lg = 500 nm device has a drive current of 471 µA/µm (Vgs = Vds = 1V) and intrinsic transconductance of 1005 µS/um.

This special issue presents a variety of invited papers covering nanostructures and related materials proposed to extend CMOS scaling to its ultimate limit and enable a variety of new logic and memory devices.

Fully depleted SOI (FDSOI) is a viable option for continued CMOS scaling. In this paper, we overview key challenges for designing and manufacturing extremely thin SOI (ETSOI) devices and provide solutions to each challenge. We demonstrate successful fabrication of ETSOI devices with physical gate length down to 25nm and SOI channel thickness down to 3.5nm. Our highly scaled ETSOI devices exhibit excellent electrostatics and respectable performances. We further discuss unique opportunities enabled by ETSOI for reducing CMOS process complexity and therefore reducing process cost, which in turn at least partially offsets the higher cost of SOI substrates. The unique advantages of ETSOI in conjunction with the presented solutions to challenges render ETSOI a strong candidate for scaling planar CMOS to 22-nm node and beyond.

As the planar CMOS transistor devices scaling down, a lot of original process have to be optimized, developed or changed to meet the evolutional requirement, and the new process elements were continuously implemented into the manufacture. The STI-liner is one of the processes from the STI module, which comes after the trench etch and before the trench gap-fill, to provide an excellent interface and good adhesion between the silicon and the oxide. While the device scaling down, some device issues, such as, the incident of dislocations which impacted on the device leakage current, the dopant segregation which result in the threshold voltage variation and impact the inverse narrow width effect (INWE) and the gate oxide integrity (GOI), etc, are associated with the STI module and can be improved by the STI-liner process. The STI liner process is evolved from the furnace oxidation, the dry RTO, the nitrided oxide liner to the ISSG.

IC technology, which has traditionally been dominated by dimensional scaling, is facing several technical and economic hurdles as it moves forward. Low K insulation has not been able to meet performance projections, copper traces are becoming more and more resistive, clock rates have been constrained due to thermal issues and multicore processors are demanding major increases in bandwidth and decreases in latency. Economic constraints will also begin limiting the number of IC companies able to develop leading-edge IC designs. Moving past 45 nm digital CMOS scaling will no longer guarantee lower cost and higher performance. All of these issues have crated a “perfect storm scenario” for the widespread adoption of 3D IC technology.

Aggressive CMOS scaling and device performance enhancement is pursued thgrough the use of advanced dielectric and substrate materials. High-k dielectric materials are the key to both dramatically reduce the standby leakage current (and thus power consumption) and to enable the use of high mobility substrates. Critical for device performance and reliability are both the interface quality and bulk defect control. The most important question for high-k materials is always: "How many defects can we allow in these materials and how these are going to influence the performance observed and the reliability?" This paper addresses these issues by looking at both the current understanding of defects in advanced materials for performance and reliability.

The advent of high-k/metal gates into production for CMOS gate stacks has marked the onset of MOSFET scaling that has clearly become reliant on new materials and / or new device architecture. Additionally, new approaches to form ultra-shallow junctions with high active-dopant concentrations and low schottky barrier height silicides with novel materials to reduce contact resistance have been reported by many groups and will continue to facilitate MOSFET scaling with increasing performance. It is becoming clear that Si (as the channel) may not be able to provide for the high performance combined with low power technologies that would be needed in future. Over several years, there has been a lot of research on high mobility channels: group IV for pMOSFETs and III-V for NMOSFETs. However, there appears to be little consensus on a) the choice of high mobility channels for P and N channel MOSFETs, b) its potential compared to short channel strained-Si, and 3) potential technology node for insertion. In this work, trends, challenges and opportunities related to several of the aforementioned modules (gate stack, junctions, contacts, and high mobility Ge based channels) will be briefly presented and discussed.

High-k/metal gate stacks are a promising and viable approach for CMOS scaling. The high permittivity of the dielectric used can reduce the leakage current while preserving the low equivalent oxide (EOT) thickness needed for the future step of technologies. The recent advances are very encouraging, but reliability aspects, in particular TDDB characteristics, are much less developed. In this paper we investigate the issue of progressive dielectric breakdown, a debated aspect (1-3), which is critical for evaluation of the device lifetime.

In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the critical features: 32 nm gate pitch and 24 nm metal pitch. Layout architectures and patterning compromises for enabling the 5nm node will be discussed in details. A distinct standard-cell template for vertical FETs is proposed and elaborated for the first time. To assess electrical performances, a BSIM-CMG model has been developed and calibrated with TCAD simulations, which accounts for the quasi-ballistic transport in the nanowire channel. The results show that the inbound power rail layout construct for vertical devices could achieve the highest density while the interleaving diffusion template can maximize the port accessibility. By using a representative critical path circuit of a generic low power SoCs, it is shown that the VFET-based circuit is 40% more energy efficient than LFET designs at iso-performance. Regarding SRAMs, benefits given by vertical channel orientation in VFETs has reduced the SRAM area by 20%~30% compared to lateral SRAMs. A double exposures with EUV canner is needed to reach a minimum tip-to-tip (T2T) of 16 nm for middle-of-line (MOL) layers. To enable HD SRAMs with two metal layers, a fully self-aligned gate contact for LFETs and 2D routing of the top electrode for VFETs are required. The standby leakage of vertical SRAMs is 4~6X lower than LFET-based SRAMs at iso-performance and iso-area. The minimum operating voltage (Vmin) of vertical SRAMs is 170 mV lower than lateral SRAMs. A high-density SRAM bitcell of 0.014 um2 can be obtained for the iN5 technology node, which fully follows the SRAM scaling trend for the 45nm nodes and beyond.

The FinFET technology is continuously progressing toward 14nm node on SOI and bulk substrate with good compatibility with planar CMOS and driving CMOS scaling and Moore's law for low-power/SOC and future Internet-of-Things (IOT) applications. The challenges of new FinFET technology in manufacturing at 14nm and beyond is reviewed.

Next generation sequencing (NGS) is a disruptive technology that concurrently sequences millions of DNA fragments at low cost with high throughput and impacts nearly every field of biology and medicine. The most widely used biosensing techniques today, including those for NGS, are optical in nature and thus do not benefit from the annual scaling advancements made in the semiconductor industry. ISFETs have been demonstrated as a viable approach towards all-electronic DNA sequencing [1]; however, there are technological barriers to overcome in scaling, namely the diminished SNR as the size of the sensor is reduced to fit more sensors on the same chip. Towards this end, we demonstrate an alternative high-density electrochemical biosensing technique for DNA sequencing that leverages CMOS scaling to reduce costs and enable more compact NGS systems.

We review the impact of oxide-semiconductor interface chemistry and precursor choice on the quality of novel field-effect transistor gate dielectrics grown by atomic layer deposition (ALD). Focus is on hafnium- and aluminum-based high-permittivity ('high-k') gate dielectrics on silicon and on high carrier mobility (germanium, gallium arsenide) channels. We shed light on the ways processing parameters (choice of materials; surface preparation; high-k dielectric deposition process) determine stack structure (continuity of the high-k layer; interfacial oxide thickness; detrimental channel-dielectric interactions) and hence electrical quality. Trends are rationalized based on thermodynamic properties of the semiconductors, dielectrics, and metal-organic precursors involved. This may serve as a basic guideline for ALD precursor selection.

The development of CMOS technology is always driven by system needs. Traditionally, these needs have been met quite satisfactorily by simply reducing the physical size of the transistors as guided by the MOSFET scaling theory and increasing the chip-level integration density as anticipated from Moore's Law. Now that CMOS has reached some of its key scaling limits, continued progress has to come from innovations beyond the traditional development paths, again guided by anticipating and addressing system designers' concerns and needs. To make real progress, we need to understand where CMOS scaling has run into limits and where the new barriers are. In this talk, we examine the factors limiting the scaling of CMOS as well as the opportunities for extending current CMOS technology to continue satisfying the needs of system designers.

In CMOS scaling roadmap, gate-all-around (GAA) nanowire (NW) is a promising candidate in sub-10nm nodes. However, newly introduced process options in GAA NW technologies can result in significant impacts on intrinsic ESD performance. In this work, ESD protection devices in GAA NW architecture are studied and the corresponding 3D TCAD simulations bring an in-depth understanding.

The Nano Wire (NW) CMOS technology is widely considered as a promising evolutionary solution of current FinFET technology. The main advantage of the nanowire transistors for ultimate CMOS scaling is their optimal electrostatic confinement. In this paper, the major assets of NW field-effect-transistors in leading-edge technology nodes are explained in details. For this purpose, electron (hole) transport properties of Si (SiGe) NWs and the critical contribution of strain are discussed. A particular attention is given to the key technological integration challenges to be addressed, with emphasis on the practical implementation of 3D high-density stacked-NWs architectures.

This review focuses on material challenges associated with III-V co-integration with Si for future CMOS. There is a huge volume of literature on this topic as implementation of III-V monolithic integration with Si has been the holy grail for last four decades; targeting a wide range of applications including RF devices, LEDs, lasers, photo-detectors and the like. The key drivers have been the cost reduction, scalability with Si wafer diameter, and accessibility to highly scaled integrated circuits next to III-V devices. With the current focus on CMOS the pace of progress on monolithic integration has accelerated by leaps and bounds partly because of its vast impact on CMOS scaling, and partly due to the aggressive CMOS roadmap requirements. The discussion below concentrates on In 0.53 Ga 0.47 As channel which is the dominant III-V material being pursued for future technology. Despite the narrow focus, fundamental and engineering challenges posed by this material encompass a broad range of material topics including epitaxial growth, crystallographic defects and their dynamics during growth and subsequent processing, clever device architecture to alleviate adverse impact of defects on device leakage, and innovative engineering for material improvement.

This paper presents a comprehensive benchmarking and co-optimization of 6T SRAM bitcells designed with 5nm vertical and lateral gate-all-around nanowire FET technology for the first time. A variety of 6T SRAM bitcells configurations combined with different device integration scenarios will be discussed. Our results show that an ultra-dense SRAM bitcell (0.01 um2) can be achieved with vertical FET architecture. The bitcell designed with vertical FET are preferably targeted for low power applications while the lateral FET-based SRAM bitcells could provide 4.5x higher in performance, but resulting in a penalty of 17x increasing in the leakage current compared to the vertical designs. A Vmin of 0.45 V could be obtained for 122 SRAM bitcells implemented with vertical devices.

A novel stacked MOSFET structure (iFinFET) is proposed to facilitate gate-length scaling to below 10 nm while mitigating the need to form very-high-aspect-ratio (>10:1 height:width) fin structures as for a stacked nanowire gate-all-around (GAA) MOSFET structure. Due to its superior electrostatic integrity, the iFinFET provides for higher performance and is more scalable than a conventional bulk FinFET.

Conventional bulk CMOS scaling starts to fail. In order to prolong the life of Moore's laws, at least one technological booster (innovation) per node has to be introduced starting from the node 32 nm on. This presents a big technological challenge for the semiconductor industry. On the other hand, accumulation of the boosters permits to retrieve healthy scaling down to sub-10 nm gate lengths. This strategy even if technologically very challenging, is prospected to prolong the CMOS competitiveness till at least 2020.

This article first of all outlines the operation of NMOS transistors operating in the strong inversion region. It then goes on to describe weak inversion, or subthreshold mode, operation and how this could be used to overcome the current scaling problems being encountered in CMOS IC manufacture. Also considered are the low-power operating advantages and current frequency limitations. Practical commercial implementations of this technology are presented along with forecasts for its future use in mainstream manufacture.