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The envisaged upgrade of the Large Hadron Collider (LHC) at CERN towards the Super-LHC (SLHC) with a 10 times increased luminosity of 1035 cm-2 s-1 will present severe challenges for the tracking detectors of the SLHC experiments. Unprecedented high radiation levels and track densities and a reduced bunch crossing time in the order of 10 ns as well as the need for cost effective detectors have called for an intensive R&D program. The CERN RD50 collaboration ''Development of Radiation Hard Semiconductor Devices for Very High Luminosity Colliders'' is working on the development of semiconductor sensors matching the requirements of the SLHC. Sensors based on defect engineered silicon like Czochralski, epitaxial and oxygen enriched silicon have been developed. With 3D, Semi- 3D and thin detectors new detector concepts have been evaluated and a study on the use of standard and oxygen enriched p-type silicon detectors revealed a promising approach for radiation tolerant cost effective devices. These and other most recent advancements of the RD50 collaboration are presented.

An option of increasing the luminosity of the Large Hadron Collider (LHC) at CERN to 10^35 cm^(- 2) s(- 1) has been envisaged to extend the physics reach of the machine. An efficient tracking down to a few centimetres from the interaction point will be required to exploit the physics potential of the upgraded LHC. As a consequence, the semiconductor detectors close to the interaction region will receive severe doses of fast hadron irradiation and the inner tracker detectors will need to survive fast hadron fluences of up to above 1016 cm 2. The CERN-RD50 project ''Development of Radiation Hard Semiconductor Devices for Very High Luminosity Colliders'' has been established in 2002 to explore detector materials and technologies that will allow to operate devices up to, or beyond, this limit. The strategies followed by RD50 to enhance the radiation tolerance include the development of new or defect engineered detector materials (SiC, GaN, Czochralski and epitaxial silicon, oxygen enriched Float Zone silicon), the improvement of present detector designs and the understanding of the microscopic defects causing the degradation of the irradiated detectors. The latest advancements within the RD50 collaboration on radiation hard semiconductor detectors will be reviewed and discussed in this work.

We report on the design, manufacturing and first characterisation of pad diodes, test structures and microstrip detectors processed with high resistivity magnetic Czochralski (MCz) p- and n-type Si. The pre-irradiation study on newly processed microstrip detectors and test structures show a good overall quality of the processed wafers. After irradiation with 24 GeV/ c protons up to 4×10 14 cm -2 the characterisation of n-on-p and p-on-n MCz Si sensors with the C – V method show a decrease of the full depletion voltage and no space charge sign inversion. Microscopic characterisation has been performed to study the role of thermal donors in Czochralski Si. No evidence of thermal donor activation was observed in n-type MCz Si detectors if contact sintering was performed at a temperature lower than 380 °C and the final passivation oxide was omitted.

This paper describes the design of a 64times2-pixel array, fabricated in a conventional industrial high-voltage 0.8mum CMOS technology, and aimed at 3D measurements based on the time-of-flight technique. Light signals are detected using a photodiode biased above its breakdown voltage so that an extremely high sensitivity can be achieved exploiting the intrinsic multiplication effect of the avalanche phenomenon. A single photon avalanche diode and dedicated read-out electronics for light pulses arrival-time estimation have been implemented in a 38times180-mum2 pixel with an expected power consumption of about 20 muW. To increase the distance measurement resolution a multiple pulse measurement is used, extracting the mean value of the light pulse arrival-time directly in each pixel; this innovative approach dramatically reduces the dead-time of the pixel read-out, allowing a high frame rate imaging to be achieved

NPN phototransistors have been fabricated on high-purity silicon substrate. The devices have been produced by ITC-IRST in the framework of a National Research Project funded by the Italian Education, University and Research Ministry (MIUR). The phototransistor emitter is composed of a phosphorus n + implant, the base is a diffused high-energy boron implant, and the collector is the 300 μm thick silicon bulk. Several devices have been investigated. Results with 22 keV X-ray from a 109 Cd-radioactive source and visible light irradiation are presented.

We have recently proposed a novel junction termination structure for silicon radiation detectors, featuring all-p-type multiguard and scribe-line implants, with metal field-plates completely covering the gap between the implanted rings. The structure is intended for detector long-term stability enhancement even in adverse ambient conditions and for fabrication-process simplification. A thorough static characterization, including stability measurements in varying humidity conditions, has been carried out on a variety of samples fabricated at ITC-irst. Comparisons with diodes featuring an n-type implant along the border—or no edge structure at all—have been performed. The new structures show stable behaviour at relatively high bias (∼200 V ) , also in the presence of wide humidity changes (1–90%). A good qualitative agreement has been obtained between experimental results and simulation predictions, allowing to gain deep insight into the physical behaviour of the device.

We report on a CMOS integrated photosensor specially tailored for smoke detection applications. A test chip consisting of an integrated photodiode, which reveals the light scattered by smoke particles, and of the related read-out electronics, has been designed and fabricated in 0.8 /spl mu/m CMOS technology. The circuit design is based on the Switched Capacitor (SC) technique, and accomplishes low noise specifications by means of an accurate design of the first read-out stage and by employing Correlated Double Sampling (CDS) filtering blocks. Circuit simulations and preliminary results from the electrical characterization of the first chip prototype allowed the basic design methodology to be validated.

"On-chip" electronics fabricated on 6 K/spl Omega/ cm high resistivity wafer is fully characterized and spectroscopic measurements carried out. A new charge sensitive circuit is introduced to amplify the hole signals with on-chip n-channel JFETs and without any resetting devices. The JFET gate-source junction is forward biased and the drain current is stabilized by a low frequency feedback on the JFET p/sup +/ well contact (used as a buried gate for the JFET). Preliminary setups with PIN diodes and tetrode n-JFETs are successfully tested. With about 5 pF total input capacitance, resolution of 86 rms electrons at 223 K with 10 /spl mu/s shaping time is obtained. With about 3 pF, 60 rms electrons at 298 K with 10 /spl mu/s are obtained.

Since the float-zone (FZ) silicon has lower contaminations and longer minority-carrier lifetime than those in Czochralski silicon and other semiconductor materials, it has potential advantages to fabricate bipolar detectors on the high-purity FZ silicon substrate to achieve a high gain at ultra-low-signal levels. The authors present preliminary experimental results on a bipolar detector fabricated on an unusual high-purity FZ silicon substrate. A backside gettering layer of phosphorus-doped polysilicon was employed to preserve the long carrier lifetime of the high-purity FZ silicon. The device has been investigated in the detection of a continuous flux of X-ray and infrared light. The bipolar detector with a circular emitter of 2 mm diameter has demonstrated high gains up to 3820 for 22 keV X-ray from a 1 mCi Cd radioactive source (the X-ray photon flux, received by the detector is estimated to be B7.77 � 10 4 /s). High gain up to 4400 for 0.17 nW light with a wavelength of 0.83mm has been observed for the same device. r 2003 Elsevier B.V. All rights reserved.

We report on the design of a full-analog current-mode CNN in a 1.2 /spl mu/m CMOS technology, whose cell core is characterized by an intrinsic capability of weights control, low power consumption and small area occupation. Circuit simulations allowed the design approach to be validated and the electrical performance of the CNN to be predicted; moreover, it is shown that the proposed CNN can be successfully adopted for several applications in image processing. A preliminary CNN test-chip consisting of a 8/spl times/1 array for connected component detection and shadow detection, is currently being fabricated at IRST (Trento Italy) in a 2.5 /spl mu/m CMOS technology.

The accuracy of the gated-diode method for extracting bulk generation lifetime and surface generation velocity in high resistivity silicon is shown to depend critically on the gate length of the adopted test device, as a result of nonidealities which are not accounted for by the measurement technique. Minimization of the surface generation velocity measurement error requires the gate length to be suitably reduced, while long gate devices are needed for accurate bulk generation lifetime extraction. Both parameters can be measured from a single test structure obtained by compenetrating a short gate device with a long gate one.

In this paper we report a novel 3D sensor structure to be used as a neutron detector in combination with an organic converter material based on polysiloxane. The first prototypes of the proposed device are presented, with emphasis on the experimental characterization. Selected results from the functional tests (with alpha particle source and pulsed laser scans) are discussed with the aid of TCAD simulations.

We report on Junction Field Effect Transistors and PIN diodes monolithically integrated on high-resistivity silicon by adopting a non-standard technology recently developed at IRST. In particular, a test structure, consisting of a small PIN diode DC-coupled to an integrated n-channel JFET in the double-gate configuration was fully characterised and spectroscopic measurements were carried out by adopting a novel double-feedback charge amplifier circuit. An ENC of about 60 electrons r.m.s. has been obtained at room temperature and at 10 μs shaping time; such a resolution is shown to be determined by the relatively high total capacitance present in this preliminary set-up, associated with the 1/ f series noise of the transistor.

In time-of-flight measurements, or positron emission tomography experiments where two gamma rays are detected in coincidence, the time resolution of the photodetector is of primary importance. SiPMs are very promising devices for these applications, since their intrinsic response time can be less than 1 ns. However the actual timing resolution of SiPM is affected by the area (capacitance) of the device, by the type of used to pre-amplify the signal, by the dark count rate which is revealed as pure noise, and other second order effects like cross-talk and after pulsing. In this work we report the characteristics of different samples of Hamamatsu Photonics (HPK) and Fondazione Bruno Kessler (FBK) SiPM, with pixel size ranging from 40 to 100 μm. In particular, we have investigated their time response when stimulated with O(50) ps pulsed laser at wavelengths in the range 400–800 nm.

A characterization of the response of SiPMs and SPADs produced at FBK-IRST Trento stimulated with fast laser pulses is presented. The tests were aimed at studying both the intrinsic timing proprieties (of SiPMs and SPADs) using the time-correlated single-photon counting technique and the dynamic range (of SiPMs). Measurements were carried out on devices with different cell size, namely, from 40×40 to 100×100 μm2. Concerning the timing resolution, all the devices exhibit a value less than 150 psec FWHM. The dynamic range of SiPMs shows a response linearity which is in line with the theory describing these devices.

This paper is concerned with the preliminary results of a technological study aimed at the development of a fabrication process for double-sided AC-coupled silicon microstrip detectors. The approach adopted for the fabrication of both single-sided and double-sided detectors is presented, and the results from electrical tests performed on detectors and test structures are reported and discussed. Good electrical characteristics as well as an acceptable number of process-related defects have been obtained for these prototype detectors, thus demonstrating the feasibility of fabricating such devices at the IRST facility.

Heavily irradiated p/sup +/-n single-sided microstrip detectors show no dramatic increase in the leakage current due to contributions originating from the cut region, despite, after type inversion, the space-charge region is touching the heavily-damaged, cutting edge, already at zero bias. In this paper, we present both theoretical and experimental results aimed at providing interpretation for such phenomenon. In particular, we show that, for high defect densities at the detector cutting edge, the hole density approaches locally its equilibrium value. Correspondingly, the net generation rate saturates, this ultimately limiting the amount of current which can originate from the detector edge. Measurements from devices irradiated at different fluences are in good agreement with simulation results.

Many applications of silicon p/sup +/-n junctions as detectors require high voltage operation. In particular the LHC experiments, because of the radiation damage level, need very high bias working voltage to fully collect the ionising generated charge multi-guard structures can be used in order to improve the breakdown voltage of microstrip detectors, limiting the occurrence of critical fields in the proximities of a reverse biased p/sup +/-n junction. In this work we present results for different designs of multi-guard structures, before and after irradiation with ionising and non-ionising radiation sources (p,n,/spl gamma/), and for different doses. Various experimental techniques have been used, like DC and AC electrical characterizations, and light emission microscopy. Moreover, a simulation work is presented. Its purpose is to improve the design on the basis of the experimental results.

We describe an activity aimed at developing npn silicon bipolar phototransistors to be used in optical position encoders. Extensive numerical proces and device simulations have been carried out, providing the guidelines for the definition of the phototransistor fabrication process. Results from the electrical and optical characterization of manifactured devices are shown. With respect to the designed fabrication process, only a little adjustment of the technological parameters has been to be necessary to achieve a final product suitable for the intended application.

We report on the development of a radiation-detector compatible JFET technology on high-resistivity silicon for monolithic integration of detectors and front-end electronics. A dedicated test-chip has been designed and fabricated for process and device characterization. Results from the electrical characterization of a first fabrication run show that good values of detector leakage current ( ≈1 nA/cm 2 ) can be obtained in spite of the relatively high thermal budget characterizing the process. As far as the JFET performance is concerned, a problem of insufficient device isolation at high substrate voltages has been evidenced. A second run is currently being carried on with the aim of optimizing the JFET structure.

High-voltage operation can be a solution to obtain full charge collection in strongly irradiated silicon detectors. The maximum bias voltage which can be applied is limited by the breakdown point of the junction. We show how multiguard structures can enhance the breakdown voltage in p+–n silicon devices designed for applications in the LHC environment.

Multiguard structures are used in order to enhance the breakdown voltage of microstrip detectors. In this work we studied the electrical properties of devices designed in four different layouts on n-Si substrates, based on a central diode surrounded by various p/sup +/ and/or n/sup +/ floating rings. In particular we measured the main DC characteristics and we compared the experimental results with those simulated by a two-dimensional drift-diffusion computer model. Device noise was also measured for the central diode as a function of the applied voltage. We repeated all measurements after neutron and gamma irradiation, in view of the application of these devices to silicon microstrip detectors for future high energy physics experiments. For example at the LHC the level of radiation damage expected during the detector lifetime implies very high bias voltages for the detector operation. Multiguards can offer a solution, provided the optimisation of the design takes into account the radiation effects.

Silicon detectors with reduced or no dead volume along the edges have been attracting a lot of interest in the past few years in many different fields. High Energy Physics (HEP) experiments are demanding this feature to ease the assembly of the innermost tracking layers, where space and material budget are usually a concern. At the same time, other applications like X-Ray imaging, are starting to use matrixes of silicon detectors to cover increasingly larger areas and, in order to do so in a seamless way, minimum edge extension is required. In this paper we report on the design and testing of a new edge termination for silicon 3D detectors able to reduce the edge extension to about 50 μm without increasing the fabrication complexity. In addition, the same edge termination can also be applied to planar detectors with little additional process complexity.

We have designed a multi-ring detector (MRD) based on Bismuth Germanate (BGO) crystals, coupled to Silicon PhotoMultipliers (SiPM) for measuring the Ps time of flight (TOF). The set-up geometry was optimized by Monte Carlo simulations to take into account at different Ps velocities: (i) the background noise due to backscattered positrons, (ii) the crosstalk between adjacent detectors, (iii) the lifetime of Ps decay. Three parameters were defined to evaluate the different configurations and a figure of merit was obtained. This allows the choice of the best set up configuration for measuring Ps emitted with a particular energy range, optimizing the signal to noise ratio and keeping the acquisition time acceptable.

Multiguard structures are used in order to enhance the breakdown voltage of microstrip detectors. In this work we studied the electrical properties of devices designed in four different layouts on n-Si substrates, based on a central diode surrounded by various p/sup +/ and/or n/sup +/ floating rings. In particular we measured the main DC characteristics and we compared the experimental results with those simulated by a two-dimensional drift-diffusion computer model. The device noise was also measured for the central diode as a function of the applied voltage. We repeated all measurements after neutron and gamma irradiation, in view of the application of these devices to silicon microstrip detectors for future high energy physics experiments. For example at the LHC the level of radiation damage expected during the detector lifetime implies very high bias voltages for the detector operation. Multiguards can offer a solution, provided the design optimisation takes into account the radiation effects.

PIN radiation detectors and other test-structures have been fabricated on a FZ, high resistivity (2 k/spl Omega//spl middot/cm), n-type silicon substrate by a process that features three different, alternative extrinsic-gettering techniques. Extremely-low leakage-current values have been measured regardless of the gettering technique adopted, this confirming the effectiveness of gettering procedures in limiting the detector leakage current. In particular, devices exploiting a phosphorus-doped polysilicon backside layer as gettering site have shown the best results in terms of leakage-current and generation-lifetime values. Results from the electrical and optical characterization of such devices are reported and discussed. X-ray detection testing is under way.

pMOSFETs biased with V/sub gs/

In this paper we report on the most recent achievements of the ATLAS 3D Sensors Collaboration in the development of silicon 3D sensors. Results from 3D pixels production for the ATLAS Insertable B-Layer (IBL) are presented, showing the high quality and good process reproducibility of the technology. In view of the future detector upgrades at the LHC, a new generation of 3D pixel sensors will be developed. This will require some new ideas and the solution of technological challenges. Both will briefly be addressed in this paper.

Silicon Photomultipliers (SiPMs) are single-photon detectors currently used in many applications as a valid alternative to Photomultiplier Tubes (PMTs). In fact, SiPMs present several advantages compared to PMTs, in terms of size, ruggedness, insensitivity to magnetic fields and voltage supply.In this work, we evaluated the use of SiPMs produced by FBK (Fondazione Bruno Kessler)-AdvanSid (Trento, Italy) in Positronium Time Of Flight (Ps TOF) technique. The aim of this technique is the study of the energy of Ps emitted by porous media for advanced experiments in the field of antimatter physics and, in the future, for open porosities characterization.The TOF spectrometer in operation at the positron beam of the University of Trento (Italy) is based on five gamma detectors composed of NaI(Tl) scintillators coupled to PMTs. We compared the performance of one of these standard detectors against a detector formed by two 4 × 4 mm2 SiPMs coupled to a 4 × 4 × 30 mm3 LYSO (Cerium-doped Lutetium Yttrium Orthosilicate) scintillator. The LYSO+SiPM detector was characterized for timing and energy resolution as well as for the background emission level.It is shown that SiPMs, thanks to their small size and versatility, can be coupled successfully to small scintillators, obtaining more compact detectors with respect to the NaI(Tl)+PMT detectors. The design of an array of detectors with wide angular acceptance and spatial resolution is discussed in order to improve the performances of Ps-TOF setups.

Minimization of the insensitive edge area is one of the key requirements for silicon radiation detectors to be used in future silicon trackers. In 3D detectors this goal can be achieved with the active edge, at the expense of a high fabrication process complexity. In the framework of the ATLAS 3D sensor collaboration, we produced modified 3D silicon sensors with a double-sided technology. While this approach is not suitable to obtain active edges, because it does not use a support wafer, it allows for a new type of edge termination, the slim edge. In this paper we report on the development of the slim edge, from numerical simulations to design and testing, proving that it works effectively without increasing the fabrication complexity of silicon 3D detectors, and that it could be further optimized to reduce the insensitive edge region to less than 100 μm.

A pin photodiode monolithically integrated with a bias resistor and a JFET-based source follower is presented. Results from static and dynamic characterisation of the structure are reported, together with SPICE simulations used to design an optimised device which can be fabricated in the same technology. This structure can be employed as a pixel in linear X-ray scanners for non-destructive inspection.

The authors report the design of a new current-mode A/D converter, based on a modified successive-approximations model, in 1.2 /spl mu/m CMOS technology. The proposed circuit is characterised by good accuracy and fast dynamic performance, low power consumption and small occupation area. SPICE simulations allow the design approach to be validated and the electrical performance of the ADC to be predicted.

A simple modification to an existing current comparator is proposed, which enables a very low response time to be achieved with a minimal increase in circuit complexity. Circuit simulations allowed the design approach to be validated and the comparator performance to be compared to those of two other existing comparators.

We report on the development of a fabrication technology for double-sided, AC-coupled silicon microstrip detectors for tracking applications. Two batches of detectors with good electrical figures and a low defect rate were successfully manufactured at IRST Laboratory. The processing techniques and the experimental results obtained from these detector prototypes are presented and discussed.

Imaging capabilities, spatial resolution and spectroscopic analysis have been performed to compare the characteristics of imaging systems based on pixel detectors of different thickness. Each system consists of a single photon counting chip (PCC), developed in the framework of the Medipix Collaboration, bump bonded to a silicon detector. The detector is a matrix of 64times64 square pixels, with 170 mum pitch and thickness ranging from 300 to 800 mum. As expected, the intrinsic detection efficiency increases with detector thickness (for 22 keV photons the detection efficiency doubles in the examined thickness range), nevertheless the spatial resolution can be affected by a charge sharing mechanism between adjacent pixels due to charge diffusion. We have studied this effect and its dependence on the detector bias voltage and the threshold value of PCC with the aim of optimizing both the detection efficiency and the spatial resolution

We show that a triple-junction photosensor can been obtained within a CMOS n-well technology with no additional process steps but a simple layout modification of the p-channel-stop mask. Results from the electrooptical characterisation of a specially designed test chip proved that the wavelength selectivity of the sensor can be used for colour detection and confirmed the device full compatibility with CMOS technology.

Due to their low depletion voltage, even after high particle fluences, improved tracking precision and momentum resolution and reduced material budget, thin substrates are one of the possible choices to provide radiation hard detectors for future high energy physics experiments. In the framework of the CERN RD50 Collaboration, we have developed p-n diode detectors on membranes obtained by locally thinning the silicon substrate by means of TMAH etching from the wafer back-side. Diodes of different shapes and sizes have been fabricated on 50-/spl mu/m and 100-/spl mu/m thick membranes and tested, showing a low leakage current (about 300 nA/cm/sup 3/) and, as expected, a very low depletion voltage (in the order of 1 V for the 50-/spl mu/m membrane). Radiation damage tests have been performed with 58-MeV Li ions at the SIRAD Irradiation Facility of the INFN National Laboratory of Legnaro, Italy, up to a fluence of 1.83 /spl times/ 10/sup 13/ Li/cm/sup 2/. Moreover, charge collection efficiency tests performed at INFN Firenze with a /spl beta/ particle source have been performed on both non-irradiated and irradiated samples. Results here reported confirm the advantages of thinned diodes with respect to standard ones in terms of low depletion voltage and charge collection efficiency even after the highest ion fluence.

A novel termination structure for silicon microstrip detectors is proposed, featuring all-p-type multiguards and scribe-line implant, as well as inward metal field-plates providing almost complete coverage of the passivation-oxide external surface. The structure is intended for detector long-term stability improvement and fabrication-process simplification. Proper design of the multiguard layout enables a very stable behavior at relatively high bias voltages to be achieved.

In this work we report on the design, fabrication, electrical characterization and sensing tests of new silicon bipolar junction phototransistors, coated by Zn-(heptiloxy)-TPP. The finger-shaped emitter/base junction has been proved to enhance the responsivity in the blue spectral region with respect to the standard fully implanted detector (0.24A/W and 0.14A/W respectively at 5 V reverse bias). This effect has been experimentally tested in reverse biased E/B junction and, even though the phototransistor is operated with floating base, slightly forward biasing the E/B junction, this improvement in responsivity was still observed. The new transducers exhibit a beta current gain higher than 150 and were employed to detect ethanol concentrations down to 300ppm.

In this contribution, new developments on the silicon photomultipliers (SiPMs) fabricated at FBK-irst (Trento, Italy) are reported. With respect to the first series of devices produced in 2005/2006, there have been major improvements on both the the layout and the technology. Concerning the first aspect we fabricated SiPMs with increased fill factor and with different geometries (square/circular devices, arrays and matrices of SiPMs) to meet the requirements of different applications. Concerning the technology, we identified a process technique able to reduce significantly the dark count rate. In this paper we will describe the main electro-optical characteristics of these devices.

A novel termination structure for silicon microstrip detectors is proposed, featuring all p-type multiguard and scribe-line implants, as well as inward metal field-plates providing almost complete coverage of the passivation-oxide external surface. The structure is intended for detector long-term stability improvement and fabrication-process simplification. Proper design of the multiguard layout enables a very stable behavior at relatively high bias voltages to be achieved both prior and after 1/spl times/10/sup 12/ cm/sup -2/ neutron irradiation.

Radiation hardness of silicon detectors based on thin epitaxial layer for the LHC upgrade was studied. No type inversion was observed after irradiation by 24 GeV protons in the fluence range (1.5–10)⋅1015 cm–2 due to overcompensating donor generation. After long-term annealing highly irradiated devices show decrease of effective doping concentration and then undergo type inversion. All mentioned means that thin epitaxial devices might be used for innermost layers of vertex detectors and need moderate cooling during beam off time. Properly chosen scenario might help to restore their working characteristics.

We show that the accuracy of the gated diode method for measuring bulk generation lifetime and surface generation velocity in high resistivity silicon depends critically on the gate length of the test device, as a result of nonidealities affecting the gated diode operation. Minimization of the surface generation velocity measurement error requires the gate length to be suitably decreased, while long gate length structures are needed for accurate bulk generation lifetime extraction.

3DJAM is a novel 3D image sensor, implemented with a 3.3V, 0.35mum CMOS technology, that combines the optical triangulation (OT) and the indirect time of flight (I-TOF) techniques in a single chip for range finding scanners. It has been designed to cover very large depth scenes (up to 20 meters), achieving sub-millimeter resolution over the OT range (below 2 meters), working with a single pulsed laser source and also taking advantage of ambient light removal. The chip embeds also a programmable logic unit, which supervises over all the internal functions (like timing, pipelining, data transfer), a power supply unit (for both the analogue and the digital subsystems) and an analogue output buffer that can drive an external ADC for data acquisition

We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures.

A 128/spl times/64 pixel image sensor in 0.35 /spl mu/m 3.3V CMOS technology achieves 138 dB dynamic range by adapting single-pixel integration time to the local illumination conditions. Video frame rate is achieved with 0.2% rms temporal noise and 14 mW power in a test chip.