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Hybrid pixel radiation detectors with a direct photon-to-charge conversion working in a single photon counting mode have gained increasing attention due to their high dynamic range and noiseless imaging. Since sensors of different materials can be attached to readout electronics, they enable work with a wide range of photon energies. The charge-sharing effect observed in segmented devices, such as hybrid pixel detectors, is a phenomenon that deteriorates both spatial resolution and detection efficiency. Algorithms that allow the detection of a photon irrespective of the charge-sharing effect are proposed to overcome these limitations. However, the spatial resolution of the detector can be further improved beyond the resolution determined by the pixel size if information about the charge proportions collected by neighbouring pixels is used to approximate the interaction position. In the article, an approach to achieve a subpixel resolution in a hybrid pixel detector working in the single photon counting mode is described. Requirements and limitations of digital inter-pixel algorithms which can be implemented on-chip are studied. In the simulations, the factors influencing the detector resolution are evaluated, including size of a charge cloud, number of virtual pixel subdivisions, and detector parameters. [ABSTRACT FROM AUTHOR]

In this work, we evaluated the performance of the prototype SFOV MediPROBE developed at the University of Naples Federico II through the protocol proposed by (Bhatia B.S. Bugby S.L. Lees J.E. Perkins A.C. A scheme for assessing the performance characteristics of a small field of-view gamma cameras. Physica. Medica. 31 (1), pp. 98–103. (2015) doi: 10.1016/j.ejmp.2014.08.004). We extensively investigated a new device configuration where the pinhole collimator was placed outside the housing of the probe, in order to increase the system spatial resolution, and the pixel size was doubled, in order to reduce the charge sharing effect. The experimental measurements show that the spatial resolution is enhanced by only about 10%, but the sensitivity decreases strongly. Therefore, the trade-off between these two features does not seem to be advantageous. In addition, our experiments suggest that the charge sharing effect is not completely canceled. Despite these results, the features of this device appear suitable for intraoperative surgical survey. We aim to use this device in the clinical practice for the intraoperative imaging of lymph nodes, breast, thyroid and parathyroid tumors. [ABSTRACT FROM AUTHOR]

Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, twoinput EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods. [ABSTRACT FROM AUTHOR]

Cubic and tetragonal phases of Cd 3 Y 2 (Y= N, P and As) compounds are studied using full potential approach of density functional theory. All the studied crystal structures were fully optimized using the generalized gradient approximation. Calculated structural parameters agree well with experimental measurements. Electronic band profiles reveal metallic nature of Cd 3 Y 2 in both phases except Cd 3 P 2 which is semiconductor with small band gap value. The charge sharing is dominant in cubic and tetragonal phases which show covalent bond nature. Optical properties of the compounds are studied in detail in both phases. Interestingly, it is revealed that the intraband transitions play vital rule in explaining the optical properties in the metals while no influence observed in the Dirac semi-metal and semiconducting nature in these compounds. The reflectivity of metallic behavior compounds Cd 3 P 2 and Cd 3 As 2 reached up to 90% with the intra band calculation. [ABSTRACT FROM AUTHOR]

Timing error predictors have a strong potential to reduce the worst case timing margins by monitoring timing slack of a design. However, these timing error predictors incur substantial amount of silicon area and power which limit the overall benefits in the system level. This paper presents a low overhead warning flip-flop (FF), which predicts setup time violations. It consists of a delay buffer and a warning generator along with a conventional master-slave FF. Low overhead FF can be designed by exploiting the concept of charge sharing to implement the warning generator. As the warning generator requires only seven transistors to predict the timing violation, the proposed warning FF occupies 30% less area and consumes 27% less power compared to the state-of-the-art timing error predictors. A test chip is fabricated using the proposed FF in a 130-nm CMOS technology to verify the functionality of the proposed warning FF in dynamic voltage and frequency scaling applications. Measurement results from the test chip show that a performance improvement of 44% can be achieved at a supply voltage of 0.9 V by employing the proposed technique compared to the worst case design. For a typical chip, the power consumption can be reduced by 36% compared to the worst case design. [ABSTRACT FROM AUTHOR]

Pulse width of single event transient can be shrunk by pulse quenching effect in combinational circuits. And it is found that the pulse quenching effect is closely related to the layout of the circuits. In this paper, we propose a placement method for reducing soft errors in combinational circuits by increasing the number of quenching unit and enhancing the pulse quenching effect between them. To evaluate the soft error automatically, an evaluation platform is also implemented and embedded into commercial EDA tools with our placer. Simulation results show that our proposed method can reduce the soft error vulnerabilities by 14%–26%. [ABSTRACT FROM AUTHOR]

Existing secure adiabatic logic designs use charge sharing inputs to deliver input independent energy dissipation and suffer from non-adiabatic losses (NAL) during the evaluation phase of the power-clock. However, using additional inputs present the overhead of generation, scheduling, and routing of the signals. Thus, we present “Without Charge-Sharing Quasi-Adiabatic Logic”, WCS-QuAL which doesn't require any charge sharing inputs and completely removes the NAL. The pre-layout and post-layout simulation results of the gates show that WCS-QuAL exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) against all process corner variations at frequencies ranging from 1 MHz to 100 MHz. It also shows least variations in average energy dissipation at all five process corners. The simulation results show that the 8-bit Montgomery multiplier using WCS-QuAL exhibits the least value of NED and NSD at all the simulated frequencies and against power-supply scaling and dissipates the lowest energy at frequencies ranging from 20 MHz to 100 MHz. [ABSTRACT FROM AUTHOR]

This paper presents a charge-sharing switching scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) in biomedical applications. By using the charge sharing between two capacitor arrays to generate binary-weighted voltage-changes sequentially on the dummy capacitor, which is used to compare the multiple low bits, the proposed switching method enhances the efficiency of switching energy by 99.51% and achieves a 93.55% reduction in the total capacitor size, compared with the conventional SAR ADC. [ABSTRACT FROM AUTHOR]

In this paper, a low power and crosstalk avoidance coding called Crosstalk Avoidance Green Coding (CAGC) is proposed and combined with capacitively charge-sharing transmitter (CCS) to provide reliable and energy-efficient interconnections for network-on-chip (NoC). The proposed CAGC consists of Green Modified Coding (GMC) and Adaptive Temporal Coding (ATC). The GMC achieves more energy reduction by modifying the mapping between original set and converted set. And the ATC reduces crosstalk by transmitting a shielding code in the case of Worst-Case-Crosstalk (WCC). In order to further reduce the power consumption of NoCs, CCS is applied to achieve a swing-voltage reduction to 10% of the supply voltage. Based on SMIC 0.13 μm CMOS technology, the simulation results show that CAGC and CCS can achieve 37.51% and 73% energy reduction compared to the full swing transmitter without low power codec, respectively. However, the combination of CAGC and CCS not only achieves 81% energy reduction, but also increases reliability by improving the ability of crosstalk avoidance. [ABSTRACT FROM AUTHOR]

This paper presents a passive-charge-sharing successive approximation register (SAR) analog-to-digital converter (ADC) that achieves 16-bit linearity. It is known that on-chip passive charge sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. This paper gives a detailed analysis for the reasons of poor linearity for passive-charge-sharing SAR ADCs and proposes solutions. The proposed ADC architecture with one-reference-cap-per-bit and short switches addresses the issue of signal-dependent reference voltage droop during SAR ADC bit trials and orthogonalizes the bit weights. The calibration technique presented further calibrates the ADC to 16-bit linearity. In addition, the proposed architecture maximizes SNR by sampling on to the digital-to-analog converter (DAC) capacitor array, the first reported in this type of SAR ADC. This paper provides the foundation of building a precision SAR ADC out of on-chip reference capacitors. Measurement result from a prototype test chip shows ±0.8 LSB (16-bit level) integrated non-linearity at 1 MSPS. [ABSTRACT FROM AUTHOR]

We evaluated the sub-pixel position resolution achievable in large-volume CdZnTe pixelated detectors with conventional pixel patterns and for several different pixel sizes: 2.8 mm, 1.72 mm, 1.4 mm and 0.8 mm. Achieving position resolution below the physical dimensions of pixels (sub-pixel resolution) is a practical path for making high-granularity position-sensitive detectors, <100 μ m, using a limited number of pixels dictated by the mechanical constraints and multi-channel readout electronics. High position sensitivity is important for improving the imaging capability of CZT gamma cameras. It also allows for making more accurate corrections of response non-uniformities caused by crystal defects, thus enabling use of standard-grade (unselected) and less expensive CZT crystals for producing large-volume position-sensitive CZT detectors feasible for many practical applications. We analyzed the digitized charge signals from a representative 9 pixels and the cathode, generated using a pulsed-laser light beam focused down to 10 μ m (650 nm) to scan over a selected 3 × 3 pixel area. We applied our digital pulse processing technique to the time-correlated signals captured from adjacent pixels to achieve and evaluate the capability for sub-pixel position resolution. As an example, we also demonstrated an application of 3D corrections to improve the energy resolution and positional information of the events for the tested detectors. [ABSTRACT FROM AUTHOR]

An active target detector array, ANASEN, has been developed for nuclear reaction studies with rare isotope beams at low energies. It aims at measurements of the excitation functions for proton and α - particle elastic and inelastic scattering and direct measurements of ( α , p) reactions with exotic nuclei in inverse kinematics. ANASEN is composed of three types of charged particle detectors. The length of the active area is 340 mm and the total covered area is 1300 cm 2 (almost 3 π steradian solid angle coverage) providing high efficiency for experiments with low intensity radioactive beams. A mix of 78 conventional electronics channels (for Proportional Counter and CsI-detectors) and 480 dedicated high-density ASICs electronics channels for the silicon detector are used for readout. [ABSTRACT FROM AUTHOR]

An energy-efficient analog SRAM (A-SRAM) is proposed to eliminate redundant analog-to-digital (A/D) and digital-to-analog (D/A) conversion in mixed-signal systems, such as neuromorphic chips and neural networks. D/A conversion is integrated into the SRAM readout by charge sharing of the proposed split bitline (BL). Also, A/D conversion is integrated into the SRAM write operation with the successive approximation method in the proposed input–output block. Also, a configurable SRAM bitcell array is proposed to allocate the converted digital data without unfilled bitcells. The multirow access decoder selects multiple bitcells in a single column and configures the bitcell array by controlling the BL switches to split BLs. The proposed A-SRAM is implemented using the 65-nm CMOS technology. It achieves 17.5-fJ/bit energy-efficiency and 21-Gbit/s throughput for the analog readout, which are 64% and 1.3 times better than those of the conventional SRAM followed by a digital-to-analog converter (DAC). Also, the area is reduced by 91% compared with the conventional SRAM with analog-to-digital converter (ADC) and DAC. [ABSTRACT FROM AUTHOR]

A novel high-voltage single-emitter horizontal current bipolar transistor (HCBT) is presented. Breakdown voltage improvement compared to high-speed transistor is obtainedwith full depletion of the intrinsic collectorby using implanted CMOS p-well region. Transistors with \text BV\text {CEO} = {10.5} V and fT = {15.8} GHz are demonstrated. Higher operating currents can be easily obtained by stretching the emitter length resulting in a flexible physical design of circuits. The transistor is fabricated in 0.18- \mu \textm HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks. [ABSTRACT FROM AUTHOR]

In this paper, we apply the common centroid layout technique in a differential latch structure (i.e., Quatro) and evaluate its effectiveness in reducing single event upset vulnerability. SPICE simulations demonstrate that higher charge sharing efficiency between the differential pair of sensitive devices results in higher critical charge of the latch. Both regular and common centroid layouts show the same heavy ion upset Linear Energy Transfer (LET) threshold because this is determined by the worst case critical charge (i.e., there is no charge sharing). Additionally, the magnitude decrease in the cross section of common centroid layout than that of the regular layout is not significant in 130-nm CMOS bulk technology because cross section covers the highest charge sharing efficiency and the lowest charge sharing efficiency from statistical point of view. [ABSTRACT FROM AUTHOR]

In this paper, an “S-like” inverter chains (SLIC) test structure is designed for the separation measurement of $N$ -hit and $P$ -hit charge sharing. The heavy-ion experiments were performed in 65-nm bulk dual-well and triple-well technology, and the $N$ -hit and $P$ -hit pulse quenching (PQ) span is attained. The results has verified the ability of the “SLIC” test structure to characterize $P$ -hit and $N$ -hit PQ, and the results also indicate that the N+ deep well can enhance the action extent of $N$ -hit charge sharing greatly though it will reduce the action extent $P$ -hit charge sharing. [ABSTRACT FROM PUBLISHER]

This paper proposes a splittable amplifier technique that can be either decomposed into two identical halves or merged for enhancing the utilization of the amplifier power and alleviating the memory effect, when applying operational amplifier (opamp) sharing. In a two-phase clock system, the amplifier can be split into two identical small amplifiers in one phase simultaneously for use in two circuits. Next, the two small amplifiers can be merged into one amplifier in the other phase for usage in another circuit. Compared with the conventional opamp sharing, a more power-efficient amplifier arrangement is achieved in the split mode. In this paper, three individual sample-and-hold (S/H) circuits with the proposed technique are designed to demonstrate the efficiency of memory effect cancellation. The simulations show that in contrast to the output spectrum of two S/H circuits with conventional opamp sharing, the spurious tones due to the memory effect can be suppressed by at least 14.66 dB in the split mode and at least 7.32 dB in the combination mode with a 0.6-VP-P input signal when using the proposed technique. [ABSTRACT FROM AUTHOR]

The charge-sharing (CS) switching scheme appeared recently as an alternative to the charge-redistribution (CR) ADC for moderate-resolution low-power applications. One advantage of the CS is that it requires less demanding reference and input buffers. On the other hand, the CS ADC is very sensitive to the comparator offset, because the latter is translated into non-linearity on the ADC transfer curve. This paper examines the mechanism that causes this non-linearity and proposes a closed-form expression for the maximum effective resolution that a CS ADC may achieve in the presence of comparator offset. Finally, the model is verified with behavioral simulations. [ABSTRACT FROM AUTHOR]

Purpose: An x-ray photon interacts with photon counting detectors (PCDs) and generates an electron charge cloud or multiple clouds. The clouds (thus, the photon energy) may be split between two adjacent PCD pixels when the interaction occurs near pixel boundaries, producing a count at both of the pixels. This is called double-counting with charge sharing. (A photoelectric effect with K-shell fluorescence x-ray emission would result in double-counting as well). As a result, PCD data are spatially and energetically correlated, although the output of individual PCD pixels is Poisson distributed. Major problems include the lack of a detector noise model for the spatio-energetic cross talk and lack of a computationally efficient simulation tool for generating correlated Poisson data. A Monte Carlo (MC) simulation can accurately simulate these phenomena and produce noisy data; however, it is not computationally efficient. Methods: In this study, the authors developed a new detector model and implemented it in an efficient software simulator that uses a Poisson random number generator to produce correlated noisy integer counts. The detector model takes the following effects into account: (1) detection efficiency; (2) incomplete charge collection and ballistic effect; (3) interaction with PCDs via photoelectric effect (with or without K-shell fluorescence x-ray emission, which may escape from the PCDs or be reabsorbed); and (4) electronic noise. The correlation was modeled by using these two simplifying assumptions: energy conservation and mutual exclusiveness. The mutual exclusiveness is that no more than two pixels measure energy from one photon. The effect of model parameters has been studied and results were compared withMCsimulations. The agreement, with respect to the spectrum, was evaluated using the reduced χ² statistics or a weighted sum of squared errors, χ² red (≥1), where χ² red = 1 indicates a perfect fit. Results: The model produced spectra with flat field irradiation that qualitatively agree with previous studies. The spectra generated with different model and geometry parameters allowed for understanding the effect of the parameters on the spectrum and the correlation of data. The agreement between the model and MC data was very strong. The mean spectra with 90 keV and 140 kVp agreed exceptionally well: χ² red values were 1.049 with 90 keV data and 1.007 with 140 kVp data. The degrees of cross talk (in terms of the relative increase from single pixel irradiation to flat field irradiation) were 22% with 90 keV and 19% with 140 kVp for MC simulations, while they were 21% and 17%, respectively, for the model. The covariance was in strong agreement qualitatively, although it was overestimated. The noisy data generation was very efficient, taking less than a CPU minute as opposed to CPU hours for MC simulators. Conclusions: The authors have developed a novel, computationally efficient PCD model that takes into account double-counting and resulting spatio-energetic correlation between PCD pixels. The MC simulation validated the accuracy. [ABSTRACT FROM AUTHOR]

A novel concept of a layer-wise produced semiconductor sensor for precise particle tracking is proposed herein. In contrast to common semiconductor sensors, local regions with increased doping concentration deep in the bulk termed charge guides increase the lateral drift of free charges on their way to the read-out electrode. This lateral drift enables charge sharing independent of the incident position of the traversing particle. With a regular grid of charge guides the lateral charge distribution resembles a normalised Pascal׳s triangle for particles that are stopped in depths lower than the depth of the first layer of the charge guides. For minimum ionising particles a sum of binomial distributions describes the lateral charge distribution. This concept decouples the achievable sensor resolution from the pitch size as the characteristic length is replaced by the lateral distance of the charge guides. [ABSTRACT FROM AUTHOR]

The linearity of the vast majority of the ADC topologies is limited by the linearity of the circuit elements employed in their design, such as resistors and capacitors. This paper presents a charge-mode SAR ADC architecture that uses only highly non-linear metal-oxide-semiconductor capacitors (MOSCAPs) as the DAC capacitance elements. The non-linearity of the MOSCAPs is exploited to improve the tolerance of the ADC to comparator offset and noise. The architecture employs local voltage boosting and a new boost-and-bootstrap switch to allow operation with an over-rails input range. A 9 bit prototype is fabricated in a 0.13 \;\upmu\textm CMOS process and operates with a supply voltage of 0.6 V, handling a differential input range of 1.7\; \textV_\textpp. The prototype achieves an effective number of bits (ENOB) larger than 8.5 for a temperature range of $-40$ to 85°C, despite the strong dependency of MOSCAPs to temperature. Operating at 1 MSps, the prototype consumes 2.78 \;\upmu\text{W}, leading to a figure of merit (FoM) of 7.8 fJ/conversion-step. [ABSTRACT FROM PUBLISHER]

As the complementary metal oxide semiconductor feature size shrinks further, single event multiple transients (SEMTs) become more serious. However, SEMTs have not yet been appropriately modelled through traditional soft error rate (SER) estimation methods. Therefore, this paper presents a mixed-level framework to estimate SER induced by SEMTs. The precision of the proposed framework is verified through HSPICE simulation. The results show that multiple pulses and convergence of SEMTs significantly affect SER estimation. [ABSTRACT FROM PUBLISHER]

The spatial and energy resolution of hybrid photon counting pixel detectors like the Timepix detector can suffer from charge sharing. Due to diffusion an initially point-like charge carrier distribution generated by ionizing radiation becomes a typically Gaussian-like distribution when arriving at the pixel electrodes. This leads to loss of charge information in edge pixels if the amount of charge in the pixel fall below the discriminator threshold. In this work we investigated the reduction of charge sharing by applying a magnetic field parallel to the electric drift field inside the sensor layer. The reduction of diffusion by a magnetic field is well known for gases. With realistic assumptions for the mean free path of charge carriers in semiconductors, a similar effect should be observable in solid state materials. We placed a Medipix-2 detector in the magnetic field of a medical MR device with a maximum magnetic field of 3 T and illuminated it with photons and α -particles from 241 Am. We observe that with a magnetic field of 3000 mT the mean cluster size is reduced by ~ 0.75 % . [ABSTRACT FROM AUTHOR]

A built-in single event upsets (SEUs) detector is presented in this paper. This detector utilizes charge sharing to detect an SEU in a sequential cell, and the detection process is analyzed through Accuro simulations in a 65 nm technology. The normal operation of this detector would not induce obvious performance degradation of the target circuit. Through using this detector, error correction can be achieved based on dual modular redundancy (DMR) while the related power is about 20.4 % lower than that induced by triple modular redundancy (TMR). [ABSTRACT FROM AUTHOR]

Due to the intrinsic lack of restoring paths, dynamic logic circuits have significant single-event susceptibility, and thus, they are not preferred in applications requiring high reliability when compared to static logic. However, in high speed applications, this circuit family is still very attractive. This papers presents two layout-based single-event resilient dynamic logic designs. The resultant SET pulse is suppressed because of charge-sharing in the layout-level. Simulation results verify that they enjoy higher single event tolerance. Experimental results validate the fact that approximately 20 ~ 30 % of magnitude reduction in cross-section is achieved in both designs. On the other hand, the increase in single-event performance is achieved at the expense of power and area overheads of 10 and 15 %, respectively, using our layout style in 130 nm CMOS bulk technology. [ABSTRACT FROM AUTHOR]

Cadmium Zinc Telluride (CZT) semiconductor detectors are capable of providing superior energy resolution and three-dimensional position information of gamma ray interactions in a large variety of fields, including nuclear physics, gamma-ray imaging and nuclear medicine. Some dedicated Positron Emission Tomography (PET) systems, for example, for breast cancer detection, require higher contrast recovery and more accurate event location compared with a whole-body PET system. The spatial resolution is currently limited by electrode pitch in CZT detectors. A straightforward approach to increase the spatial resolution is by decreasing the detector electrode pitch, but this leads to higher fabrication cost and a larger number of readout channels. In addition, inter-electrode charge spreading can negate any improvement in spatial resolution. In this work, we studied the feasibility of achieving sub-pitch spatial resolution in CZT detectors using two methods: charge sharing effect and transient signal analysis. We noted that their valid ranges of usage were complementary. The dependences of their corresponding valid ranges on electrode design, depth-of-interaction ( DOI ), voltage bias and signal triggering threshold were investigated. The implementation of these two methods in both pixelated and cross-strip configuration of CZT detectors were discussed. Our results show that the valid range of charge sharing effect increases as a function of DOI , but decreases with increasing gap width and bias voltage. For a CZT detector of 5 mm thickness, 100 µm gap and biased at 400 V, the valid range of charge sharing effect was found to be about 112.3 µm around the gap center. This result complements the valid range of the transient signal analysis within one electrode pitch. For a signal-to-noise ratio (SNR) of ~17 and preliminary measurements, the sub-pitch spatial resolution is expected to be ~30 µm and ~250 µm for the charge sharing and transient signal analysis methods, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we propose and demonstrate the first fully integrated surface acoustic wave (SAW)-less superheterodyne receiver (RX) for 4G cellular applications. The RX operates in discrete-time domain and introduces various innovations to simultaneously improve noise and linearity performance while reducing power consumption: a highly linear wideband noise-canceling low-noise transconductance amplifier (LNTA), a blocker-resilient octal charge-sharing bandpass filter, and a cascaded harmonic rejection circuitry. The RX is implemented in 28-nm CMOS and it does not require any calibration. It features NF of 2.1–2.6 dB, an immeasurably high input second intercept point for closely-spaced or modulated interferers, and input third intercept point of 8–14 dBm, while drawing only 22–40 mW in various operating modes. [ABSTRACT FROM PUBLISHER]

Following our successful demonstration of the position-sensitive virtual Frisch-grid detectors, we investigated the feasibility of using high-granularity position sensing to correct response non-uniformities caused by the crystal defects in CdZnTe (CZT) pixelated detectors. The development of high-granularity detectors able to correct response non-uniformities on a scale comparable to the size of electron clouds opens the opportunity of using unselected off-the-shelf CZT material, whilst still assuring high spectral resolution for the majority of the detectors fabricated from an ingot. Here, we present the results from testing 3D position-sensitive 15×15×10 mm 3 pixelated detectors, fabricated with conventional pixel patterns with progressively smaller pixel sizes: 1.4, 0.8, and 0.5 mm. We employed the readout system based on the H3D front-end multi-channel ASIC developed by BNL's Instrumentation Division in collaboration with the University of Michigan. We use the sharing of electron clouds among several adjacent pixels to measure locations of interaction points with sub-pixel resolution. By using the detectors with small-pixel sizes and a high probability of the charge-sharing events, we were able to improve their spectral resolutions in comparison to the baseline levels, measured for the 1.4-mm pixel size detectors with small fractions of charge-sharing events. These results demonstrate that further enhancement of the performance of CZT pixelated detectors and reduction of costs are possible by using high spatial-resolution position information of interaction points to correct the small-scale response non-uniformities caused by crystal defects present in most devices. [ABSTRACT FROM AUTHOR]

In this paper, a novel uniform vertical inverter chains (UniVIC) single event multiple transient (SEMT) test structure is proposed for the first time. Charge sharing between standard inverters is measured for the first time experimentally. The heavy-ion experiment results in 65 nm bulk CMOS process indicate that charge sharing can impact three transistors at most. At the same time, the occurring probability of charge sharing is attained for the first time experimentally. 3D TCAD simulations have also verified them. In total, the conclusions are helpful for researchers to have a direct knowledge of charge sharing in concrete circuits, and then to improve the precise of soft error evaluation. [ABSTRACT FROM AUTHOR]

The ambipolar-diffusion-with-cutoff (ADC) model is extended to estimate the single-event-induced collected charge for multiple transistors for circuits simulation. The proposed improvement in the model includes both parasitic-bipolar and charge-sharing effects for a given technology. Simulation results indicate excellent agreement between the proposed model and published TCAD data for 130, 90, 65, and 40 nm technology nodes. A comparison between ADC and both rectangular parallelepiped (RPP) and integral rectangular parallelepiped (IRPP) models indicates a 2.7\times and 2.5\times lower error in estimating collected charge when compared with TCAD data. The ADC average error was estimated to be 7.1 fC and for the RPP and IRPP about 19.1 fC and 17.5 fC, respectively, across the technologies for particles with the linear energy transfer range from 1 - 30~\MeV-cm^2/\mg. [ABSTRACT FROM PUBLISHER]

As chip technologies scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes. The so-called pulse quenching effect, induced by single-event charge sharing collection, has been widely explored in efforts to find mitigation techniques for single-event transients (SETs) or single-event upsets (SEUs), and the dummy gate isolation has been proven to be an efficient layout technique for pulse quenching enhancement. In this paper, the characterization of SET pulse quenching among dummy gate isolated logic nodes is performed in 65 nm twin-well and triple-well CMOS technologies. Four groups of heavy ion experiments are explored for the characterization, and the pulse quenching effect is quantitatively analyzed in detail. The pulse quenching effects show different characteristics in twin-well and triple-well CMOS technologies. [ABSTRACT FROM AUTHOR]

Ternary content addressable memory (TCAM) is used for high-speed table look-up. A match-line (ML) sensing scheme to reduce energy consumption in ML during look-up is presented. The look-up is performed in two steps. In the first step, small segment of each TCAM word is compared with the search key to detect most of the mismatched words. These words remain deactivated in the next step causing energy saving. In the second step, the charge stored in a matched ML first segment is recycled by allowing charge sharing with second ML segment. Charge recycling and absence of ML charging from power supply make total energy consumption low. Post-layout simulation of the scheme implemented using 180 nm 1.8 V CMOS logic shows that for a search time of 2479 ps, the scheme can provide larger noise margin than some popular techniques. It offers at least 80%, 31%, and 29% energy savings compared to the conventional, current-race, and state of the art charge sharing scheme, respectively. For 32 nm technology node, the energy savings are at least 46% and 15% compared to the current-race and the existing charge sharing scheme, respectively. [ABSTRACT FROM PUBLISHER]

This paper proposes an adaptive charge sharing (ACS) method for reducing power consumption in liquid crystal displays (LCDs). Our ACS method involves calculating the power consumption of all data lines assuming the charge is shared and analyzing the analog characteristics of the data transitions. With conventional CS, charge is shared between data lines only when the polarities of data signals change. Our ACS method selectively shares charge even when no polarity change occurs, but only if CS provides an overall reduction in power consumption. To compare the performance of ACS and conventional CS, we applied the ACS method to common inversion methods, namely, column, two-dot, and Z inversion. Our simulation results demonstrate that the ACS method can effectively reduce power consumption, especially with the column and Z inversion methods. The average power consumption of the ACS method with column and Z inversion was 87.7% and 84.7%, respectively, of the conventional CS power consumption. [ABSTRACT FROM AUTHOR]

A novel, multi-point contact high-purity germanium detector has been developed for applications in high-rate gamma environments. The planar detector was fabricated with seven point contacts, a high-voltage steering grid and bias electrode using amorphous germanium technology. We have characterized this detector and report herein on the depletion profile, leakage current, energy resolution, and charge-sharing behavior. [ABSTRACT FROM PUBLISHER]

Recent years, the hardening of combinational circuits is becoming a common concern. Unlike the transistor-level hardening technique, the cell-level hardening technique, a divide and conquer strategy, can substantially make use of some typical character in the cell-circuit module to mitigate single event transient (SET) sensitivity. The mirror image (MI) technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure. 3D TCAD mixed-mode simulation have been performed in 65 nm twin-well bulk CMOS process, the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25 %, and can mitigate the SET pulse width from the posterior-stage PMOS about 10 %. The MI technique, a represent of the cell-level technique, may be the future of the hardening of combinational circuits. [ABSTRACT FROM AUTHOR]

The motivation for single event effects (SEE) analysis and mitigation as part of the process for adaptation of a commercial Field Programmable Gate Array (FPGA) architecture for space-qualified applications is discussed. The interdependent roles of heavy-ion and laser-induced upset evaluation coupled with computer-aided investigations of SEE mechanisms and mitigation techniques in this process are shown to enable a significant reduction in SEE sensitivity of the device, while achieving minimal impact on remanufacturing steps. [ABSTRACT FROM PUBLISHER]

Technology scaling increases the role of charge sharing and bipolar effect with respect to multiple cell upset. We analyze the contributions of cell distance and well-contact density to suppress MCU by device-level simulations and neutron experiments. Device simulation results reveal that the ratio of MCU to SEU exponentially decreases by increasing the distance between redundant latches. MCU is suppressed when well contacts are placed between redundant latches. Experimental results also show that the ratio of MCU to SEU exponentially decreases by increasing the distance between cells. MCU is suppressed effectively by increasing the density of well contacts. [ABSTRACT FROM PUBLISHER]

The SLS detectors group has a longstanding history in the development of hybrid X-ray detectors for synchrotrons [1]. Hybrid detectors consist of a sensor (usually silicon) absorbing the photons and front-end electronics transforming the charge into a measurable signal. The two parts are distinct and can therefore be optimized separately, depending on the application. The group has the know-how to design sensors and Read-Out Chips (ROC) in-house, assemble the detectors with a high yield for a large number of channels (both wire- and bump-bonding), and develop data acquisition systems and software. The detectors must provide high-quality data and be reliable for the daily user operation at the beamlines. They are normally developed to target specific applications, and particular effort is put into the integration of the systems at the beamlines and on their reliability. The detector group works in close connection with the beamline scientists of the SLS as early as the development phase and then later to train them in operating the detectors in an optimized way and in supporting the final users. [ABSTRACT FROM AUTHOR]

A charge-domain SAR ADC is presented which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors as sampling capacitor for passive amplification to relax the comparator noise requirements without compromising linearity. The prototype in 40 nm low power CMOS process consists of a 1.1–17.6 mS transconductor, combined with a 10 b 0–80 MS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45 mA from a 1.1 V supply and achieves a peak SNDR of 56.85 dB at 40 MS/s. [ABSTRACT FROM PUBLISHER]

The fault tolerance of CMOS D and RS flip-flops with a two-phase structure and memory cells based on them under exposure to single nuclear particles depends on the response to charge collection by several nodes. The relation between pairs of nodes with identical critical characteristics and specifics of symmetry of electric couplings between trigger transistors was established for DICE and Quatro cells. Critical pairs of nodes with minimal critical charges and an increased noise immunity were determined. The guidelines for mutual arrangement of transistors in DICE cells were given. The examples of quantitative estimation of critical dependences were given for cells with a 65 nm bulk CMOS design rule. DICE cells have an advantage in the event of multiple influence on the nodes. [ABSTRACT FROM AUTHOR]

We report on the electrical properties of current annealed graphene and few layer graphene devices. It is observed that current annealing for several hours results the n-type doping in the graphene layers. After current annealing, Dirac point start to shift toward positive gate voltage and saturate at some fixed gate voltage. N-type conduction in current annealed graphene layers is caused by the charge trapping in oxide layer during current annealing and recovery of charge neutrality point with time span is understood due to the de-trapping of charge with time. [ABSTRACT FROM AUTHOR]

A Monte Carlo model based on the signal-dependent charge sharing mechanism during charge collection has been developed to explain the nonlinearity of the photon transfer curve (PTC) in image sensors. The model is based on tracing of individual electrons generated by Poisson-distributed photons and describes the PTC nonlinearity as a process with sub-Poisson variance, with an excellent qualitative agreement with the experimental data. A new PTC curve fitting formula is proposed, considering this nonlinearity. The new formula is an excellent fit to the data, does not require selection of linear section of data points and allows more robust calculation of the system conversion gain. [ABSTRACT FROM PUBLISHER]

Highlights: [•] Faraday Cup principle based charge measurement method. [•] Novel method of measuring charge on a flat substrate. [•] Reduction of charge sharing through grounded shield cup across each conductive cup. [ABSTRACT FROM AUTHOR]

The spectroscopic performance of photon counting detectors is limited by the effects of charge sharing between neighboring pixels and the emission of characteristic X-rays. For these reasons, an event can be either missed or counted more than once. These effects become more and more of a concern when pixel pitches are reduced, and for the technology available so far, this meant that there would always be a trade-off between a high spatial and a high spectral resolution. In this work, we present first measurements obtained with the new Medipix3RX ASIC, which features a network of charge summing circuits establishing a communication between pixels which helps to mitigate these effects. Combined with cadmium telluride sensors, we show that this new technology is successful at improving a detector’s spectroscopic capabilities even at pixel pitches as small as 55~\mu\m. At this pitch, we measure an energy response function similar to that observed for a pixel pitch of 165~\mu\m in the absence of a charge summing circuitry. This amounts to an effective reduction of the pixel area by at least one order of magnitude at a comparable energy response. Additionally, we present synchrotron measurements at high X-ray fluxes, where significant pulse pile-up occurs, and provide first experimental evidence for a net benefit when balancing spectroscopic performance and high flux tolerance in charge summing mode. [ABSTRACT FROM PUBLISHER]

Heavy-ion experimental results from flip-flops in 180-nm to 28-nm bulk technologies are used to quantify single-event upset trends. The results show that as technologies scale, D flip-flop single-event upset cross sections decrease while redundant storage node flip-flops cross sections may stay the same or increase depending on the layout spacing of storage nodes. As technology feature sizes become smaller, D flip-flop single-event upset cross sections approach redundant storage node hardened flip-flops cross sections for particles with high linear energy transfer values. Experimental results show that redundant storage node designs provide > 100X improvement in single-event upset cross section over DFF for ion linear energy transfer values below 10~\MeV-cm^2/\mg down to 28-nm feature sizes. [ABSTRACT FROM PUBLISHER]

This paper presents a SET predictive methodology based on coupled MUSCA SEP3 and electrical simulations (CADENCE tool). The method is validated by SET measurements on an inverters chain based on 65-nm bulk CMOS technology, and two designs were considered (respectively for same-well and separate-well designs). These methodologies have been validated in the case of 1000 inverters chain and for heavy ions and demonstrate the impact of the quenching effect. Furthermore, both the designs were considered and the analyses are consistent with experiments and this allows for identification of the quenching effect as the main mechanism responsible for the difference in SET sensitivity. However, the modeling approach can be also used for other logical cells or/and complex radiation environments, to determine SET cross sections, SET cartographies and SET characteristics. This method is applied to SEU analyses, i.e., SBU (Single Bit Upset) and MCU (Multiple Cell Upset) for 65-nm bulk SRAM memory and neutron/proton SET modeling. [ABSTRACT FROM PUBLISHER]

Charge collection by multiple junctions is investigated using broadbeam heavy-ion and backside laser current transient measurements. The probability that significant charge is collected by more than one junction is greater for laser-generated events compared to heavy-ion measurements, which is attributed to the larger carrier generation track radius for the laser. With both sources, the probability of collecting charge on multiple junctions saturates at high charge generation levels. Effects caused by the interaction between junctions on the transient current waveforms is determined using position-correlated two-photon absorption laser analysis. The total charge collected for ion strikes between four adjacent junctions is shown to be approximately the same as for a direct strikes on a single junction, even though the incident ion does not pass through the depletion region of a biased junction. [ABSTRACT FROM PUBLISHER]