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Lead-free potassium titanium halide (K2TiI6) perovskite is considered a substantial alternative for highly efficient perovskite solar cells. This research consists of a computational study of Pb-free K2TiI6-based perovskite solar cell using SCAPS 1D. Primarily, the TiO2 and PEDOT:PSS are considered as ETL and HTL exhibit a device efficiency of 5.70%. Further, the impact of various ETL and HTL is explored. The optimization is mainly focused on considering its built-in potential relation with the open circuit voltage and its device efficiency. It is obtained from the numerical simulation, that to circumvent the VOC loss, the CB minimum of the PVSK(CBmin_PVSK) layer should be higher than the CB minimum of the ETL (CBmin_ETL), and the CB minimum of the ETL (CBmin_ETL) should either align or lie above than the FTO contact. In order to have proper hole transport from the perovskite, the VB maximum of the perovskite (PVSK) layer should be lower than the VB maximum of HTL and should either align or lie below the back contact. It is obtained from the simulation that the optimized ETL and HTLs are found as PCBM and Sr2Cu2O2 improve the device efficiency. Further, the impact of perovskite thickness is also investigated, which enhances the device efficiency up to 23.75%. The proposed structure shows remarkable PV parameters VOC = 1.32 V, JSC = 22.30 mA/cm2, FF = 81.07%, and ƞ = 24.01% which indicates that the K2TiI6-based perovskite solar cell is considered a remarkable candidate for Pb-free perovskite solar cell development. [ABSTRACT FROM AUTHOR]

Introduction: Though, having right set of behavioural skills is always been a priority of all organizations, nevertheless, today's organizations are investing too much on behavioural skill training to safeguard their brand value, bring-up the work culture, maintaining reputation, etc. Behavioural skills plays a vital role in personal development and well-being at student level also. This paper identifies and analyzes the fourteen behavioural skills which are vital in the personal and professional excellence development of a student. Methods: Exhaustive literature review is done and expert opinions are taken to determine the behavioural skills. Interpretive Structural Modelling is performed to analyze and prioritize these skills into strategic, operational and performance outcomes. Results: Behavioral skills are not only depicted in ones' actions but also determines thought process and attitude of a person. Result of this research shows that time management, emotional intelligence, self-development, resilience, multitasking, and open mindedness of an individual are the key behavioural skills that trigger most behaviours and eventually influences the effectiveness of management of personal and professional life. Discussion: Every job requires specific skills to perform. There are certain skills that must be possessed by every student irrespective of the discipline. It include behavioural skills like human values, resilience, multitasking, communication, etc. Research on behavioral skills and its importance are available in literature. However, the literature is lacking in explaining the interplay of these skills in driving personal and professional journey of an individual. Such skills may not be mentioned in the recruitment advertisements but are vital to perform well. [ABSTRACT FROM AUTHOR]

Purpose: The purpose of this study is to explore and examine the determinants of artificial intelligence (AI) adoption by human resource management (HRM). Further, the impact of AI adoption by HR department on their effectiveness has also been tested. Design/methodology/approach: A model explaining the antecedents of AI adoption by HRM is proposed in this study. The proposed model is based on task–organization–environment and task–technology fit models. A two-step partial least square-based structural equational modelling (PLS-SEM) has been used for testing the model. Data was collected from 210 HRM employees (only senior level or specialized HR positions), working in IT firms located in Delhi-NCR region. Findings: Literature review shows that among others, organizational preparedness, perceived benefits and technology readiness determine AI adoption which in turn can make HR system more effective. Results of PLS-SEM support all hypothesized relationships and validate the proposed model. Originality/value: Considering paucity of research on antecedents of AI adoption by human resource department, this study adds significantly to the body of knowledge. Additionally, based on the findings of statistical analysis, certain AI-related recommendations are given to HRM. [ABSTRACT FROM AUTHOR]

In this article, a transient-enhanced fully synthesizable digital low dropout regulator (FS-DLDO) is proposed for ultra-low-power applications. The FS-DLDO uses a fully synthesizable comparator (FS-Com) to sense load variations. A digital logic controller (D-CTRL) tunes the output voltage (VO) through a quad-loop architecture. The quad-loop architecture uses short bidirectional shift registers (BSR) to achieve fast-transient response and reduce leakage current. In addition, the FS-DLDO supports freeze-mode to regulate a ripple-free VO and minimize power consumption at a steady state. To demonstrate this entire design using standard-cells, the P-MOSFET array (PTA) used in traditional digital low dropout regulator (DLDO) is replaced with an array of three-state buffers (TSA). The layout is created using digital design flow in TSMC CMOS 45 nm process, which occupies a 6708 µm2 area. For a power supply (VSUP) range of 0.5–1 V, the FS-DLDO can provide regulated VO with a 50 mV dropout voltage. At VSUP = 500 mV and clock frequency (fCLK) of 10 MHz, the proposed regulator achieves a transient response time of 0.91 µs. This prototype achieves a peak current efficiency of 99.90% and produces a ripple-free VO at a steady state. [ABSTRACT FROM AUTHOR]

The adoption of Industry 4.0 (I4.0) is expected to grow exponentially, especially as it offers efficient and cost-reducing options in an increasingly competitive business environment. The emergent business environment is facing increasing scrutiny and new regulations pertaining to sustainability. Hence, manufacturing in I4.0 is expected to contribute significantly to upping the sustainability quotient of businesses. The Sustainable Development Goals (SDGs) based regime, articulated by the United Nations, provides directions for assessing business performance on the sustainability yardstick. It is therefore imperative to understand and delineate the implications of I4.0 in the attainment of specific SDGs. The current research explores extant literature on this theme along with interaction with expert focus groups, composed of practitioners and researchers. An Interpretive Structural Modelling (ISM) approach has been used to identify eight key SDGs relevant and applicable to manufacturing. Analytic Hierarchy Process (AHP), was applied thereafter, using the Super-Decisions software to understand the relationships between the I4.0 technologies (I4.0T) and the SDGs. The final synthesized outcome from AHP prioritized eight I4.0 building blocks. Digitalization of processes and systems; additive manufacturing; big data analytics; cloud computing and artificial intelligence; and machine language were identified as the top five drivers facilitating sustainable manufacturing. Together they account for 80 percent of the sustainability effort in manufacturing. The study proposes a metric called the Technology Driven Sustainability Index (TDSI) for measuring and tracking the progress of the impact of I4.0 on sustainability in the organization's I4.0 transformation journey. [ABSTRACT FROM AUTHOR]

This computational study investigated a lead (Pb)-free ethyl ammonium (EA) substituted ethylenediamine (EDA) based ((FA 0.9 EA 0.1) 0.98 EDA 0.01 SnI 3) perovskite solar cell (PSC) using the solar cell capacitance one-dimensional simulator (SCAPS 1D). The initial device schematic comprised ((FA 0.9 EA 0.1) 0.98 EDA 0.01 SnI 3) based perovskite as an absorber layer with copper (I) oxide (Cu 2 O) and [6,6] phenyl-C61 butyric acid methyl ester (PCBM) as hole and electron transport layers, where the device efficiency was 21.87%. The impacts of numerous electron transport layers (ETLs) and hole transport layers (HTLs) were also examined. The charge transport layers were optimized based on their energy levels and according to the relationship between the built-in potential (V bi) and the open-circuit voltage (V OC). Numerical simulations showed that to circumvent the V bi loss, the valence band (VB) maximum of HTL (E VB_HTL) should not be lower than the VB for perovskite (PVK) (E VB_PVK) for the appropriate selection of HTLs. Correspondingly, for the suitable selection of ETLs, the conduction band (CB) minimum of ETL (E CB_ETL) and the front contact should not be greater than the CB minimum for PVK (E CB_PVK). Therefore, the optimized ETLs and HTLs were obtained as zinc oxysulfide and copper (II) phthalocyanine, respectively, where the device's efficiency increased up to 22.36%. The effect of the thickness of the EDA-based PSCs was also examined and the optimized thickness was obtained as 1.1 μm, where the device's efficiency increased to 24.42%. This improvement in the performance of the device indicates that EA substituted EDA-based ((FA 0.9 EA 0.1) 0.98 EDA 0.01 SnI 3) PSC is a promising alternative for use in Pb-free PSCs. • The simulation of the lead-free ethylenediamine based ((FA 0.9 EA 0.1) 0.98 EDA 0.01 SnI 3) perovskite solar cell is performed. • The charge transport layers are optimized co-relating the built-in potential and the open circuit voltage. • The band alignment between ETL/perovskite & perovskite/HTL depicts a significant impact on the device performance. • The CuPc and ZnOS as a hole and electron transport layer elevate the device efficiency up to 22.36 %. • At the optimized thickness of the perovskite layer, the device efficiency improves up to 24.42%. [ABSTRACT FROM AUTHOR]

This paper presents a novel jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is helpful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL) and time-based circuits whose performance is severely degraded by high jitter. In the proposed technique, the jitter is extracted using Excess Phase Discrimination (EPD) block and is transformed into Pulse Width Modulated (PWM) signal, which is then fed into the Phase Compensator (PC) block. This block reduces the jitter by about half its value after enabling the Single Ended Injection Locking (SEIL). The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. On enabling the proposed circuit, the Root Mean Square (RMS) jitter reduces from 5.94 to 2.58 ps (about 56%) for VCRO running at 58 MHz and consumes a total power of 375.84 μ W. The overall performance of the proposed circuit does not vary much in the post-layout simulations, hence demonstrating the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

• All- perovskite lead –free tandem solar cell is simulated with efficiency 26.73%. • CH 3 NH 3 GeI 3 & FAMASnGeI 3 perovskite layers have been used. • Different elctron transport layers have been studied. • The impact of defect density and front electrode work function is also studied. The numerical simulation of lead-free all-perovskite tandem solar cell using solar capacitance one dimensional tool (SCAPS 1D) has been performed. The combination of methyl ammonium germanium halide (CH 3 NH 3 GeI 3) as wide band-gap (1.9 eV) perovskite layer and FA 0.75 MA 0.25 Sn 0.25 Ge 0.5 I 3 (FAMASnGeI 3) as a low band-gap (1.4 eV) perovskite layer is considered for the first time which shows the optimal device efficiency of 26.72%. The present work studies the effect of the different electron transport layer, perovskite absorber thickness and its defect density on photovoltaic performance. Further, the effect of front electrode work function on the device photovoltaic performance is also studied. It has been observed that the device open circuit voltage (Vo C) is significantly affected by the built-in voltage (V bi) across the perovskite layer. In addition, the effect of thickness of the perovskite absorber layers is also investigated. Moreover, the effect of defect density of the absorber layer is also explored, and it has been found that for better device performance the defect density needs to be as low as possible. Furthermore, it has been observed that the work function of the front contact plays a significant role and for the proposed device its value should not be more than 4.4 eV. The proposed all–perovskite tandem solar cell shows the remarkable photovoltaic parameters i.e., open circuit voltage (V OC) = 1.07 Volts, short circuit current density (J SC) = 28.36 mA/cm2, fill factor (FF) = 84.39% and efficiency (η) = 26.72%. [ABSTRACT FROM AUTHOR]

Electrocardiogram (ECG) signal processing and analysis is becoming more and more popular as it is useful in diagnosis and prognosis of human heart and clinically automatic machine estimation is based upon it. R-peak is the most important component in ECG beat and is widely used to investigate normal and abnormal subjects (patients). From the last few decades, R-peak detection in ECG has been the most challenging topic in the biomedical research. As QRS complex has high frequency in ECG as compared to other waves (P, T, U-wave), so majority of algorithms estimate QRS complex by either filtering or suppressing the lower frequency waves, including various artifacts like baseline wander, power line interference, and electromyograph noises. This paper demonstrates a new kind of ECG denoising algorithm based on self-convolution window (SCW) concept. The SCW based on Hamming window, herein referred to as Hamming self-convolution window, is used to design a new kind of filter which possesses negligible ripples in the stop band, as compared to the conventional window-based filters. This algorithm is validated on MIT-BIH arrhythmia database and the results outperform in terms of sensitivity, positive predictivity, and error rate obtained as 99.93%, 99.95%, and 0.117%, respectively, as compared to the other well-established works. The approach has also outperformed the results of well-established window-based filters (Hamming and Kaiser) in terms of reduced false negative, false positive, and error rate. [ABSTRACT FROM AUTHOR]

This paper presents an artificially intelligent Flash ADC with enhanced resolution from 4 to 10 bits. Unlike conventional approaches, this artificial intelligence (AI)‐based architecture avoids the use of many number of comparators in the Flash ADC when the ADC's resolution changes from 4 to 10 bits. This work initially gets the digital output of a 4‐bit existing Flash ADC as a training data set and then uses these 4‐bit output bits and sends to resolution enhancement logic (REL) block to vary its resolution without increasing the hardware complexities. After simulation, it is observed that the proposed ADC is of SNR of 24.13 dB for 4‐bit Flash ADC designed in SCL 180 nm CMOS technology and increases from 36.89 to 60.70 dB for 6 to 10‐bit resolution, respectively. The sampling frequency of the proposed architecture ranges from 3.6 to 1.04 GHz for a change in resolution from 4 to 10 bits. The FoM of 235 fJ/conv‐step in the training phase is obtained, and it varies from 56 to 20.3 fJ/conv‐step in the next phase of the testing and the prediction. The estimated area of the proposed 4‐to‐10‐bit variable resolution Flash ADC is 235.23×301.67$$ 235.23\times 301.67 $$ μm2. [ABSTRACT FROM AUTHOR]

A power and area efficient metal-oxide semiconductor field-effect transistor (MOSFET)-only 1.5-bit fully differential pipelined analog-to-digital converter (ADC) stage is proposed and designed in TSMC 0.18 μm digital CMOS technology with supply voltage of 1.8 V. It is based on charge pump based technique to achieve the stage voltage gain of 2. Various capacitances are implemented by MOSCAPs (capacitance offered by the MOSFET), offering compatibility with cheaper digital complimentary metal-oxide semiconductor (CMOS) process in order to reduce the much required manufacturing cost. The proposed stage suffers from only linear gain error with full signal swing of 2 V peak-to-peak (p–p) differential. Using the proposed stage, un-calibrated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) for 10-bit, 100 MS/s pipelined ADC are 40.11 and 40.86 dB, respectively, which can be further increased by using a simple digital calibration technique. Comparison between the proposed stage and conventional operational amplifier based stage shows insensitivity towards capacitor mismatch along with power savings and design simplicity. [ABSTRACT FROM AUTHOR]

In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/–0.4 LSB and INL improves from +9.3/–9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power. [ABSTRACT FROM PUBLISHER]

A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost. [ABSTRACT FROM PUBLISHER]

Cryogenic two-phase flow with phase change heat transfer, consisting of a saturated liquid slug translating in its own superheated vapor in a circular pipe, was numerically simulated. The cryogenic chill down process was simplified by assuming ideal inverted annular flow regime. The method used is based on a sharp interface concept and developed on an Eulerian Cartesian fixed-grid with a cut-cell scheme and marker points to track the moving interface. The unsteady, axisymmetric Navier-Stokes equations in both liquid and vapor phases are solved separately and used to compute the velocity, pressure, and temperature fields and the deformation of the liquid core very accurately. Three most common cryogenic fluids, viz. nitrogen, oxygen, and argon were included in the study. The influence of non-dimensional parameters like Reynolds number $$Re,$$ Weber number $$We$$ , and Jakob number $$Ja$$ on flow characteristics was studied by systematically varying only one at a time. $$Re$$ was found to affect the mass flow rates, but did not have a significant influence on the wall cooling or the Nusselt number. $$We$$ affected the interface shape at the leading edge of the liquid slug, also influencing the heat transfer and velocity field there. $$Ja$$ affects all three quantities of interest, i.e., mass flow rate, wall cooling, and the Nusselt number. [ABSTRACT FROM AUTHOR]

The present study investigates the effect of band offsets engineering for lead–free (Pb-free) all-inorganic double-perovskite solar cell (DPSC) using the solar cell capacitance simulator one dimensional (SCAPS 1D). The initial simulation study is carried out by using Cs 2 AgBi 0.75 Sb 0.25 Br 6 based double-perovskite layer along with 2,2′,7,7′-tetrakis[N,N-di4-methoxyphenylamino]-9,9′-spirobifluorene (SpiroOMeTAD) as a hole transport layer (HTL) and zinc oxide (ZnO) as an electron transport layer (ETL) which shows the device efficiency of 11.35%. Further, the impact of the conduction band offset (CBO) and valence band offset (VBO) is studied to improve the device performance. The proposed study suggests that extremely negative and positive CBO resulted in limited PV performance. This is mainly due to the reason that in extremely negative CBO limits the V bi and thus V OC. However, the extreme positive CBO leads to the formation of a barrier spike which restricts the device performance. Similarly, the positive VBO leads to band misalignment which further deteriorates the device performance. Hence, it has been revealed from the numerical simulation, that the optimum conduction band offset (CBO) is found to be −0.1 eV to +0.1 eV and the optimum valence band offset (VBO) is found to be −0.1 eV–0.00 eV with respect to the double-perovskite absorber layer. It has been found that with the introduction of copper (I) thiocyanate (CuSCN) as a hole transport layer (HTL) and zinc oxysulfide (ZnOS) as an ETL the overall power conversion efficiency (PCE) improves up to 18.26% which is an outstanding improvement in the lead-free double–perovskite solar cell. In addition, the effect of the thickness of the perovskite layer is also studied in which the optimized double-perovskite layer thickness obtained is 400 nm. Thus, the proposed simulation study provides significant insight for the researchers that will help to find out the suitable ETL and HTL for Pb-free DPSC. • Band offset engineering is analyzed to improve the performance of double–perovskite solar cells. • The range of optimum CBO and VBO is obtained is −0.1eV–0.1eV and −0.1 eV–0.00 eV respectively. • The effect of thickness of the Pb-free double-perovskite layer on the photovoltaic performance is also investigated. • The final device efficiency of double–perovskite solar cell reaches up to 18.26%. [ABSTRACT FROM AUTHOR]

This article presents a fully-synthesizable digital voltage regulator for applications with extremely low power consumption. The proposed design uses a synthesizable controller (DLDOC) to detect load fluctuations and control a tri-loop structural design. This tri-loop structure minimizes the ripples on output voltage (V OUT) and provides a fast-transient response (TR). This structure decreases the length of bi-directional shift register (Bi-SR) which reduces the overall power consumption. A quivering control is introduced to minimize the V OUT oscillations in steady-state. To demonstrate this design using CMOS standard-cells, a fully-synthesizable comparator (FS-comp) is utilized. A tri-state buffer array (TBA) is employed instead of conventional PMOS switch array to make this design fully-synthesizable. A pattern detection mechanism is used to switch between different loops. The proposed prototype occupies 6394 µm2 area in 45 nm CMOS technology. This design is implemented using conventional synthesis and place-and-route (P & R). For a supply voltage (VDD) of 0.5–1 V, a regulated V OUT is attained with a dropout voltage of 50 mV. At 10 MHz clock frequency, the proposed LDO achieves a quiescent current (I Q) and fast-TR of 2.2 µA and 300 ns, respectively. A maximum current efficiency (C.E.) of 99.98% is attained with output ripples < 1 mV. [ABSTRACT FROM AUTHOR]

Abstract: An accurate finite-volume based numerical method for the simulation of an isothermal two-phase flow, consisting of a rising deformable bubble translating in a quiescent, unbounded liquid, is presented. This direct simulation method is built on a sharp interface concept and developed on an Eulerian, Cartesian fixed-grid with a cut-cell scheme and marker points to track the moving interface. The unsteady Navier–Stokes equations in both liquid and gas phases are solved separately. The mass continuity and momentum flux conditions are explicitly matched at the true surface phase boundary to determine the evolving interface shape and movement of the bubble. The highlights of this method are that it utilizes a combined Eulerian–Lagrangian approach, and is capable of treating the interface as a sharp discontinuity. A fixed underlying grid is used to represent the control volume. The interface, however, is denoted by a separate set of marker particles which move along with the interface. A quadratic curve fitting algorithm with marker points is used to yield smooth and accurate information of the interface curvatures. This numerical scheme can handle a wide range of density and viscosity ratios. The bubble is assumed to be spherical and at rest initially, but deforms as it rises through the liquid pool due to buoyancy. Additionally, the flow is assumed to be axisymmetric and incompressible. The bubble deformation and dynamic motion are characterized by the Reynolds number, the Weber number, the density ratio and the viscosity ratio. The effects of these parameters on the translational bubble dynamics and shape are given and the physical mechanisms are explained and discussed. Results for the shape, velocity profile and various forces acting on the bubble are presented here as a function of time until the bubble reaches terminal velocity. The range of Reynolds numbers investigated is 1< Re <100, and that of Weber number is 1< We <10. [Copyright &y& Elsevier]

The paper demonstrates an efficient process flow for the Hardware Testing of an ASIC (Application Specific Integrated Circuit). The procedure is implied on Comparator, ADC (Analog-to-Digital) and Present Cipher Crypto ASIC. This involves the testing functionality of an Analog, Digital and Mixed Signal design ASIC. The results obtained during functional testing are verified through simulations on Cadence, in case of comparator and ADC ASIC, and vivado in case of Crypto ASIC. The method gives high accuracy and requires less power even at high frequency. [ABSTRACT FROM AUTHOR]

This work presents a PVT robust machine learning-based Voltage-controlled Oscillator (VCO) with an enhanced linearity range. The machine learning algorithm with PVT robustness is implemented digitally. Different from conventional methods, the proposed scheme does not require the VCO to be in working mode every time one needs the prediction of frequency. The proposed scheme uses the frequency to digital converter (FDC) output data as an input learning vector and uses a prediction block to predict the future frequencies. An 11-stage voltage-controlled oscillator with a machine learning algorithm is implemented in SCL 180 nm CMOS technology. The measurement results show that the proposed architecture is robust against PVT variations with an enhanced linearity range. Without a machine learning algorithm, the VCO's control voltage linearity range is 0.28 V to 0.40 V that increases to the range from 0.1 to 1.8 V after applying the proposed machine learning algorithm. The maximum gain variation of 3.71% is observed at FF with respect to the TT corner after applying the proposed machine learning algorithm. [ABSTRACT FROM AUTHOR]

A dual‐loop ADPLL architecture with 3‐bit flash TDC and background calibration‐based VCO is presented in this paper. The major aim of this work is to achieve the low jitter, low power, fast locking, and PVT‐insensitive ADPLL using simple flash TDC and gain calibrated VCO. A simple flash‐based 3‐bit TDC in the main loop is used which helps in achieving the fast locking with lower power consumption in ADPLL. The novel low phase noise VCO, with gain calibration in another loop, is used to fasten the locking process and jitter reduction due to any PVT variations. Therefore, both flash TDC and dual loop in the proposed ADPLL architecture help in achieving the fast locking. Proposed ADPLL is designed in SCL 180 nm CMOS technology at 1.8 V. The resolution of 3‐bit flash TDC is 3 ps. The achieved jitter of ADPLL is 1.83 ps with a phase noise of −153 dBc/Hz and locking time of 1.7 μs. Total power consumption is 5.3 mW at a frequency of 1.6 GHz. [ABSTRACT FROM AUTHOR]

This article presents the numerical simulation of lead–free (Pb-free) double–perovskite (Cs 2 AgBi 0.75 Sb 0.25 Br 6 , i.e., mixed antimony bismuth halide double-perovskite) solar cell (DPSC) using solar cell capacitance one dimensional simulator (SCAPS-1D). In this contribution, the hole transport layers (HTLs) and electron transport layers (ETLs) are optimized. The optimization is performed by correlating the open circuit voltage (V OC) with the built-in potential (V bi). It is disclosed from the simulation results, that higher V bi resulted higher V OC. Furthermore, it is also found that, for the proper selection of HTL, the E V_HTL (Valence band maximum of HTL) and φ BC (Work function of back contact) should not be much deeper than the E V_PVK (Valence band maximum of double–perovskite layer) to avoid V bi loss. Correspondingly, for proper selection of ETL, E C_ETL (Conduction band minimum of electron transport layer) and Φ FC (Work function of front contact), should not be much higher than E C_PVK to prevent V bi loss. The optimized HTL and ETL are found to be Cu 2 O (copper(I) oxide) and ZnOS (Zinc oxysulfide) respectively. Moreover, the device photovoltaic performance is further improved by optimizing the double-perovskite layer thickness which is found to be 400 nm. Under optimized condition, the device photovoltaic power conversion efficiency (η) improves to 18.18%. The optimized device photovoltaic performance are found to be, open –circuit voltage (Voc) = 1.39 V, short-circuit current density (J SC) = 16.04 mA/cm2, and fill factor (FF) = 78.34% which indicates that double–perovskite absorber layer (Cs 2 AgBi 0.75 Sb 0.25 Br 6) is a suitable candidate for the development of highly efficient Pb-free DPSC. • The numerical simulation of lead-free double–perovskite is performed with-optimized device efficiency of 18.18%. • The electron transport layer and hole transport layer is optimized by co-orelating V OC with V bi. • The simulation study reveals that V OC is strongly dependent on V bi of lead-free double –perovskite absorber layer. • The optimized ETL and HTL found to be ZnOS and Cu 2 O respectively. [ABSTRACT FROM AUTHOR]

The numerical simulation of lead-free perovskite cesium tin germanium halide (CsSnGeI 3) and methyl ammonium germanium halide (CH 3 NH 3 GeI 3) solar cells have been performed. It has been elucidated from the numerical simulation that as compare to the CH 3 NH 3 GeI 3 based structure, CsSnGeI 3 based structure depicts better photovoltaic performance under constant illumination condition. To enhance the device photovoltaic performance, the effects of different hole transport layer (HTL), defect density of the absorber layer, metal work function and the effect of temperature has been studied. In the present investigation, the effect of hole transport layers are analyzed by correlating the built-in voltage (V bi) with the open circuit voltage (V OC). It has been obtained from the simulation results, that V bi has a significant impact on V OC as the higher V bi corresponds to the highest V OC. Moreover, the effect of defect density and metal work function is also studied. It is obtained from the simulation results, that the optimum defect density is found to be 1 × 1014 cm−3 and metal work function should be greater than or equal to 5 eV for both lead-free CH 3 NH 3 GeI 3 and CsSnGeI 3 based perovskite layer. Furthermore, to suggest possible lead-free alternatives for all-perovskite two-terminal multi-junction solar cell, an attempt is made to match the current of bottom perovskite layer i.e., CsSnGeI 3 based perovskite layer to the top perovskite layer i.e., CH 3 NH 3 GeI 3 based perovskite layer. To attain the current matching for bottom perovskite layer (CsSnGeI 3 based perovskite layer) to top perovskite layer (CH 3 NH 3 GeI 3 based perovskite layer), the bottom perovskite sub cell is fed with the filtered spectrum which is obtained by transmission from top electrode. After, the realization of current matching the short circuit current density of CsSnGeI 3 based perovskite layer drops from 25.75 mA/cm2 to 15.32 mA/cm2 which is similar to CH 3 NH 3 GeI 3 based perovskite absorber layer. In addition, it has been obtained from literature, that both the perovskite layers can be fabricated using solution–processing low-temperature technology. Hence, the numerical study suggests the possible alternatives for wide and narrow bandgap perovskite layers for the application to obtain highly efficient lead-free all-perovskite multi-junction solar cells. • The numerical simulation of lead-free wide and narrow bandgap CH 3 NH 3 GeI 3 and CsSnGeI 3 perovskite layers is performed. • The effect of different hole transport layers is realized by correlating V bi with the V OC. • Cu 2 O as an HTL shows highest V bi and hence shows better photovoltaic performance. • The study of defect density, metal work function and temperature are explored for lead-free perovskite layers. • The lead-free perovskite layers proves to be the promising candidate for all-perovskite multi-junction solar cell. [ABSTRACT FROM AUTHOR]

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180 nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1 V to 1.8 V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8 V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55 mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is 1 5 0 μ W @ 1 V and 3 1 2 μ W @ 1. 8 V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much. [ABSTRACT FROM AUTHOR]

In this work, a dual loop all-digital phase locked loop (ADPLL) is designed to obtain a fast locking, low power and low jitter for SoC and battery-operated applications. The high speed and high-resolution 4-bit flash time to digital converter (TDC) is also proposed to achieve low jitter and fast locking in ADPLL. The flash TDC uses a foreground calibration to make the ADPLL work robustly over PVT variations. In present work, fasting settling time of 1 μs and low power is achieved for proposed ADPLL owing to flash-based TDC and dual loop architecture. The proposed 4-bit flash TDC achieves a resolution of 6 ps. A low-phase noise voltage-controlled oscillator based on inverters is designed to obtain a reduced jitter in ADPLL. The ADPLL is implemented in a 180-nm SCL digital CMOS technology. The achieved phase noise of proposed ADPLL is − 128.2 dBc/Hz at an offset of 100 MHz. At an output frequency of 1.6 GHz, the periodic jitter of ADPLL is 7.8 ps, and power consumption is 6.5 mW. [ABSTRACT FROM AUTHOR]

A voltage supply scalable analog voltage comparator for a wide input range is presented in this paper. A digital gate-based methodology is used to design the comparator in order to extend the use of automation in the analog designs. Therefore, the proposed comparator is enormously cost-effective, reduces the time-to-market, scalable to newer technologies, and more immune to process variations than the conventional CMOS analog voltage comparators. The comparator is designed using Semi-Conductor Laboratory (SCL) 180 nm digital CMOS technology at a supply voltage of 1.8 V. The power consumption of the proposed comparator is 160 µW approximately with total delay and offset voltage of 1.63 ns and 4.28 mV, respectively. Also, 4-bit and 5-bit flash ADC is designed as an application. The measured values of DNL/INL are ± 0.4/± 0.4 LSB and 0.42/± 0.6 LSB for 4-bit and 5-bit, respectively. [ABSTRACT FROM AUTHOR]

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6 GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18- μ m CMOS technology with supply voltage of 1.8 V. The output clocks with cycle-to-cycle jitter of 2.13 ps at 1.6 GHz. The phase noise of VCO is − 137 dBc/Hz at an offset of 100 MHz and total power consumed by the proposed PLL is 2.63 mW at 1.6 GHz. [ABSTRACT FROM AUTHOR]

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6 GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180 nm CMOS process with supply voltage of 1.8 V. The phase noise of VCO is − 1 3 7 dBc/Hz at an offset frequency of 100 MHz. The reference clock of 25 MHz synthesizes the output clock of 1.6 GHz with rms jitter of 0.642 ps. [ABSTRACT FROM AUTHOR]

A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is presented in this paper. This circuit has an advantage of digital circuit concept and can be easily migrated to lower technologies. Also, the digital circuits are less sensitive to the noise and device mismatches can be synthesized and auto place and route (P&R) using EDA tools. The design of the proposed comparator is based on the standard cells implementation. As the proof of concept this comparator is implemented on Xilinx Basys-3 Artix-7 FPGA kit. The prototype of complete 4-bit Flash ADC is designed in 180 nm CMOS technology with 1.8 V supply voltage. The measured values of ENOB, SNDR, SNR and SFDR are 3.6, 23.43 dB, 25.2 dB and 30.1 dB, respectively at 33.20 MHz input frequency and 200 MHz clock frequency. The total power consumed by the 4-bit flash ADC is 2.14 mW. The calculated value of DNL and INL is < 0. 4 LSB and < 0. 5 LSB respectively. [ABSTRACT FROM AUTHOR]

Clinically, electrocardiogram (ECG) is a powerful tool for determining the health and functioning of the human heart. Faster detection and diagnosis of heart functioning would aid cardiologists to provide appropriate treatment to the patients (subjects). In this paper, the concept of fractional-order calculus is employed for noise cancellation and artifacts removal in ECG signal as fractional-order differentiator proved to provide more peculiar details about signals than an integer-order differentiator. In the proposed method, R-peaks are detected using Riesz fractional-order digital differentiator (RFODD) based on the differencing method. The differentiation operation enhances the high-frequency components of the signal. So, QRS complex which is a high-frequency component in ECG is accentuated and the R-peaks are detected using appropriate threshold technique. The proposed method is tested on Massachusetts Institute of Technology-Beth Israel Hospital (MIT-BIH) arrhythmia database, and the experimental results of the proposed method have achieved a sensitivity of 99.95%, positive predictivity of 99.949% and an error rate of 0.095%. ECG waveforms are analyzed on various fractional orders of RFODD, and their performance parameters, i.e., sensitivity, positive predictivity and error rate, are also calculated. [ABSTRACT FROM AUTHOR]

This paper presents variable resolution SAR ADC with digitally implemented Bit enhancement logic. Unlike conventional approaches, this work avoids complex hardware architecture to reduce power consumption as the variable resolution is achieved using digitally implemented VRL (Variable Resolution Logic) block instead of combining different ADC configurations altogether. The proposed architecture utilizes the VRL block to enhance the resolution. This work first uses the linear range of an 8-bit SAR ADC as a learning dataset and then uses corresponding output bits as training data for VRL block. This VRL block further enhances the resolution with the help of a 2-bit voltage-to-digital converter by self-adjusting the required resolution after estimating the error. Less variation in sampling rate from 250 MHz to 175 MHz is achieved after implementing the VRL block. The proposed architecture is designed in 180 nm CMOS technology to validate the work. The simulation results show the ADC achieves an SNDR of 47.4 dB for 8-bit and increases to 72.11 dB for 12-bit resolution. The FoM of 253 fJ/conversion step for 8-bit SAR ADC is achieved, and it ranges from 168.3 to 35.7 fJ/conversion step in Variable resolution block phase. The area of the proposed ADC is 315.86 × 151.30 µm2. [ABSTRACT FROM AUTHOR]

Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence Virtuoso Analog Design Environment using UMC 180nm CMOS technology at 1.8V supply. [ABSTRACT FROM AUTHOR]

In the present work, a methodology has been proposed to design analog/mixed-signal circuits using digital-in-concept circuits in digital technology. This paper presents a digital standard cell-based, scalable, highly synthesizable analog voltage comparator designed in 180 nm CMOS technology at the supply voltage of 1.8 V. The digital design requires less design effort and is highly immune to process, voltage and temperature variations. The proposed comparator has been designed and simulated in the Cadence virtuoso analog design environment. It is observed from the simulation results that the total power dissipation and propagation delay is 143.2 μW and 1.07 ns, respectively. The offset voltage of the proposed comparator is 4.98 mV. Also, as a proof-of-concept, the feasibility of the proposed analog voltage comparator is carried out on Artix-7 field-programmable gate array (FPGA) using Xilinx Basys-3 FPGA kit and other off-the-shelf components. The proposed digital-in-concept comparator is suitable for low power and high-speed SoC application with reduced design effort and lesser time-to-market. • A methodology to design analog/mixed signal circuits using digital-in-concept technique in digital technology is proposed. • Digital standard cell-based, highly synthesizable analog voltage comparator has been presented. • The proposed analog comparator has been implemented on Xilinx Basys-3 FPGA using other off-the-shelf components. • The proposed comparator is scalable to lower technologies due to its standard cell-based design methodology. • The proposed design takes less design effort, highly immune to process, voltage and temperature variations. [ABSTRACT FROM AUTHOR]

A high-resolution dynamic voltage comparator with an input signal dependent power down technique for low power applications is presented here. Without affecting the resolution, a preamplifier stage has been removed from the proposed dynamic voltage comparator in order to reduce the power consumption and its delay. In this design, an input signal dependent power-down technique is used. The proposed design consists of NMOS & PMOS Input Stage Dynamic Voltage Comparator with power down (NISDVC_PD & PISDVC_PD) along with multiplexers for full rail-to-rail input swing. One out of PISDVC_PD and NISDVC_PD is active at a time to reduce power consumption. The proposed comparator has been designed using SCL 180 nm CMOS technology at 1.8 V. The simulation results of the proposed design show that the power consumption and delay is 94.1 µW and 208.28 ps at 500 MHz whereas at 2 GHz the value of the power consumption and delay is 147.7 µW and 212.5 ps, respectively. Furthermore, the offset voltage is obtained as 185.3 µV and the sensitivity of the circuit is 0.15 µV. [ABSTRACT FROM AUTHOR]

In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter (TDC) is designed to enhance the jitter and locking time performance. The proposed ADPLL utilizes a low power and high resolution 3-bit flash TDC with foreground calibration to suppress the issues of process, voltage and temperature (PVT) spreads and achieves low jitter and low power ADPLL. To obtain the fast locking, a proposed dynamic bang-bang PFD is used. The proposed ADPLL takes only 5 iterations to achieve the locking from unlocked state. Additionally, ADPLL employs a wide range and low phase noise voltage controlled oscillator (VCO) based on inverters to obtain a reduced jitter in ADPLL. The proposed ADPLL is designed in 180-nm SCL digital CMOS technology at 1.8 V supply. It consumes a total power of 5.94 mW at 1.8 V. From the post layout simulations, the achieved FoM and periodic jitter is −227.6 dB and 1.71 ps respectively at an output frequency of 1.6 GHz. The achieved phase noise of proposed ADPLL is −131.2 dBc/Hz at offset of 100 MHz. [ABSTRACT FROM AUTHOR]