Search

When thickness-dependent carrier mobility is coupled with Thomas-Fermi screening and interlayer resistance effects in two-dimensional (2D) multilayer materials, a conducting channel migrates from the bottom surface to the top surface under electrostatic bias conditions. However, various factors including (i) insufficient carrier density, (ii) atomically thin material thickness, and (iii) numerous oxide traps/defects considerably limit our deep understanding of the carrier transport mechanism in 2D multilayer materials. Herein, we report the restricted conducting channel migration in 2D multilayer ReS2 after a constant voltage stress of gate dielectrics is applied. At a given gate bias condition, a gradual increase in the drain bias enables a sensitive change in the interlayer resistance of ReS2, leading to a modification of the shape of the transconductance curves, and consequently, demonstrates the conducting channel migration along the thickness of ReS2 before the stress. Meanwhile, this distinct conduction feature disappears after stress, indicating the formation of additional oxide trap sites inside the gate dielectrics that degrade the carrier mobility and eventually restrict the channel migration. Our theoretical and experimental study based on the resistor network model and Thomas-Fermi charge screening theory provides further insights into the origins of channel migration and restriction in 2D multilayer devices.

International audience; This work presents the performance and low-frequency noise (LFN) of 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The experimental measurements and the analysis are performed as a function of temperature for the first time, focusing on cryogenic applications, down to 4.2 K. The back bias impact on device performance is evaluated. The results reveal that the threshold voltage tuning is found to be temperature independent, allowing extra drain current improvement. This is particularly interesting for short channel devices, whose drain current gain with temperature lowering is expected to be smaller in comparison with long channel MOSFETs. LFN is characterized by means of time-domain current sampling measurements. Moderate and strong inversion regimes are investigated. The carrier number with correlated mobility fluctuations model can well describe the 1/f noise behavior down to 4.2 K. The physical origin behind the drain current noise-to-signal power augmentation with temperature lowering could be mainly attributed to the normalized transconductance improvement.

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

This study investigates the inter-tier coupling, for a Back-Side Illuminated (BSI) 4-Transistor (4T) pixel with its diode and Transfer Gate on the bottom tier and the rest of its circuitry on the top tier of a 3D Sequential Integration (3DSI) process. Variations due to coupling are compared with variations due to temperature, showing that both effects may result in a readout error of the same order of magnitude for the top-tier readout circuit. Nevertheless, we demonstrate that in a typical rolling readout, the sequence of the pixel control signals makes the coupling effect nearly negligible. As a result, we suggest that the fabrication of an inter-tier ground plane for electrical isolation is not strictly necessary for Monolithic 3D pixels when the readout top tier is directly stacked on the photodiode bottom tier.

International audience; The applicability of the Lambert-W function-based parameter extraction methodology is demonstrated for 28nm FDSOI MOSFETs down to deep cryogenic temperatures (4.2K). The Lambert-W function enables to accurately model the inversion charge and drain current MOSFET characteristics from weak to strong inversion, while using the classical mobility law down to liquid helium temperature. The main MOSFET parameters were extracted versus temperature and gate length, showing the temperature independence of short channel effects and the strong mobility degradation at short channel length due to increased neutral defect scattering.

A comprehensive Kubo-Greenwood modelling of FDSOI MOS devices is carried out down to deep cryogenic temperatures. It is found that a single set of mobility parameters is only needed to fit the device characteristics versus temperature for long channel devices. Instead, in short channels, the neutral scattering mobility component µN is found to decrease at small gate length due to the increased presence of neutral defects close to source/drain ends whatever the temperature.

RF performance and intertier coupling of CMOS processed in 3-D sequential integration are investigated. pMOS transistor fabricated with a 500 °C thermal budget features good RF figures of merit with ${f}_{t} =105$ GHz and ${f}_{\text {max}} =175$ GHz for a gate length of 45 nm and ${V}_{\text {DD}} = -1$ V. Moreover, we demonstrate that the low- ${k}$ SiCO oxide spacer and low polysilicon gate resistance obtained with the low temperature process contribute to ${f}_{\text {max}}$ results that are better than high temperature process (above 1000°). Finally, we illustrate the crosstalk effects and the influence of the low-tier transistor gate voltage ${V}_{\text {G}}$ on the top-tier threshold voltage ${V}_{T}$ . We also show that a polysilicon ground shield integrated under the top-tier transistor substantially attenuates the intertier RF field coupling effects.

In this paper we present an analytical experimental study regarding the extraction and analysis of 28 nm FD-SOI MOSFET parameters, from room temperature down to 25 K, and from micro- to nanometer gate lengths. It is shown that the FD-SOI device behavior with temperature can reliably be described by the already established theory of physics for deep cryogenic conditions: Boltzmann statistics and phonon scattering mechanisms are the two main factors that define the device electrical behavior. Moreover, we also demonstrate the advantage of the Y-function as a parameter extraction method, across different channel lengths, and a wide temperature range. We demonstrate the dependence of threshold voltage, sub-threshold swing, low-field mobility and source-drain series resistance on temperature, and how this may be affected by the gate length decrease.

In this work, a continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs is presented, valid in all regions of operation. Initially, the expressions of the gate, drain and source total charges are analytically derived based on a continuous and symmetric drain current compact model already developed. Then, the intrinsic capacitances are calculated via the differentiation of the terminal charges, verified against TCAD simulation data. The AC symmetry tests of the trans-capacitance compact model are thoroughly investigated.

This article presents a new methodology for the extraction of low-frequency noise (LFN) or random telegraph noise (RTN) parameters, such as the gate oxide interface trap density, ${N}_{\text {t}}$ , and the mobility fluctuations factor, $\Omega $ , without the influence of the source/drain series resistance, ${R}_{\text {sd}}$ . The method utilizes the ${Y}$ -function—which is immune to any first-order degradation, including the series resistance—as well as the intrinsic mobility degradation factors $\theta _{ {1,0}}$ and $\theta _{{2}}$ . The proposed extraction technique is first demonstrated through numerical calculations and then applied on experimental results of n-channel short length FinFETs. It is shown that if the ${R}_{\text {sd}}$ impact is not accounted for, the extracted LFN parameters through the classic carrier number fluctuations (CNF) with correlated mobility fluctuations (CMF) model can lead to significant extraction errors. This mainly concerns the correlated mobility factor $\Omega $ , which may be strongly underestimated, but also the extraction of the trap density ${N}_{\text {t}}$ .

Field effect transistors (FETs) based on networks of randomly oriented Si nanowires (Si nanonets or Si NNs) were biomodified using Thrombin Binding Aptamer (TBA&ndash, 15) probe with the final objective to sense thrombin by electrical detection. In this work, the impact of the biomodification on the electrical properties of the Si NN&ndash, FETs was studied. First, the results that were obtained for the optimization of the (3-Glycidyloxypropyl)trimethoxysilane (GOPS)-based biofunctionalization process by using UV radiation are reported. The biofunctionalized devices were analyzed by atomic force microscopy (AFM) and scanning transmission electron microscopy (STEM), proving that TBA&ndash, 15 probes were properly grafted on the surface of the devices, and by means of epifluorescence microscopy it was possible to demonstrate that the UV-assisted GOPS-based functionalization notably improves the homogeneity of the surface DNA distribution. Later, the electrical characteristics of 80 devices were analyzed before and after the biofunctionalization process, indicating that the results are highly dependent on the experimental protocol. We found that the TBA&ndash, 15 hybridization capacity with its complementary strand is time dependent and that the transfer characteristics of the Si NN&ndash, FETs obtained after the TBA&ndash, 15 probe grafting are also time dependent. These results help to elucidate and define the experimental precautions that must be taken into account to fabricate reproducible devices.

We fabricated junction less and inversion-mode monocrystalline nanowire nMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junction less transistors for analog applications: $A_{VT}=1.4mV \cdot \mu$ m matching, $A_{v0}=62dB$ gain (L=200nm), $f_{T}=126GHz$ cut-off frequency and $f_{MAX}=182GHz$ maximum operating frequency (L=35nm). Junction Less transistor performances even exceed those of inversion-mode ones in terms of back-bias capability, low-frequency noise, hotcarrier degradation and fMAX. This is explained by junction less physics: channel length modulation, bulk conduction and high channel-depth sensitivity to back bias.

International audience; This work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier coupling impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and ΔIon might reach high values, it is demonstrated that regarding digital applications, the coupling-induced fluctuations are well below the mismatch effects. TCAD and SPICE simulations were used to fully understand the phenomenon, to predict the effects at SRAM bitcell level and to propose guidelines to contain the inter-tier electrostatic coupling: the coupling effect can be limited either by increasing the Inter-Layer Dielectric (ILD) thickness or through a top/bottom transistor misalignment.

We investigated the performances of GaN junctionless fin-shaped field-effect transistors (FinFETs) with two different types of gate structures; overlapped- and partially covered-gate. DC, low-frequency noise (LFN), and pulsed I-V characterization measurements were performed and analyzed together in order to identify the conduction mechanism and examine both the interface and buffer traps in the devices. The fabricated GaN junctionless device with overlapped-gate structure exhibits improved DC and noise performance compared to the device with partially covered-gate, even though its gate length is much larger. The LFN behavior was found to be dominated by carrier number fluctuations (CNF). At off-state, the device with partially covered-gate exhibits generation-recombination (g-r) noise on top of 1/ ${f}$ noise. This superposition is correlated with the severe current collapse revealed by pulsed I-V measurements. In contrast, the device with overlapped-gate shows clear 1/ ${f}$ behavior without g-r noise.

International audience; In this paper we demonstrate for the first time how the series resistance of an advanced CMOS device, such as the FinFET, can lead to an incorrect extraction of low-frequency noise parameters. In particular, the use of the carrier number fluctuations with correlated mobility fluctuations model is shown to be very sensitive to the transistor series resistance. We demonstrate how the classic fitting methods can lead to an underestimated value in the extraction of the mobility fluctuations factor Ω. Furthermore, we present an original method for suppressing this effect, by taking advantage of the series resistance immune Y-function.

GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gate-all-around (GAA) structure. In this article, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows a threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low-voltage/power applications. However, the devices with smaller diameters of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance.

In this article, we investigate the impact of the hot carrier (HC) aging on the performance of nanoscale n-channel triple-gate junctionless MOSFETs with channel length varying from 95 down to 25 nm. The devices were electrically stressed in the ON-state region of operation at fixed gate voltage ${V}_{g} = {1.8}$ V and drain bias ${V}_{d} = {1.8}$ V, with the stress time being a variable parameter. The device degradation was monitored through the relative change with stress time of the threshold voltage, subthreshold swing, linear drain current, low-field mobility, series resistance, and gate current. For relatively long-channel transistors ( ${L} = {95}$ nm), the threshold voltage and the subthreshold swing remain almost unchanged, whereas the ON-state drain current is degraded showing a good correlation with the series resistance degradation, caused by HC-induced damage in the drain region. For short-channel transistor ( ${L} = {45}$ nm), the HC-induced damage is extended in the channel region: interface traps are generated, exhibiting good correlation with both threshold voltage and low-field mobility degradations. For the very short-channel device ( ${L} = {25}$ nm), after long stress time, the HC-induced interface degradation is severe, causing a continuous increase of the ideality factor with increasing the gate voltage.

In this chapter, we present the most important aspects of our recent research work concerning the low-frequency noise (LFN) characterization and modeling of Fully Depleted Silicon-on-Insulator (FDSOI) MOSFETs, as well as the development of circuit noise simulation methods. Before doing so, we make a brief introduction (Sect. 1) on the importance of LFN characterization and modeling, especially in sub-μm multi-interface devices such as the FDSOI MOSFETs.

International audience; For the first time, an in-depth analysis of the intertier dynamic coupling and RF crosstalk of digital circuits in 3D sequential integration enables to conclude on the need of a Ground Plane (GP) for various applications. Experiments in conjunction with TCAD simulations reveal the parasitic capacitances responsible for the dynamic coupling effects and their impact is investigated for a 3D sequential 2-bitcell SRAM cell circuit configuration. Furthermore, we show a greater than 20dB suppression up to 100GHz of the inter-tier RF crosstalk, achieved by the addition of a strategically designed polysilicon Ground Plane between active device layers enabling the possibility of heterogeneous 3DSI integration without metallic Ground Plane. We propose a technological solution to create experimentally a 34nm-thick polysilicon GP of 1.8x10 20 at/cm 3 n-doping and 295Ω/sq sheet resistance.

International audience; The negative bias temperature instability (NBTI) is investigated in ultrathin body ultrathin box (UTBB) fully depleted silicon-on-insulator (FD-SOI) p-MOSFETs with zero back gate bias and small drain bias voltage. The threshold voltage shifts during stress at different temperatures and gate bias voltage conditions show that the NBTI is dominated by the trapping of holes in preexisting traps of the gate dielectric, while the recovery transient follows a logarithmic-like time dependence. Considering the hole-trapping/detrapping mechanisms, NBTI modeling has been proposed capturing the temperature and gate voltage dependence.

In this brief, we upgrade our initial drain current compact model for triple-gate junctionless transistors (JLTs) to a continuous model satisfying the source/drain (S/D) symmetry. This is achieved by reformulating the key equations of our original model, using Lambert-function-based terminal charges. The upgraded model is compact, bulk-referenced valid in all regions of operation and it is validated through comparison with experimental data to verify its accuracy. The symmetry condition is investigated and validated performing the dc Gummel symmetry test (GST) for all derivatives up to the fifth order.

The drain current in nanoscale fully depleted ultra-thin body and buried oxide n-MOSFETs is studied in terms of critical dynamics. The time series formed by the measured current through the channel of the MOSFET, appears to have the form of random telegraph noise (RTN). This timeseries is analyzed by the Method of Critical Fluctuation (MCF). Its dynamics are compatible with critical intermittency. According to the quantitative analysis performed, the current-value distributions are compatible with the spontaneous symmetry breaking phenomenon; in addition, it also carries information of criticality according to the corresponding power law. Finally, MCF analysis identified traces of tri-critical dynamics.

In this paper, Low Frequency Noise (LFN) characterization of SP500 polymer-based Organic Thin Film Transistors with a nonfluorinated dielectric material is presented. The work aimed at identifying the mechanism of 1/f noise as well as inspecting the quality of the gate dielectric interface. Analysis of the LFN experimental data reveals that the 1/f noise power spectral density (PSD) follows 1/f γ frequency dependence over 1 Hz–10 kHz range. The normalized current noise PSD is found to vary similar to the squared-transconductance drain current ratio with respect to drain current, and is inversely related to the gate-area. Furthermore, the high carrier mobility (on the order of 2–3 cm 2 / Vs) obtained in these devices indicates that low density of traps exists in the semiconducting organic thin film. Such results ascribed the origin of 1/f noise to the dynamic exchange of charge carriers between the gate-dielectric traps and the channel. In addition, Nst values extracted from the 1/f noise experimental data reflect the enhanced quality of the gate dielectric and the interface it forms with the channel material.In this paper, Low Frequency Noise (LFN) characterization of SP500 polymer-based Organic Thin Film Transistors with a nonfluorinated dielectric material is presented. The work aimed at identifying the mechanism of 1/f noise as well as inspecting the quality of the gate dielectric interface. Analysis of the LFN experimental data reveals that the 1/f noise power spectral density (PSD) follows 1/f γ frequency dependence over 1 Hz–10 kHz range. The normalized current noise PSD is found to vary similar to the squared-transconductance drain current ratio with respect to drain current, and is inversely related to the gate-area. Furthermore, the high carrier mobility (on the order of 2–3 cm 2 / Vs) obtained in these devices indicates that low density of traps exists in the semiconducting organic thin film. Such results ascribed the origin of 1/f noise to the dynamic exchange of charge carriers between the gate-dielectric traps and the channel. In addition, Nst values extracted from the 1/f noise experimental...

A thorough investigation of trap density (Dit) in defective zones of Tunnel FET (TFET) devices is presented. The TFETs were fabricated with standard high-temperature (HT, 1050ºC) and low-temperature (LT, 600ºC) processes [1]. A larger average of defects at the top surface in LT process TFETs was found [2]. For the first time, we use charge pumping (CP) method [3] in Silicon On Insulator (SOI) HT & LT TFETs (Fig. 1) with a ultrathin silicon thickness of 11 nm, EOT of 1.18 nm and 145 nm thick BOX [4]. CP method requires the presence of majority and minority carriers since ICP current results from the recombination of detrapped electrons in the channel region with holes. Therefore, ICP is proportional to Dit and frequency. In FDSOI structures, the top and bottom interfaces are extremely close. This means that the pulse applied on the front-gate can sweep the whole film from accumulation to inversion. Carriers from the top region could also be trapped in defects located at the back interface, enabling a net contribution to the ICP current and thus, providing a non-accurate value of Dit. For this reason, it is mandatory to apply a back-gate voltage (VBG) in order to avoid the scanning of the back interface traps. In the past, the influence of the substrate polarization on the CP current has been studied for SOI devices with thicker films (from 450 nm to 100 nm) [5,6,7]. Here, we present the relation between the CP current (experiments) and the carrier concentration (TCAD simulation), for TFETs with ultrathin film. Specifically, for VBG = -20V at VG,top = +0.65V the electron density is located at the top surface, while the back interface is depleted of electrons (lower than 1015 cm-3). For VG,base = -0.65V, two layers of holes are formed at the channel interfaces. Considering both mechanisms at the same time, during the falling edge of the pulse, the concentration of electrons that could be trapped by defects at the bottom interface is at best equal to 1015 cm-3. Although the concentration of holes is significantly higher, the recombination at the back-interface is negligible because it is proportional to the lowest concentration of either carriers (here electrons). So, traps at the back-interface are rather empty of electrons and their contribution to ICP is low. The situation is different for VBG = +20V: at VG,top = +0.65V, electrons are present at each interface. At VG,base = -0.65V, the hole density is only formed at the top surface, while the back-interface is depleted of holes, deactivating the possibility of recombination. Finally, when VBG = 0V, electron and hole concentrations at the back-interface are more similar and participate in the recombination process. Simulation results indicate that the variation of the ICP depends of the carriers available for recombination at the front and back interfaces. Therefore either one of these concentrations decreases when the back-gate voltage is more negative (fewer electrons) or more positive (fewer holes), not only at the back but also at the top interface. Fig. 2 shows the minority carrier concentration (which governs the recombination rate and ICP) for different applied back-gate voltages. The curve of the carrier concentration presents the same shape as the one obtained for the experimental charge pumping current [2], explaining the recombination mechanism. Same consistent results between experiments and simulations have been obtained for different VG,base voltages respectively (-0.35 V and -0.85 V). We discuss in detail the shape of CP curves as well as the back-gate selection for the traps at the back-interface to have negligible contribution to the front-pulse CP current. Our updated CP method is applied to determine and compare the density of traps in HT and LT FD-SOI TFETs. Acknowledgments This work is partly funded by the French Public Authorities through NANO 2017 program and EQUIPEX FDSOI11. References C. Le Royer et al, EuroSoi-Ulis, pp. 69-72, (2015). C. D. Llorente et al, IEEE S3S, (2018). J. S. Brugler and P.G.A. Jespers, IEEE TED., vol. 16, no. 3 (1969). C. D. Llorente et al, Solid-State Electron., vol.144, pp.78-85 (2018). T. Ouisse et al, Trans. Electron Devices., vol.38, no.6 (1991). D. J. Wouters et al, Trans. Electron Devices, vol.36, no.9 (1989). Y. Li and T. P. Ma, Trans. Electron Devices, vol.45, no.6 (1998). Figure 1

International audience; This work presents for the first time an analytical study of the electrostatic coupling between bottom and top layer of 3D sequential integration devices, regarding its impact on both static and noise behavior. The effect is demonstrated experimentally through statistical measurements, and TCAD simulations are used to further examine its properties and propose ways for the limitation of inter-tier coupling. It is demonstrated that regarding digital applications, the coupling-induced fluctuations are well within the mismatch variation level.

International audience; Two different lateral GaN-based nanowire gate-all-around transistors with and without 2-D electron gas (2-DEG) channel were fabricated using top-down approach, and their noise characteristics were investigated. The nanowire transistor with 2-DEG channel had a relatively larger channel cross section, which consists of regrown AlGaN/GaN plateau on the trapezoidal GaN layer, and exhibited negative threshold voltages ( ${V} _{\textsf {th}}$ ). The transistor without 2-DEG channel consisted only GaN layer with triangular-shaped smaller channel cross section and exhibited a positive ${V} _{\textsf {th}}$ . Both nanowire transistors clearly demonstrated typical $1/{f}$ noise characteristics, but the AlGaN/GaN nanowire transistor with 2-DEG channel showed larger noise magnitude. The noise characteristics of both devices are well explained by the carrier number fluctuation with correlated mobility fluctuation model. Using this model, the interface trap densities and the remote Coulomb scattering parameters were extracted, revealing a worse interface quality for the AlGaN/GaN device on the one hand, but stronger scattering for the narrow GaN transistor on the other hand.

International audience; The low-frequency noise in triple-gate junctionless n-MOSFETs, with channel lengths varying from 95 to 25 nm and operating in the bulk and accumulation modes, is investigated by measurements in the frequency and time domains. The experimental drain current noise spectra present 1/f and Lorentzian-type behavior components. The noise spectra in the time domain reveal that the Lorentzian-type behavior components are due to the capture and emission processes of carriers at discrete gate insulator traps, resulting in random telegraph noise (RTN). The 1/f behavior can be described by the carrier number with the correlated mobility fluctuations model. In the below-threshold region, the conducting channel is isolated from the interface by depletion region. In the above-threshold region (bulk conduction mode), the histograms of the time-domain data show multilevel switching events, from which one or more individual traps can be distinguished. The extracted time constants of two-level RTN signals indicate the interaction of a single trap either with the channel or with both channel and gate. The relative RTN amplitude is described with the carrier number with the mobility correlated fluctuations physics-based model or with the “hole in the inversion layer” stochastic simulation-based model, enabling estimation of the flat-band voltage fluctuation caused by the RTN.

A detailed study of the hot-carrier degradation in nano-scale fully depleted ultra-thin body and buried oxide n-MOSFETs is presented. The degradation mechanisms were identified based on static current-voltage measurements. The degradation of the transistor was explained by considering generation of traps at the gate dielectric/Si interface and traps located within a tunneling distance of the interface. All stress parameters are considered describing with semi-empirical relations their impact on the transistor parameters. Based on our analytical compact model, we propose an aging hot-carrier model predicting with good accuracy the device degradation stressed under different bias conditions using a unique set of model parameters. Display Omitted The hot-carrier degradation of nanoscale UTBB FD-SOI n-MOSFETs has been investigated under different drain and gate bias stress conditions.The degradation mechanisms have been identified by studying the static current-voltage characteristics measurements.The impact of the HC degradation on the device parameters has been expressed with semi-empirical models in terms of the stress time, channel length, drain bias and gate bias.Based on our analytical compact model, HC aging model is proposed enabling to predict the device degradation stressed under different bias conditions, using a unique set of few model parameters determined for each technology through measurements.

session C1L-A: gas sensors & stochastic effects; International audience; This paper describes the study carried out in order to characterize the influence of the main fabrication steps of the silicon nano-gauge on their l/f noise. Geometry of the nano-gauge, doping level, thinning process of gauges, doping before or after gauges patterning, release process and treatments for trap curing have been studied. Gauges release has a great impact on the l/f noise: it increases the noise by a factor of up to 100 for the smallest gauges. N 2 H 2 annealing and O 2 plasma treatment reduce the noise generated by the release of the gauge. We assume that the origin behind the noise increase is the trapping-detrapping of carriers in surface traps of the nano-gauge.

session: SOI devices 2; International audience; This work presents for the first time a self-contained defect-aware implementation of a Fully Depleted SOI model, capable of reproducing low-frequency noise, random telegraph noise and time-dependent variability effects in transient circuit simulations in the most realistic way. The impact of back-bias and the response under non-stationary bias conditions are also accounted for. Furthermore, a defect-aware transient simulation of the Read Static to Noise Margin for a 6TSRAM cell is also presented, as a circuit case study.

session: 3D technology II; International audience; Tunnel FETs fabricated using the low-temperature Cool Cube TM process are compared with devices made with standard high-temperature (HT) technology. Charge pumping (CP) and low-frequency noise (LFN) measurements were performed to evaluate the impact of low-temperature (LT) process on the device performance. LT devices feature a higher density of source/drain junction defects, due to lower thermal budget, causing higher levels of LFN. These defects enhance the trap-assisted tunneling (TAT) current which is further amplified by the more abrupt junctions obtained using LT processing.

session B4L-F: Analog/RF and High mobility; International audience; A detailed static and low frequency noise characterization of InGaAs/OI MOSFETs has been performed. The mobility in long channel devices is very good for such 20nm thin film III-Vvv channels. However, the mobility in short channel devices is strongly degraded down to sub 10nm. As in Silicon MOSFETs, this mobility limitation in scaled devices could originate from similar process-induced channel scattering centers in both III-V and Si MOSFETs. The gate dielectric/channel interface also reveals a high density of fast as well as slow oxide traps as measured by subthreshold swing and LF noise.

session 9: Noise characterization; International audience; We investigated the 1/f noise generation mechanism in surface-treated AlGaN/GaN heterojunction field-effect transistors (HFETs) with different gate length and gate-to-drain distance (Lgd). From the normalized drain current power spectral density (PSD) SIdId 2 versus Id, the AlGaN/GaN HFET with shorter gate length exhibited the Hooge mobility fluctuation (HMF) in subthreshold region and the carrier number fluctuation (CNF) above threshold gate voltage. On the other hand, the HFET with longer gate of 20 μm followed the correlated mobility fluctuation (CMF), irrespective of the gate bias. The extracted trap density (Nt) in the HFET with shorter gate length was noticeably less than that in the HFET with longer length. The input gate voltage power spectral density (PSD) proves that the HFET with shorter gate length suffers from higher interface roughness scattering.

DC and 1/ ${f}$ noise performances of the AlGaN/GaN fin-shaped field-effect transistor (FinFET) with fin width of 50 nm were analyzed. The FinFET exhibited approximately six times larger normalized drain current and transconductance, compared to those of the AlGaN/GaN planar metal-insulator-semiconductor heterostructure field-effect-transistor (MISHFET) fabricated on the same wafer. It was also observed that the FinFET exhibited improved noise performance with lower noise magnitude of ${8.5} \times {10}^{-{15}}~\text{A}^{{2}}$ /Hz when compared to the value of ${8.7} \times {10}^{-{14}}\text{A}^{{2}}$ /Hz for the planar MISHFET. An intensive analysis indicated that both devices follow the carrier number fluctuation model, but the FinFET suffers much less charge trapping effect compared to the MISHFET (two orders lower charge trapping was observed). Moreover, the FinFET did not exhibit the Lorentz-like components, which explains that the depleted fin structure effectively prevents the carriers from being trapped into the underlying thick GaN buffer layer. On the other hand, the slope of the noise is 2 irrespective of drain voltage and apparently showed the Lorentz-like components, especially at high drain voltage in MISHFET device. This explains that the carrier trapping/detrapping between the 2-D electron gas channel and the GaN buffer layer is significant in MISHFET.

International audience; A complete static and low frequency noise characterization of ultra-thin body InAs MOSFETs is presented. Characterization techniques, such as the well-known Y-function method established for Si MOSFETs, are applied in order to extract the electrical parameters and study the behavior of these research grade devices. Additionally, the Lambert-W function parameter extraction methodology valid from weak to strong inversion is also used in order to verify its applicability in these experimental level devices. Moreover, a low-frequency noise characterization of the UTB InAs MOSFETs is presented, revealing carrier trapping/detrapping in slow oxide traps and remote Coulomb scattering as origin of 1/f noise, which allowed for the extraction of the oxide trap areal density. Finally, Lorentzian-like noise is also observed in the sub-micron area devices and attributed to both Random Telegraph Noise from oxide individual traps and g-r noise from the semiconductor interface.