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Designing the next generation of high-resolution displays requires high pixel density per area and small pixel sizes without compromising the optical quality. Quantum dots (QDs) have been demonstrated as a promising material system for down-conversion of blue emission as they provide pure colors on the wide color gamut. However, for high color-conversion efficiency, the required QD film thickness has not been compatible with small pixel sizes. In this work, we develop a new type of freestanding QD-based color converter for efficient optical down-conversion from inorganic blue light-emitting diodes (LEDs) in a color-by-blue configuration. CdSe/ZnS core-shell QDs in a UV-curable polymer matrix are encapsulated within cavities formed by patterning and bonding a pair of patterned quartz substrates. By controlling the required QD thickness and the pixel size independently, we demonstrate freestanding monochrome red and green converters with small pixel sizes down to 5 × 5 μm

In this article, we demonstrate the Ti/TiN/Al (15/50/50 nm) ohmic contact on InGaP/GaAs heterojunction bipolar transistors (HBTs) epitaxially grown on 200-mm Si substrate. We study the rapid thermal annealing (RTA) effect of the metal stack on both n-type InGaAs and p-type GaAs. The dc characteristics of the HBT devices fabricated using the Ti/TiN/Al metal contacts have been analyzed. Contact resistances (R-c)

Speculations regarding electronic and photonic properties of strained germanium (Ge) have perpetually put it into contention for next-generation devices since the start of the information age. Here, the electromechanical coupling of111Ge nanowires (NWs) is reported from unstrained conditions to the ultimate tensile strength. Under tensile strain, the conductivity of the NW is enhanced exponentially, reaching an enhancement factor of ∼130 at ∼3.5% of strain. Under strains larger than ∼2.5%, the electrical properties of Ge also exhibit a dependence on the electric field. The conductivity can be further enhanced by ∼2.2× with a high bias condition at ∼3.5% of strain. Cyclic loading tests confirm that the observed electromechanical responses are repeatable, reversible, and related to the changing electronic band structure. These tests reveal the excellent prospects for utilizing strained Ge NWs in photodetector or piezoelectronic transistor applications, but significant challenges remain to realize strict direct band gap devices.

We report an In0.3Ga0.7As HBT device grown on a 200 mm Si wafer using GeSi as virtual starting substrate and InAlAs as the compositionally graded buffer layer from GaAs to In0.3Ga0.7As lattice constant. A DC gain, emitter-base, and base-collector ideality factors of 10, 1.43, and 1.56, respectively, are obtained for a device with an emitter area of 40×50µm2. Small-signal simulation of an In0.3Ga0.7As HBT device with 2x8 µm2 emitter area shows that current gain cutoff frequency (fT) and maximum cut-off frequency (fMax), of 50 GHz and 220 GHz, respectively, can be achieved with base doping and layer thickness of 2×1018cm-3 and 30 nm, respectively. Ministry of Education (MOE) National Research Foundation (NRF) Submitted/Accepted version This work was supported by the National Research Foundation Singapore through the Singapore MIT Alliance for Research and Technology’s Low Energy Electronic Systems IRG and MOE AcRF Tier-2 T2EP50121-0001.

N-p-n InGaP/GaAs double heterojunction bipolar transistor has been successfully grown on a 200 mm Ge/Si wafer using metalorganic chemical vapor deposition with low defect density of 107 cm $^{-2}$ . Non-gold metals of Ni/Ge/Al and Ti/Al are used to form the ohmic contact for small pieces device fabrication. Both direct-current (dc) and high-frequency characteristics of the device were measured. The device with emitter area of $6\times8 \mu {\text {m}}^2$ shows a dc gain of 55 at a collector current of $I_{c}$ = 4 mA, with high collector-emitter breakdown voltage of ~17 V. The high-frequency response with cutoff frequency ( $f_{T}$ T) of 23 GHz and maximum available frequency ( $f_{\text {max}}$ T) of 10 GHz can be achieved. These results demonstrate that InGaP/GaAs double heterojunction bipolar transistor grown on low defect density Ge/Si wafer has the potential for realizing III-V CMOS integrated platform for high-frequency applications.

This paper presents a logic inverter circuit consisting of both CMOS and GaN devices to drive high-torque DC motors requiring high voltages in various robotics applications. The GaN+CMOS inverter can be monolithically integrated with CMOS digital circuits on a single die, accommodating a 5V CMOS logic level input and providing a 30V output voltage using depletion-mode GaN HEMTs without negative gate bias circuitry. Electro-thermal simulations are also performed to analyze the temperature of CMOS devices affected by nearby GaN HEMTs.

The needs of electronics are endless. The complexity in designing a circuit to meet high demand markets has increased daily. Furthermore, the urge for high power gain for high-efficiency RF applications leads to searching a replacement of Si material. III–V compound semiconductor (CS) materials provide a promising technology booster but integrating into the state-of-the-art Si equipment for VLSI faces some challenges for circuit designs and device fabrication. To ease the design complexity, Process Design Kit (PDK) has been widely used for modern semiconductor designs. This paper presents cross-platform III–V/Si circuit simulation, schematic and layout design, and integration of III–V/Si design verification for VLSI on 200-mm wafer in Si CMOS fabrication environment.

High quality GaN was grown on 200 mm Si (111) substrates by using AlN and 3 step-graded AlxGa1-xN as the buffer layer in a metalorganic chemical vapor deposition system. We have investigated the influence of NH3 pre-flow time on the threading dislocation density (TDD) of AlN, AlGaN buffer layers and GaN layers. It was observed that the compressive stress introduced into the buffer layer and GaN is dependent on the nitridation time. The lowest TDD for GaN obtained in our samples was ~1 × 109 cm−2 for screw type and 3.2 × 109 cm−2 for edge type dislocations, as obtained from atomic force microscopy and further confirmed by high resolution X-ray diffraction analysis. The threading dislocations generated in the first buffer layer (AlN) during its nucleation are found to influence the TDD in the subsequent layers. Samples without an intentional nitridation step exhibit higher TDD compared to the samples with optimal nitridation time. Longer nitridation time also leads to poor crystalline quality likely because of amorphous SiNx formation at the interface.

Integration of Si-CMOS and III-V compound semiconductors (with device structures of either InGaAs HEMT, InGaP LED, GaAs HBT, GaN HEMT or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN LED or HEMT on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.

Compositionally graded InAlAs buffers grown by metal–organic chemical vapor deposition are impaired by phase separation occurring at In content higher than 35%. Phase separation results in rough epilayers with poor crystalline material quality. By introducing low temperature grown InGaAs interlayers in the compositionally graded InAlAs buffer, the surface roughness decreases, allowing a grading of up to In 0.60 Al 0.40 As without any phase separation occurring. This composite buffer is applied to fabricate a 200 mm diameter InP-on-Si virtual substrate with a threading dislocation density around 1 × 10 8 cm −2 .

We report on the growth of In0.30Ga0.70As channel high electron mobility transistor (HEMT) epi-layers on a 200-mm Si substrate by metal-organic-chemical-vapor-deposition. The HEMT layers were grown on the Si substrate by using a ~3- ${\mu }\text{m}$ thick epitaxial buffer composing of a Ge layer, a GaAs layer, and a compositionally graded and strain relaxed InAlAs layer. The optimized epitaxy has a threading dislocation density of less than $2 {\times } 10^{{7}}$ cm−2 and a root mean square surface roughness of ~6.7 nm. The device active layers include a ${ {\delta } }$ -doped InAlAs bottom barrier, a ~15-nm thick InGaAs channel, a ~8-nm InGaP top barrier layer and a heavily doped InGaAs contact layer. MOSHEMTs with channel length down to 130 nm were fabricated. The devices achieve a peak transconductance of ${\sim }450 ~{\mu }\text{S}/ {\mu }\text{m}$ at ${V} _{ D}$ of 0.5 V. The peak effective mobility ( ${\mu }_{\text {eff}}$ ) in a device with a channel length of 20 $ {\mu }\text{m}$ device channel was ~3700 cm2/ $\text{V} {\cdot }\text{s}$ .

This paper demonstrates InGaAs vertical nanowire (VNW) MOSFETs fabricated via an improved top–down approach, the performance of which is comparable to that of the best bottom–up devices in terms of the balance between transport and electrostatics. These devices, when contrasted with an earlier generation fabricated by a similar technology, have enabled the first experimental study of source/drainasymmetry in InGaAs VNWMOSFETs. The transconductance differs significantly when swapping source and drain due to inherently different top and bottom contact electrical resistance. This also results in distinct asymmetry in the saturation behavior of the output characteristics. On the other hand, diameter nonuniformity along the nanowire (NW) length is responsible for asymmetry in the subthreshold characteristics. A uniform NW cross section, enabled by our improved InGaAs dry etch technology in the present devices, eliminates the asymmetry of the electrostatics, which was observed in our previous work.

In this work, we investigate the bonding processes to improve Germanium-on-insulator (GOI) quality for III–V integration, and an InGaP LED has been grown and characterized on this GOI substrate. The threading dislocation density (TDD) of GOI was reduced from 5.1 ± 0.8 × 108 cm−2 to 4.3 ± 0.4 × 107 cm−2 by chemical mechanical polishing (CMP) processes. The thermal and mechanical properties of the CMPed GOI have been characterized. It showed that a 200 nm thermal oxide layer effectively absorbed the hydrogen generated from the bonding by-product reactions, which avoided the formation of thermal bubbles and provided sufficient stability during high temperature epitaxy processes. After post-bonding annealing, a high bonding strength of 1720.6 mJ/cm2 was achieved. Then, an AlInGaP/InGaP multi-quantum well (MQW) LED was grown on GOI substrate. Compared to LED on bulk Ge substrate, LED on GOI showed high leakage current due to the presence of high TDD in the Ge layer and the LED junctions. The electroluminescence of LED on GOI was approximately 50% of the light output of LED on bulk Ge.

In this letter, a novel compact on-chip output matching network to achieve harmonic impedance matching is proposed. With the proposed matching network, a highly efficient GaN monolithic microwave circuit power amplifier (PA) is designed for 5-GHz wireless local area network 802.11ac application. The implemented PA achieves a maximum power-added efficiency (PAE) of 49.5%-61.3% over the frequency band from 4.9 to 5.9 GHz, with a saturated output power (Psat) of 34.6-36.1 dBm. When tested with 802.11ac VHT80 MCS9 (80 MHz, 256-quadratic -amplitude modulation) signal with 11.3-dB peak-to-average power ratio, the PA achieves an average output power of 23.7-26.3 dBm, with a PAE of 24.9%-30.9%, while meeting the standard error vector magnitude specification of -32 dB. Accepted version

In this work, inductors and capacitors are designed and fabricated on an InGaAs-on-Insulator (InGaAs-OI) wafer that enables millimeter-wave (mmWave) integrated circuits design together with InGaAs high electron mobility transistors (HEMTs) for 5G mobile devices. Wafer bonding process between an InGaAs wafer and a high resistive substrate is developed and optimized for high frequency operation. Fabricated passive components are measured and compared against the electro-magnetic (EM) simulation data. A phase shifter circuit which is essential for directional beamforming in 5G mmWave communications is designed based on the measured data, which demonstrates the feasibility of integrated mmWave circuits design on an InGaAs-OI wafer for high data rates and small form factor 5G mobile devices.

To improve the bonding yield and the brightness of the final integrated Si-CMOS + GaN LED wafers, two issues have to be addressed. The first problem is the surface protrusions such as melt-back etching and hillocks which are the common surface imperfections on the surface of GaN/Si substrates. This prevents the direct contact of the two wafers and results in unbonded area. To address this, a CMP process that using conventional SiO 2 slurry with the addition of diamond nanoparticles is carried out on the GaN (LED)-on-Si wafer prior to the bonding to the Si-CMOS wafer. The second issue is that the Si substrate of the GaN LED wafer absorbs photons which lowers the light emitting efficiency of the LEDs. We address this issue by transferring the Si-CMOS + GaN LED films from the Si (111) wafer onto a transparent quartz substrate. By addressing these issues, a high bonding yield and high brightness of Si-CMOS + GaN LED on quartz substrate can be realized.

This paper discusses phased array system design issues for millimeter-wave circuits in 5G mobile devices. 5G technologies to enable extremely high data rates (10Gbps)., ultra-low latency (1msec), and massive number of devices (1M devices/km2) can support broad range of application spaces which have never been considered before. Directional beamforming by utilizing a phased array system in the millimeter-wave frequency ranges helps to improve system level efficiency providing spatial multiplexing capability. However., beamforming requires multiple RF channels and antennas with phase and gain control circuitry., which affects the radio form factor and degrades the performance due to the increased parasitic. Furthermore., 5G millimeter-wave power amplifiers have to be inherently linear without digital calibration because multiple RF channels cause complex and time-consuming calibration procedures prohibited in commercial mobile products. Since there is a tradeoff between linearity and efficiency., high efficiency in a millimeter-wave power amplifier cannot be achieved with CMOS only. Thus III-V devices and their monolithic integration with CMOS circuits are crucial for a small form factor and power efficient 5G mobile devices.

GaN-on-Si has revealed its great potential for next-generation power electronics applications, however, there remains a challenge in increasing the breakdown voltage $(BV_{\text{off}})$ due to the limit of the GaN epilayer thickness on large size wafers. In this work we propose a GaN-on-Insulator (GNOI)-on-Si structure to address this issue. A 200 mm GNOI-on-Si wafer was prepared through removing the original Si substrate of a GaN-on-Si wafer and bonding onto a fresh SiO 2 /Si substrate. HEMTs were fabricated with measured $BV_{\text{off}}$ much larger than those on GaN-on-Si. Record high $BV \text{off}$ up to 2200 V and high figure-of-merit (FOM) $BV_{off^2}/R_{\text{on, sp}}$ up to 1.87 GW/cm2 have been achieved in the HEMTs on a 200 mm GNOI-on-Si wafer with a thin GaN epilayer of $3.2 {\mu m}$ .

To improve the bonding yield and the brightness of the final integrated Si-CMOS + GaN LED wafer, two issues need to be addressed. The first problem is the surface protrusions such as melt-back etching and hillocks which are the common surface imperfections on the surface of GaN/Si substrates. This prevents the direct contact of the two wafers and create unbonded area. To address this, a CMP process that using conventional SiO 2 slurry with additional diamond nanoparticles is carried out on the GaN (LED)-on-Si wafer prior to the bonding to the Si-CMOS wafer. The second issue is the Si substrate of the GaN LED wafer absorbs photons which lowers the light emitting efficiency of the LEDs. We address this issue by transferring the Si-CMOS + GaN LED films from the Si (111) wafer to a transparent quartz substrate. By addressing these issues, a high bonding yield and high brightness of Si-CMOS + GaN LED on quartz substrate is realized.

Integrate LEDs and CMOS circuits on large Si wafers can enable numerous new applications and add new functions to Si integrated circuits. In the past efforts on the integration of AlGaInP LEDs and CMOS circuits on 200 mm Si wafers, we have solved fundamental problems such as III-V semiconductor heteroepitaxy on Si substrates, wafer bow control, and bonding of LED wafers with CMOS wafers. Our latest achievement in this work is the demonstration of working devices processed on 200 mm LED wafers. We will present our efforts on the development of CMOS-compatible Ohmic contacts, 200 mm wafer-scale processing, and characteristics of the devices. We have evaluated different metals as CMOS-compatible low-resistance Ohmic contacts to the AlGaInP LEDs. We will compare the performance of the LEDs using the different metal contacts. We will present our progress on the process of CMOS-bonded LED wafers. Different from the LED-only wafers, the process of CMOS-bonded LED wafers can only be done in opened trenches, which adds extra difficulties. In addition, we will show the method we have developed for the re-entry of the CMOS-LED integrated wafers to the CMOS foundries for the end-of-line metal interconnections. Finally, potential applications using the CMOS-integrated LEDs will be discussed.

One effective approach to reduce the cost of GaN devices is to use 200 mm-diameter and 725 μm-thick p-Si substrates. We demonstrated RF and power GaN-on-Si HEMTs on small pieces of samples from 200 mm wafers using Au-contained process. f T /$f_{\max}$ of 36/33 GHz were achieved in 0.25 μm gate RF devices and breakdown voltage (BV off )>1200V was achieved in power devices. 200 mm wafers were fabricated using CMOS-compatible process and devices with BV off >850 V were achieved.

This paper describes the analysis following the breakdown of an ion cyclotron radio frequency (ICRF) tuner purchased from Advanced Ferrite Technology (AFT). The codes used in the analysis were CST and COMSOL. These codes use the standard gyromagnetic model for the ferrite, which gives results that are largely in error when compared with measurements at ICRF and at lower hybrid frequencies. We have measured a slab of the ferrite used in the ICRF tuner provided by AFT and from these measurements we have constructed a tabular model of the ferrite and inserted it into the COMSOL code. The results give performance that closely agrees with the performance specifications issued by AFT. We then used this modified code to correlate the simulation with the destructive evidence found in the tuner. The correlation was good between the destruction spot and the peak of the standing electric field. Pictures of the destruction and the heating in the tuner and the standing field results from the simulation are given.

Deep level traps in the low dislocation density, 5.1 × 107 cm−2, semi-polar GaN (11–22), grown on patterned sapphire substrate was characterized for the first time using deep level transient spectroscopy (DLTS) and deep level optical spectroscopy (DLOS). DLTS revealed two deep levels ET1 = EC − 0.24 eV and ET2 = EC − 0.41 eV in the semi-polar GaN layer. The dominant trap ET1 = EC − 0.24 eV with a density of 6.1 × 1014 cm−3, is documented in c-plane and m-plane GaN. It is attributed to VN. DLOS revealed two deep level traps ET3 = EC − 1.20 eV and ET4 = EC − 3.26 eV. The dominant level ET4 = EC − 3.26 eV is also observed in non-polar m-plane GaN grown on sapphire and it is attributed to CN acceptor-like state. The total trap density of the semi-polar GaN is about 2 × 1016 cm−3, which is comparable with that found in c-plane GaN.

CBrCl 3 is shown to be a useful precursor for heavy p-type carbon doping of GaAs x P 1− x grown via metalorganic chemical vapor deposition (MOCVD) across a range of compositions. Structural and electrical properties of the GaAsP films were measured for various processing conditions. Use of CBrCl 3 decreased the growth rate of GaAsP by up to 32% and decreases x by up to 0.025. The dependence of these effects on precursor inputs is investigated, allowing C-doped GaAsP films to be grown with good thickness and compositional control. Hole concentrations of greater than 2×10 19 cm −3 were measured for values of x from 0.76 to 0.90.

Metamorphic epitaxy offers the possibility of growing devices on wafers composed of different materials that might be larger than the native bulk substrates for a potential cost-reduction of III–V components; this is especially important when native substrates with desired lattice constants are not available. This article reviews the concepts of metamorphic epitaxy of III–V compound semiconductor materials and examines how they have been applied to the development of advanced transistor devices. These metamorphic devices are expected to be a key enabler of future heterogeneous integrated circuits in which Si and III–V devices are monolithically integrated on a wafer scale using complementary metal oxide semiconductor-like process flows.

We investigated the epitaxy and morphology of GaAs/Ge superlattices grown by metal organic chemical vapor deposition (MOCVD) under a range of conditions. The surfaces of Ge layers deposited on GaAs at 650 °C and 100 Torr are observed to be rough in cross-sectional transmission electron microscopy. When either the temperature is lowered to 500 °C or the pressure is increased to 250 Torr, the surface of the first deposited Ge layer is observed to be smooth. This behavior suggests that Ge roughening is a thermodynamically favorable process that can be kinetically limited with appropriate growth conditions. At 500 °C, GaAs islands on Ge do not completely coalesce into one film. This may result from poor surface coverage; the short depositions would not be sufficient to coarsen and completely coalesce the islands. At 650 °C, growth on offcut substrates did not suppress antiphase boundaries, likely due to the unique conditions for GaAs/Ge superlattice growth. A wide-range of two- and three- dimensional nanostructures are formed and should allow insight in structure-property correlations in semiconducting thermoelectric materials.

SiGe films were grown on a chemical vapor deposition (CVD)-grown Si0.88Ge0.12/Si (0 0 1) graded film with different growth solution compositions using a temperature interval of 950-940 °C by liquid phase epitaxy (LPE). The LPE films grown on the CVD-grown SiGe/Si (0 0 1) graded film are ≥86% relaxed, much more relaxed than those on bare Si (Wang and Quitoriano, 2019) since the existing threading dislocations in the CVD-grown SiGe/Si (0 0 1) graded film glide to create misfit dislocations without needing to nucleate new ones. The threading dislocation density of the LPE films is slightly lower than that of the CVD-grown SiGe films and on the same order of magnitude, ~106 cm−2. Since the CVD-grown SiGe/Si (0 0 1) graded film was annealed for 4 h before the LPE growth occurred, the properties of the CVD-grown SiGe/Si (0 0 1) graded film were studied and we found that the CVD-grown SiGe/Si (0 0 1) graded film have SiGe islands appear all over the surface aligned along the 〈1 1 0〉 crosshatch morphology and become more relaxed after annealing.

We report the time-resolved light emission measurement of a nanoscale electrically-injected III-V light emitting diode coupled to a metal antenna. Spontaneous emission lifetime decreases from 1.6 ns to 250 ps with an antenna.

Recently, sub-10-nm-diameter InGaAs vertical nanowire (VNW) MOSFETs have been demonstrated. The key to this achievement was the use of Ni for the top ohmic contact. In this paper, we present a detailed study of the impact of Ni and Mo contacts on the electrical characteristics of highly scaled InGaAs VNW MOSFETs. Sequential annealing experiments are presented that reveal the optimum temperature for each type of contact. A negative temperature dependence of the ON-resistance of 7-nm-diameter Ni-contacted devices suggests the existence of an energy barrier. We also observe an unexpected transconductance and drain-induced barrier loweirng (DIBL) dependence on transistor diameter in Ni-contacted devices as well as abnormal DIBL asymmetry to swapping source and drain. All these results can be explained by Ni diffusing down the nanowire during the contact annealing process, reducing the effective channel length, and creating a Schottky-barrier drain.

GaN-on-Silicon growth by MOCVD is wildly discussed in the context of stress and strain management. The low bow AlGaN/GaN structure grew on 200mm Si(111) wafer was demonstrated in this study. After using the sapphire pits on the normal flat susceptor, the wafer bow and residual stress decrease to 21.27um and 0.28GPa tensile stress. The GaN quality and the Rs in HEMT also got huge improvement. The sub-micron devices also show the comparable results in DC and small signal characteristics.

In this paper, we systematically investigate the use of multilayer antireflection coatings (ARC) on GaAs 0.69 P 0.31 /Si dual-junction solar cells for achieving broadband reflection suppression. We incorporate dispersion, absorption, and both coherent and incoherent interference, by modeling the solar cell as a multilayer medium of thin films and a substrate, using the transfer matrix method. The analytical model is verified through reflectance measurements on a GaAs (1 −x ) P x /GaP stack. Our results show that optimized double- and triple-layer ARCs can minimize reflectance to below 5% within the spectral range of ∼400–945 nm, with the latter maintaining this performance over a broader spectrum of 390–1000 nm, in comparison to 25–45% reflectance for the bare solar cell.

We demonstrate the influence of the arsine partial pressure (p(AsH3)) on the quality of a GaAs layer grown on Ge substrate by metal organic chemical vapor deposition. The GaAs quality improves with p(AsH3) used during the 100 nm thick GaAs buffer layer. By growing a GaAs buffer layer at 630 °C with p(AsH3) of 5 mbar, we obtain a smooth GaAs layer with a root mean square roughness of 4.7 Å. This GaAs layer does not contain anti-phase boundaries. With these optimized growth parameters, we fabricate a virtual GaAs substrate on a 200 mm silicon wafer as a first step towards the integration of III–V devices on silicon., National Research Foundation of Singapore

A high performance germanium (Ge) based anode is achieved through an appropriate air annealing post-treatment. Annealed Ge is fabricated by sputtering of Ge onto a stainless steel (SS) current collector and then annealed in air. It shows high specific and volumetric capacities of 1186 mA h g −1 and 5887.4 mA h cm −3 , respectively, at the rate of 812 mA g −1 up to 50 cycles. These specific and volumetric capacities are approximately a factor of 20 higher than those from as-deposited Ge on the SS substrate. In addition, the annealed Ge has a higher initial Coulombic efficiency of 90.8% than the as-deposited Ge of 81%. The improved performance of the annealed Ge can be attributed to the enhanced adhesion of annealed Ge film to SS substrate through interdiffusion at the SS/Ge interface due to the annealing post-treatment.

The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (–OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of –OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of –OH groups from the ambient. This process results in defect-free bonded wafers. NRF (Natl Research Foundation, S’pore) Published version