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We investigated the effect of photon irradiation with various energies on the gate bias instability of indium–gallium–zinc oxide transistors. The illumination of red and green light on the transistor caused positive threshold voltage (Vth) shifts of 0.23 V and 0.18 V, respectively, while it did not affect the Vth value in blue light after a positive bias stress. However, the stability of transistors was deteriorated with increasing photon energy after a negative bias stress: negative Vth shifts for red (−0.23 V) and blue light (−3.7 V). This difference can be explained by the compensation effect of the electron carrier trapping and the creation of meta-stable donors via photon excitation.

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

The amorphous oxide thin-film transistor (TFT)-oriented simulator [subgap Density of states (DOS)-based Amorphous Oxide TFT Simulator (DeAOTS)] is proposed, implemented, and demonstrated for amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs. It only consists of parameters having their physical meanings and is supplied with concrete techniques for parameter extraction. Among the physical parameters, the acceptor-like DOS gA(E) was experimentally extracted using the multifrequency C-V technique, whereas the donor-like DOS gD(E) and the doping concentration ND were extracted using numerical iterations. The simulation result reproduces the DOS and thin-film-thickness-dependence of dc I-V characteristics very well. Compared with the previously reported a-Si TFT models, the proposed DeAOTS model not only reflects the strong VGS dependence of the effective mobility (μeff) but also clarifies the relations between process-controlled DOS parameters and dc I- V characteristics based on experimentally extracted DOS parameters. Also, it sufficiently takes into account the peculiar situation of amorphous oxide TFTs where the free-carrier charge can be larger than the localized one out of the total induced charge. Moreover, it reproduces the measured electrical characteristics within the wide range of VGS/VDS with a single equation, not distinguishing the operation regions such as the subthreshold, linear, and saturation regimes.

An effective stacked memory concept utilizing all-oxide-based device components for future high-density nonvolatile stacked structure data storage is developed. GaInZnO (GIZO) thin-film transistors, grown at room temperature, are integrated with one-diode (CuO/InZnO)–one-resistor (NiO) (1D–1R) structure oxide storage node elements, fabricated at room temperature. The low growth temperatures and fabrication methods introduced in this paper allow the demonstration of a stackable memory array as well as integrated device characteristics. Benefits provided by low-temperature processes are demonstrated by fabrication of working devices over glass substrates. Here, the device characteristics of each individual component as well as the characteristics of a combined select transistor with a 1D–1R cell are reported. X-ray photoelectron spectroscopy analysis of a NiO resistance layer deposited by sputter and atomic layer deposition confirms the importance of metallic Ni content in NiO for bi-stable resistance switching. The GIZO transistor shows a field-effect mobility of 30 cm2 V−1 s−1, a Vth of +1.2 V, and a drain current on/off ratio of up to 108, while the CuO/InZnO heterojunction oxide diode has forward current densities of 2 × 104 A cm−2. Both of these materials show the performance of state-of-the-art oxide devices.

A technique for extracting the acceptorlike density of states (DOS) of n-channel amorphous GaInZnO (a-GIZO) thin-film transistors based on the combination of subbandgap optical charge pumping and C-V characteristics is proposed. While the energy level is scanned by the photon energy and the gate voltage sweep, its density is extracted from the optical response of C-V characteristics. The extracted DOS shows the superposition of the exponential tail states and the Gaussian deep states (N TA=2times1018 eV-1ldrcm-3, N DA=4times1015 eV-1ldrcm-3, kT TA=0.085 eV, kT DA=0.5 eV , E O=1 eV). The TCAD simulation results incorporated by the extracted DOS show good agreements with the measured transfer and output characteristics of a-GIZO thin-film transistors with a single set of process-controlled parameters.

Currently, both high-density 3-D stacking nonvolatile (NV) memory and embedded NV memory in advanced systems on panel (SOPs) urgently demand the assistance of new and functional transition metal-oxide materials. This is to overcome serious fabrication issues encountered in the use of conventional Si or poly-crystalline Si materials, as well as to increase storage density with lower process cost. This paper reports the fully functional NV memory structure operated by an ionic amorphous oxide semiconductor with a wide energy band gap (> 3.0 eV) in a Ga2O3-In2O3-ZnO (GIZO) system under low process temperature (< 400degC) while being combined with various metal-oxide materials of Al2O3, GIZO, and Al2O3 as the electron charge's tunneling, storage, and blocking layers, respectively. The different methods of memory programs and, especially, the unique erase characteristics caused by a much wider band gap than Si were intensively being investigated, and as a result, excellent electrical results of a large program/erase window over 3.8 V at a pulse time of 10 ms are achieved.

Amorphous gallium-indium-zinc-oxide (GIZO) thin film transistors with short channels of 50 nm were successfully fabricated by e-beam lithographic patterning. The GIZO thin film transistors showed a high mobility of 8.2 cm2/Vldrs with on-to-off current ratios up to 106. Excellent short channel characteristics were also obtained with a small shift of the threshold voltages and no degradation of subthreshold slopes as VDS increased, even with short channel lengths of less than 100 nm. These promising results indicate that the GIZO thin film transistors could be a candidate for selection transistors in 3-D cross point stacking memory.

In this letter, we present a comparative study of the low-frequency noise behavior of single-layer InGaZnO and bilayer InZnO-InGaZnO thin-film transistors (TFTs). The normalized noise for the bilayer oxide TFT is three times lower than that for the single-layer oxide TFT, mainly due to the higher mobility of the thin interfacial InZnO layer. The carrier number fluctuation is the dominant low-frequency noise mechanism in both devices. The use of a high-mobility bilayer oxide TFT with scaled gate length is still valid for reducing low-frequency noise.

In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit of a plot of the reciprocal of channel resistance versus gate voltage yields a threshold voltage of 3.5 V and a field-effect mobility of about 13.5 cm2/Vldrs. Furthermore, in a-GIZO TFTs, most of the current flows in the distance range of 0-0.5 mum from the channel edge and shorter than that in a-Si:H TFTs. Moreover, unlike a-Si:H TFTs, a-GIZO TFTs did not show an intersection point, because they did not contain a highly doped ohmic (n+) layer below the source/drain electrodes.

We have studied the microwave properties of the Josephson junction array by measurement of Josephson self-radiation power and Shapiro-steps. The serial–parallel and parallel Josephson junction arrays were prepared with and without additional inductive coupling lines. The maximum detected power of 22 GHz from the serial–parallel array is about 25 pW and its peak point revealed a good quality of frequency-locking and exactly satisfied the Josephson voltage–frequency relationship. Although the parallel array has similar physical properties of average critical current and normal resistance of Josephson junctions to serial–parallel array, the maximum detected power is only about several tens of fW. The received power of serial–parallel array is higher than that of the parallel array for the same intensity of irradiation power.

We have demonstrated fully integrated 64-kb magnetoresistive random access memory (MRAM) using 0.24-/spl mu/m CMOS technology and discussed some key issues in process integration. Optimal tunneling magnetoresistive (TMR) properties of MRAM bits (37% of TMR ratio and 5-10 k/spl Omega//spl middot//spl mu/m/sup 2/ of RA) were obtained mainly by the control of bottom electrode roughness, and electrical shorting was avoided by some commercialized wet solutions. In viewpoint of process integration, excellent TMR properties of magnetic tunnel junction (MTJ) fresh films and prevention of their degradation in post patterning process are two crucial factors, and especially, electrical shorting requires some careful control.

A temperature-dependent mobility model in amorphous oxide semiconductor (AOS) thin film transistors (TFTs) extracted from measurements of source-drain terminal currents at different gate voltages and temperatures is presented. At low gate voltages, trap-limited conduction prevails for a broad range of temperatures, whereas variable range hopping becomes dominant at lower temperatures. At high gate voltages and for all temperatures, percolation conduction comes into the picture. In all cases, the temperature-dependent mobility model obeys a universal power law as a function of gate voltage.

We proposed a novel photo sensor architecture utilizing transparent amorphous oxide TFT as both switching and sensor elements. The optimized triple layered TFT reveals negligible V th , and photo current distributions with various device dimensions and aging time, which provides the solution to a workable transparent oxide sensor in terms of manufacturability and scalability. In addition, the operation principle of an oxide sensor TFT proposed in this paper allows for us to realize high performance (>150Hz) sensor array.

A novel amorphous oxide TFT Enhancement/Depletion (E/D) inverter through uni-/bi-layer channel hybrid integration with conventional process is demonstrated. The device's threshold voltages (V th ) is strictly controlled and the fabrication technique is specially designed. Comparing to the reported high speed bootstrapped inverter, the output swing, switching voltage gain and noise margin of E/D inverter are greatly improved and only the ring oscillator's speed is slightly degraded while with a small supply voltage of 5V.

High reliable bottom gate amorphous gallium indium zinc oxide (a-GIZO) thin-film transistors (TFTs) have been fabricated by using the double active layers. Top and bottom layers were CuGaInZnO (CGIZO) and GIZO, respectively. When the plasma-enhanced processes were introduced during fabrication of the TFTs, the TFT with a-GIZO single active layer did not exhibit electrically reliable performance due to forming the conducting surface layer from the plasma damages. The double-active-layer TFT with a CGIZO layer had the reliable performance (μ FE of 5.1 cm 2 /V s, V th of 3.25 V, subthreshold gate swing value of 0.68 V/decade, I off of 3.8 X 10 -12 A) even under the same processes. This suggested that the Cu atom of CGIZO layer suppressed the carrier concentration during plasma-enhanced processes. The TFTs with double active layer showed excellent stability, which has the threshold voltage shift of

The damage of an amorphous Ga 2 O 3 -In 2 O 3 -ZnO (a-GIZO) thin-film transistor (TFT) due to dry etching was removed by wet-cleaning treatment and characterized in terms of electrical performance. The damaged channel layer by dry etch had lower chemical bonding energy than that of the as-deposited layer due to physical bombardment. It seems to be oxygen deficient and to have a reduction of metal cation. The existence of a damaged layer in the a-GIZO TFT tends to significantly deteriorate threshold voltage, subthreshold swing, and off-current. With the wet-cleaning treatment, however, the damaged layer was successfully removed, thereby revealing significantly recovered electrical performances. X-ray photoelectron spectroscopy, Auger electron spectroscopy, and transmission electron spectroscopy analysis support the evidences such as channel-layer composition, chemical bonding structure, and cross structure.

We fabricated gallium-indium-zinc oxide (GIZO) thin film transistors (TFTs) having a double-gated (DG) structure and studied the back gate effect on device performance. DG GIZO TFTs showed better threshold voltage (Vth), swing factor (S), and on/off current than those with a single gate. With the variation in back gate bias, the device performance significantly changes due to the modification of field distribution near the GIZO channel. It is believed that our DG structure is an effective way to improve the performance of GIZO oxide transistors and suppress the formation of an accumulation layer at the back surface.

Linear astigmatism of a confocal off-axis reflective imaging system when the object plane is tilted and located at a finite distance from the imaging system is derived. We show that linear astigmatism can be eliminated by proper configuration of the parent mirror axes in confocal off-axis two-mirror systems. The tilt angle of the image plane is also derived. The developed theory is verified by ray-tracing analysis of an example system.

We have fully integrated a 64 Kb MRAM with 0.24 /spl mu/m-CMOS technology. A new sensing scheme employing a separated half-current source is adopted for the reference bit line to increase the sensing signal. To reduce cell resistance, a Co salicidation process is applied to transistor formation. In key fabrication processes, the roughness of the buffer layer, on which the MTJs are stacked, is reduced by using Ru on the TiN bottom electrode, and magnetic disturbance is avoided by depositing TiN hard masks on the MTJ under low-power and low-temperature conditions. The tunneling barrier micro-bridge due to the attachment of by-products during etching is completely eliminated by adopting a 2-step MTJ etch with an introduced capping oxide layer. Consequently, MR values of >30% are found in more than 90% of chips.