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The low-frequency (LF) noise characterization of Si0.7Ge0.3 pFinFETs and transistors’ performance were analyzed for different NH3 post deposition annealing (PDA) temperatures. The flicker noise of these pFinFETs is dominated by carrier number fluctuations at low and intermediate drain currents. At high gate overdrive, the voltage noise Svg increases dramatically and the effect of the access resistance cannot be ignored. By analyzing the input-referred voltage noise power spectral density(PSD) at flat band voltage ( Svgfb ), we will demonstrate that nitridation of the high- κ layer at 650 °C yields the best quality gate-stack and also results in the highest mobility. While NH3 PDA temperature above 650 °C may introduce more hydrogen at the oxide layer and at the interface, hydrogen can induce hole traps and interface traps that degrade the quality of the gate-stack and reduce the mobility.

The energy distributions of electrons in gate-all-around (GAA) Si MOSFETs are analyzed using full-band 3-D Monte Carlo (MC) simulations. Excellent agreement is obtained with experimental current–voltage characteristics. For these 24-nm gate length devices, the electron distribution features a smeared energy peak with an extended tail. This extension of the tail results primarily from the Coulomb scattering within the channel. A fraction of electrons that enter the drain retains their energy, resulting in an out-of-equilibrium distribution in the drain region. The simulated density and average energy of the hot electrons correlate well with experimentally observed device degradation. We propose that the interaction of high-energy electrons with hydrogen-passivated phosphorus dopant complexes within the drain may provide an additional pathway for interface-trap formation in these devices.

Peak transient currents due to pulsed-laser or heavy-ion irradiation of Ge $p$ MOS FinFETs are nearly independent of gate bias. This is because the prompt photocurrent is due primarily to a transient source–drain shunt. In contrast, long-term diffusion charge collection is strongly gate-bias dependent. This bias dependence results from hole injection from the source in response to the transient increase in electron concentration in the channel. The transients measured at the source terminal change polarity when the strike location moves from the source to the drain, but this effect does not occur for the transients measured at the drain terminal. Charge collection mechanisms are studied using TCAD simulations.

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. We then performed 400 virtual experiments comprising seven sources of process variation. Using this virtual fabrication technique, we were able to identify a minimum gate-to-source/drain spacer thickness for a high-temperature post-EPI rapid thermal anneal (RTA) anneal process that avoided device subthreshold slope penalties. The model allowed us to determine the optimal Si recess depth target and process window prior to source/drain epitaxy. We obtained these results by reviewing device performance as a function of statistical process sensitivity and highlighting key process parameters requiring variation control. These experiments would have been impractical to perform in an actual fab, due to the time, cost, and equipment requirements of running 400 fab-based process variation experiments for each process parameter. This methodology can be used to avoid wafer-based testing during early technology development.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

In this work, we have investigated the influence of ${V}_{\text {t}}$ extraction procedure on overall ${V}_{\text {t}}$ variability of sub-10 nm ${W}_{\text {fin}}$ FinFETs. Using six different ${V}_{\text {t}}$ extraction techniques, we have experimentally demonstrated that the ${V}_{\text {t}}$ variability is independent of ${V}_{\text {t}}$ extraction procedure (unlike reported earlier). Furthermore, through systematic evaluation on commonly used ${V}_{\text {t}}$ extraction techniques, the physics behind this anomalous behavior is investigated. It is shown that the significant variation in metal gate work-function and gate dielectric charges in advanced CMOS nodes is mainly responsible for this behavior. This claim is further validated for FinFETs with deeply scaled fin-width and effective oxide thickness (EOT).

In this work, IGZO device integration is reported leveraging our 300mm-fab facilities. Our objective is mainly to gain insights into the process and material elements which drive the control of the performance parameters of IGZO nFETs. To control the final doping of the IGZO channel, it is well reported in literature that a final oxygen anneal can be applied to passivate the oxygen vacancies which are formed during the device fabrication. This technique is also used in our 300mm flow. As it might be expected, in front gate IGZO nFETs, the passivation efficiency is limited by the presence of the top metal gate stack. Therefore, it seems important to limit the formation of the oxygen vacancies during the deposition of the gate dielectrics. Three oxides were studied: SiO2, Al2O3 and HfO2 on top of the IGZO channel. After oxygen annealing, only PECVD-SiO2 shows a large recovery while for Al2O3 and HfO2, it remains low. This result challenges the implementation of conventional water-based high-K materials in gate first IGZO integration. Contrary to the use of undoped IGZO in the channel for IOFF control, contacts can rely on maximizing the oxygen vacancies to increase the dopant concentration in the S/D regions. When not done locally, it could be an extra source of variability. This doping is made through oxygen scavenging from IGZO by a thin metal contact barrier. Low specific contact resistivity down to 1x107 Ohm.cm2 is demonstrated when Ti is thinner than 5nm. With thicker barrier, the formation of TiO2 and specific alloys is taking place at the IGZO/Contact barrier interface. This is both confirmed by ab initio simulations and by advanced physical characterization techniques. Regarding the channel, X-ray diffraction techniques are extensively here since this is a nondestructive in-fab technique that provides detailed information about the crystallographic structure of the IGZO material. We show a typical spectrum where clear peaks/humps are seen and attributed to: 1. amorphous IGZO, 2. CAAC-IGZO and 3. a previously not reported, to the best of our knowledge, phase called here s-IGZO. The s-phase is only formed under certain conditions of power, temperature and oxygen flow during material deposition. Thick IGZO (>12nm) back-gated nFETs with active layers submitted to final O2 anneal are used to study the different phases of IGZO and their electrical impact on device parameters. In this configuration, the carrier transport preferentially occurs in the bottom half of the IGZO channel while the top half (SiO2/IGZO interface) mostly drives the electrostatic control of BG transistors. The amorphous IGZO has much reduced spread in VTH-ON and higher ID,LIN (~mobility) than that of CAAC-IGZO. Reliability tests have also been carried out to compare the two phases and the results show the existence of two competing PBTI degradation mechanisms for CAAC-IGZO. It is important to report the degradation over time and different VG stress because a cut line at a specific value could have shown no BTI degradation of CAAC-IGZO and then attributing an unfair benefit of this phase over the a-IGZO phase. Combining these findings to some other results where the sheet resistance of IGZO under hydrogen exposure depends on the phases, we can reasonably conclude that CAAC owns different doping levels in comparison to a-IGZO. Based on the previous learning about n-type dopant location in IGZO, we show that the performance of transistors keeps increasing when the channel length is reduced and scales with the channel width. A measure of the VTH-ON variation has been performed at the 300mm wafer scale from long to ~120nm LCH and down to 200nm WCH dimensions. The figure in attachement shows the Id-Vg curves of >100 Back Gated IGZO-nFETs with no failed devices detected. The standard variation of the VTH-ON across LCH and WCH is often less than 40mV with a minimum of 20mV. In conclusion, we have demonstrated in this study scaled IGZO nFETs with excellent VTH_ON control using an industry compatible 300mm process flow. This has been achieved thanks to a careful mapping of n-type doping in the three dimensions of the IGZO channel. While semi-crystalline IGZO seems to be more robust against hydrogen than that of amorphous-IGZO, a new IGZO phase is found to help boost ION at short channel. The demonstration of back-gate IGZO nFETs with low variability and relatively high drive will benefit to the top-gate architecture development. This will provide new opportunities for the IGZO-based devices like an “on-the-fly” VTH setting for the performance control of advanced applications. Figure 1

The correct and flawless functioning of medical devices is of utmost importance for patients and the medical sector. Although medical device manufacturers utilize various protocols and procedures during the development and production of medical devices, the integrated circuits are usually manufactured by other parties. During the manufacture of the semiconductors utilized in the integrated circuits, the performance of the components can vary from batch to batch and even samples within the same batch can have different performance characteristics. For applications in life critical applications the selection of the most fit for purpose components is vital. In this paper, we propose a novel method for the semiconductor industry to verify the quality of transistors. The I-V graphs of the components are evaluated by multiple Convolutional Neural Networks (CNN) using visual data similar to expert evaluation, then these Machine Learning (ML) architectures utilize a multi model ensemble technique where one architecture providing a negative output will overrule the vote of the other architectures is utilized to assure very stringent quality control. Our method is tested on CMOS transistors and the results are comparable to those of experts with 10 years of experience in the industry.

Pulsed, laser-induced, single-event current measurements on silicon-on-insulator (SOI) FinFETs at subbandgap wavelength (1260 nm) are affected by the polarization of the laser light used in the experimental testing setup. Such polarization dependence is not observed during pulsed laser, single-event effects testing on large-area silicon diodes, suggesting that polarization dependence arises due to the presence of the nanoscale fin. Plasmonic enhancement is proposed as a likely mechanism for the polarization effects due to the metal/dielectric interfaces in the fin region. The observed polarization dependence has ramifications for collection and interpretation of data acquired by pulsed laser testing. Device orientation of FinFETs and other nanoscale devices during pulsed laser testing should be considered in order to ensure consistent testing conditions and reproducible measurement results across multiple measurement campaigns.

This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high- ${k}$ last process. SiO2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Si x )Ge1- x O y , which is, compared to a pure SiO2, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced ${D}_{{\text {IT}}}$ , and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum ${V}_{{\text {OV}}}$ of 0.13 V, the best GmSAT/SSSAT of 5.4 is achieved, which is today’s record value among the sub-100-nm- ${L}_{g}$ n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack.

In this article, we explore different device and standard cell architectures for scaling the Germanium fin field-effect transistor (FinFET) and nanosheet (NS) at the sub-5-nm node. It is demonstrated that the Germanium device provides approximately 70% improvement in drive current and $3.4\times $ less device resistance. The main concern for Germanium devices remains the high leakage current due to the gate-induced drain leakage, which limits their usage to high-speed applications. Overall, Germanium devices require fewer boosters than silicon to scale beyond the 5-nm node. Contact resistivity is found to be a critical knob for Germanium and it can be relaxed to 3e $- 9\,\,\Omega $ -cm2 to meet the power and performance targets for the sub-5-nm node. Moving to the NS helps in relaxing this constraint further.

We evaluate the total ionizing dose (TID) responses of InGaAs nMOS FinFETs with different gate lengths irradiated with 10-keV X-rays under different gate biases. The largest degradation after irradiation occurs at $V_{\mathrm {G}} = -1$ V. Radiation-induced trapped positive charge dominates the TID response of InGaAs FinFET transistors, consistent with previous results for InGaAs multifin capacitors. Shorter gate-length devices show larger radiation-induced charge trapping than longer gate-length devices, most likely due to the electrostatic effects of trapped charge in the surrounding SiO2 isolation and SiO2/Si3N4 spacer oxides. The 1/ $f$ noise measurements indicate a high trap density and a nonuniform defect-energy distribution, consistent with a strong variation of effective border-trap density with surface potential.

The implementation of a barrier potential layer underneath the channel region, well known as Ground Plane (GP) implantation, and its influence on the performance of relaxed germanium pFinFET devices is investigated in this manuscript. This study aims to explain the fin width dependence of the threshold voltage from experimental data and evaluates the ground plane doping concentration and its depth influence on relaxed p-type channel germanium FinFET parameters, as threshold voltage, transconductance and subthreshold swing, through Technology Computer-Aided Design (TCAD) numerical simulations. The threshold voltage variation reaches up to 80 mV from the narrowest device to the widest one, considering the studied range of ground plane doping concentration. Concerning the subthreshold swing parameter, neither the GP doping concentration, nor its depth play a significant role since the electrostatic coupling is predominant.

The aggressive downscaling of FET devices (FinFET, NanowireFET, NanosheetFET, to name a few) in past years has put a great emphasis on the need to come up with properly calibrated process and device simulation tools to predict performances, suggest processing options and even understand failure mechanisms. As their modeling is complex with multiple calibration parameters, adequate two- and three-dimensional characterization techniques have been identified as a necessity to achieve an accurate modeling and calibration of the complex physical mechanisms for scaled devices. In such scaled devices even the smallest variations of the structure dimensions (i.e., width or length, local interconnect or spacer, source/drain epi volumes, etc.), carrier distribution and/or activation rate can cause significant variations in the electrical properties.

Reliability and variability-aware simulations of logic cells are essential to correctly analyze and predict the performance of upcoming technologies. A simulation flow for DTCO is presented here, which combines the accuracy of TCAD with the performance of SPICE - utilizing parasitic extractions, the impedance field method for variations, and the compact-physics simulator Comphy for reliability. Good agreement with experimental RO performance of iN14 is demonstrated and projections to N3 FinFET and nanosheet technologies are made.

For many years traditional 193i lithography has been extended to the next technology node by means of multi-patterning techniques. However recently such a 193i technology became challenging and expensive to push beyond the technology node for complex features that can be tackled in a simpler manner by the Extreme UltraViolet Lithography (EUVL) technology. Nowadays, EUVL is part of the high-volume manufacturing device landscape and it has reached a critical decision point where one can push further the single print on 0.33NA full field scanner or move to a EUV double patterning technology with more relaxed pitches to overcome current 0.33NA stochastic limits. In this work we have selected the 28nm pitch dense line-space (P28) as critical decision check point. We have looked at the 0.33NA EUV single print because it is more cost effective than 0.33NA EUV double patterning. In addition, we have conducted a process feasibility study as P28 in single print is close to the resolution limit of the 0.33NA EUV full field scanner. We present the process results on 28nm dense line-space patterning by using Inpria’s metal-oxide (MOx) EUV resist. We discuss the lithographic and etching process challenges by looking at resist sensitivity, unbiased line edge roughness (LER) and nano patterning failures after etching (AE), using broad band plasma (BBP) and e-beam (EB) defectivity inspection tools. To get further understanding on the P28 single patterning capability we have integrated the developed EUV MOx process in a relevant iN7 technology test vehicle by developing a full P28 metallization module with ruthenium. In such a way we were able to carry on electrical tests on metallized serpentine, fork-fork and tip-to-tip structures designed with a purpose of enabling further learning on pattern failures through electrical measurements. Finally, we conclude by showing the readiness of P28 single exposure using Inpria’s MOx process on a 0.33NA EUV full field scanner.

Gate-all-around (GAA) silicon nanowire (NW) CMOS transistors demonstrate outstanding total-ionizing-dose (TID) tolerance due to the ultrascaled gate dielectric thickness, enhanced electrostatic gate control, and suppression of parasitic leakage current paths. nFETs and pFETs show similar TID responses, making the GAA NW technology an excellent candidate for CMOS IC applications in high-radiation environments. The slight degradation of the threshold voltage suggests limited charge buildup in the gate dielectrics. However, low-frequency noise and random telegraph noise measurements show the importance of change in trap configurations in both the near-interfacial SiO2 and HfO2 dielectric layers to the radiation response and reliability of GAA NW devices. These traps are most likely due to oxygen vacancies and/or hydrogen complexes.

We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal V th reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10-19A/µm).

This paper describes our recent research progress on high-mobility Ge-channel n/pFETs. Gate stack, junction and contact are the key challenging components of Ge n/pFETs. Through the improvement of those unit modules, the electrical performance and reliability of Ge FinFET and gate-all-around (GAA) nanowire (NW) pFETs have been improved. Remaining technical challenges for the realization of high performance and reliable Ge n/pFETs will be discussed.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

This paper shows the importance of oxygen control at the SiGe fin surface and within the gate stack. Optimized SiN liners are required to protect SiGe fins from oxidation during a flowable CVD (FCVD) densification anneal. Suppression of oxygen diffusion or scavenging from GeO via metal electrode is essential to achieve a low-D IT SiGe gate stack. By replacing HfO 2 with other dielectrics offering lower oxygen diffusivity, impact of metal electrode deposition process as well as the HfO 2 nitridation is corroborated to be related to the oxygen diffusivity. Finally, when using an embedded B-doped Si 0.4 Ge 0.6 S/D, higher channel strain in Si 0. 7 Ge 0.3 than in Si p-fins is obtained as predicted by TCAD.

Top tier devices in a 3D sequential integration are optimized using a low temperature process flow $( . Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar $\mathrm{I}_{\mathrm{on}}-\mathrm{I}_{\mathrm{off}}$ device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion.

Low-frequency noise is used to estimate the quality of the gate stack for planar Ge nMOSFETs with different effective work function metals and cap layers. It is shown that replacing TiN by a TiAl-based metal gate will induce a significant decline of the threshold voltage ${V}_{T}$ and noise power spectral density, indicating the introduction of Al will induce an advantageous effect on the trap density in the underlying HfO2. Meanwhile, the application of a LaO x cap tends to reduce ${V}_{T}$ and the trap density in the gate oxide, which could attribute to the La in-diffusion in the gate stack. The 1/f noise analysis shows that the noise could mainly be associated with number fluctuations and correlated mobility fluctuations.

In this work, we have studied the effect of threshold voltage $(\mathbf{V}_{t})$ extraction methods on in-wafer variability of sub-10nm fin-width FinFETs. Using six different $\mathbf{V}_{t}$ extraction techniques, it is experimentally demonstrated that the $\mathbf{V}_{t}$ variability is independent of the extraction technique. The significant variation in work-function and oxide-charges compared to mobility and series-resistance is shown to be the reason behind these observations. It is also shown that the inferences drawn from this work will hold true even for future CMOS nodes.

This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the $Q$ factor is increased to 25 as compared to our previous work, $I_{ \mathrm{\scriptscriptstyle ON}} = \textsf {500}~\mu \text{A}/ \mu \text{m}$ at $I_{ \mathrm{\scriptscriptstyle OFF}} = \textsf {100}$ nA/ $\mu \text{m}$ is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB.

In this work, we discuss how the insertion of a LaSiOx layer in between an in-house IL passivation layer and the high-k has moved the III-V gate stack into the target window for future technology nodes. The insertion of this LaSiOx layer in the gate stack has reduced the Dit and Nbt below the target level of 5×1011 /eV.cm2 and 3×1010 /cm2 (target at 10 years operation: ΔVfb

In this work, we have studied gate length (Lgate) scalability of Si0.55Ge0.45 Implant Free Quantum Well (IFQW) pFET with raised and embedded Si0.75Ge0.25 source/drain structures. Although embedded SiGe device shows higher Idsat which can be attributed to thinner Tinv (more scavenging of High-k interfacial layer), raised SiGe device has better short channel control than embedded SiGe device thanks to shallower junction depth. Raised SiGe device can scale down Lgate by 4 nm compared to embedded SiGe device while maintaining identical Ioff. This results in superior intrinsic delay in raised SiGe device.

In this letter, evidence of plasma-induced damage (PID) occurring in ${p}$ -type FinFET Germanium devices due to BEOL processing is reported. The ability of high-pressure anneal (HPA) (20 min at 450° with 20 atm pressure) to cure this damage is investigated by comparing different ambients (hydrogen and deuterium) with the reference case without HPA. The degradation and partial recovery during anneal of the threshold voltage, the transconductance, and the subthreshold slope are observed. Further, bias temperature instability stress is employed to evaluate the impact of PID in terms of reliability. It is found that the damage observed in the dc and reliability measurements is more efficiently cured by the H2 ambient than the D2 ambient.

We use capacitance–frequency ( $C$ – $f$ ) measurements to provide lower bound estimates of border-trap densities in multifin MOS capacitors with high-K dielectrics built in Ge and InGaAs fin field effect transistor (FinFET) technologies before and after X-ray irradiation. The $C$ – $f$ method is illustrated for SiO2-based planar MOS capacitors and compared with high-frequency capacitance–voltage measurements. Lower effective border-trap densities are found before and after irradiation for multifin capacitors built in a strained Ge $p$ MOS FinFET technology than for similar devices built using an early-developmental stage InGaAs MOS technology. These results show the utility of $C$ – $f$ measurements in characterizing defect densities in MOS capacitors, particularly when large border-trap densities exist.

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions ( $L_{G}= 40$ nm) published to date. Electrostatics and off-state leakage are maintained down to the shortest gate lengths studied, showing drain-induced barrier lowering of 30 mV/V and sub-20 nA/ $\mu \text{m}~I_{\mathrm{\scriptscriptstyle off}}$ at $V_{\mathrm {{\text {DD}}}}= -0.5$ V and $L_{G}= 40$ nm. The short-channel device subthreshold slope SS and performance can be further improved by use of high-pressure annealing in hydrogen, yielding the best SSLIN and SSSAT of 71 and 76 mV/dec reported so far for any $L_{G}= 40$ -nm Ge pMOS channel device.

SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology.

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained.

We demonstrate multiple ways to reduce the D IT of Si-cap-free low-Ge-content (25-30%) SiGe gate stack. The D IT is reduced by i) Ge oxide scavenging via Ge condensation or by the work function metal (WFM), ii) nitridation of gate dielectrics and iii) optimized high-pressure anneal (HPA). A moderate nitridation of the interface layer (IL) is beneficial in EOT and D IT reduction, while nitridation of the HfO 2 dramatically reduces D IT by negating an ALD TiN-induced D IT increase. The optimized gate stack is evaluated in 8-nm-wide strained Si 0 7 Ge 0 3 pFinFETs integrated on 300 mm Si wafers, for which a 35% improvement in high-field mobility is demonstrated as compared to Si pFinFET counterparts.

A systematic methodology to segregate different variability sources from electrical measurements, in sub-10nm W fin FinFETs, is proposed. The threshold voltage variation, coming from gate-metal work-function and oxide charge variations, is shown to be the major contributor to in-wafer variability. The contribution of FER, GER and RDF to V t variability is negligible. TiTaN, a new work function metal (WFM) for the metal gate-stack, is introduced and it provides ~37% less total and ~27% less random variability.