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The electrothermal behavior of gallium nitride (GaN) HEMTs has been simulated by using a hybrid approach in which the problem is solved by coupling together an effective model (for the electrical part) and a 3-D finite element model (for the thermal part). The effective model relies on the estimation of the channel current at different temperatures in the absence of thermal gradients. This regime occurs in real devices only during the very initial stage of bias pulses, when self-heating effects are not yet developed, for time intervals shorter than 1 ns. Virtual output electrical characteristic, in which self-heating effects are negligible, have been derived from pulsed measurements of the electrical output characteristics and electrothermal transient simulations. The maximum temperature because of self-heating evaluated by using the virtual output characteristic are substantially higher than those obtained using the short time-pulsed measurements directly. The results have been validated by a comparison with temperature measurements obtained using Raman thermography. This approach has proven to be numerically very efficient and fast, allowing the analysis of realistic complex structures and circuits.

In this chapter the historical evolution over more than 30 years of pulsed laser annealing for semiconductor processing has been reviewed. After describing the main physical aspects of the laser annealing process, some of the more relevant key technologies, i.e., excimer lasers and optical systems to manipulate the laser beam, are discussed. The chapter is then focused on two major applications of semiconductor industry: the first dealing with the amorphous silicon transformation into polycrystalline silicon for the thin-film transistor (TFT) technology and the second aiming to the dopant activation in CMOS technology for both logic and power MOS applications. In the case of polysilicon technology, the advantages offered by excimer laser annealing have guaranteed the establishment of industrial production of displays based on polysilicon TFTs active matrix. In the case of CMOS applications, excimer laser annealing in Si melting regime was shown to provide a number of advantages with respect to other annealing methods, but industrial production has not yet started due to a number of issues. Several techniques have been proposed to solve many of these issues, resulting, however, in an increased complexity of the process. These technological achievements have paved the way to further developments and renewed interest in excimer laser annealing.

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μFE> 1 cm2V−1s−1) and excellent stability under gate bias stress (bias stress Vds = 0V). However, after prolonged bias stress performed at high drain voltage, Vds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high Vds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.

The electrical properties of dinaphtho [2,3-b:2′ ,3′ -f]thieno[3,2-b]thiophene (DNTT) based organic thin film transistors (DNTT-TFTs) were investigated in detail under dark and various light illumination conditions with different channel lengths. We have exploited the experimental curves current–voltage of our TFT to extract electrical parameters such us mobility, threshold voltage, sub-threshold voltage and trapped density in dark and under illumination. By using an analytical model, we are able to reproduce very accurately the output and transfer characteristics with a joint analysis of the L = 100 μm and L = 500 μm electrical characteristics, the dependence of the contact resistance (Rc) upon the illumination conditions has been extracted. The used model gives a good agreement between the measured current–voltage characteristics of the DNTT-TFTs and those modeled in all measurement conditions (in dark and under illumination).

Organic material deposition by gravure printing is a promising pathway for the realization of large area flexible electronic devices. Nevertheless, in order to achieve high performance it is required to improve the electronic ink printability, operating on the fluid dynamic mechanisms involved during the process. In this work, this issue has been faced working on ink characteristics for a conductive and a dielectric material. The suitable ink features have been defined studying the influence on the printability of the different forces that act in the fluid during the printing process, using an experimental approach. Properly defined ink formulations have been printed, considering different shapes and dimensions of the cells on the gravure cliche to fit the ink features. The printing outcomes have been compared and analysed through the evaluation of several significant fluid dynamic parameters and the rheological characterization of the materials. Finally, exploiting the results of this study, high performance fully printed organic thin film transistors have been realized.

As one of the main expected advantages of organic electronics is the low cost, printing technologies are actively investigated for the fabrication of OTFTs. Techniques such as ink-jet or gravure printing frequently results in organic semiconductor (OSC) layers with low crystallinity and relatively low carrier mobility. Moreover, the minimal feature sizes attainable are often in the range of the tens of microns. Hence, the resulting carrier transit time (τ) in the channel of OTFTs can be of the order of tenth of milliseconds with associated cut off frequencies in AC regime in the range of few kilohertz [1]. Due to the large tolerances associated to printing processes, the layout of printed OTFTs often includes semiconductor regions whose dimensions are chosen prudently larger than the spacing existing between the source and drain contacts. The presence of the parasitic regions, that is negligible in DC operation, must be accounted in order to accurately reproduce the dynamic operation of these devices. Due to the relatively high value of τ, it is very likely that in practical applications organic circuits are operated with signals varying on a time scale of the same order or shorter than τ. Hence, the carriers in the device don’t have enough time to reach the distribution associated to stationary conditions and the OTFTs enter in non quasi static (NQS) regime of operation. The device response to large variation of its polarization (large signal, LS) becomes dependent on the delay times associated with the high value of τ. Moreover, in NQS regime the device effective admittance in small signal (SS) AC operation is found to be dependent upon the small signal frequency [2][3]. Hence, to successfully design electrical circuits employing printed OTFTs, it is necessary to develop compact models that are able to precisely reproduce not only the DC operation but also the LS and SS AC behavior of these devices. In this work, a large signal non quasi static (LS-NQS) compact model has been developed: the model is based on the current continuity equation that, in the case of a MOSFET transistor channel, can be cast as a partial differential equation (PDE) governing the carrier density distribution during time, Q(x,t), in a distributed RC transmission line. In order to solve this PDE, the space variable x is discretized by using a spline collocation approach: the PDE is transformed in a set of ordinary differential equations (ODE) in the time variable t, that can be solved numerically in a “SPICE-like” circuit simulation environment [4], [5]. The spline collocation approach allows to choose the number of splines (N) in which the device channels and the parasitic regions are split: by choosing an appropriate value for N it is possible to find the best compromise between computation accuracy and performance. NQS models have been already investigated and developed for crystalline silicon MOSFETs. The model presented in this work differs from the crystalline silicon counterparts in two major aspects: 1 – the equations accounting for the charge and current densities are based upon the variable range hopping (VRH) theory that is well suited for amorphous organic semiconductors[6]. 2 – the model takes into account the presence of parasitic regions by imposing appropriate boundary conditions on their extremities. The LS-NQS model has been implemented in Verilog-A and validated by simulating the electrical behavior of multi-fingered OTFTs, with staggered top-gate configuration, fabricated on PEN substrates by means of a fully printed process. The devices were characterized and simulated in DC, and SS AC operation. A common source amplifier circuit has been realized and measured in LS operation. As can be seen from fig. 1, the model reproduce perfectly the device behavior in LS operation. Moreover, the use of the model has permitted to gain several physical insights concerning the device operation. [1] J. S. Chang et al., IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 7, no. 1, pp. 7–26, Mar. 2017, doi: 10.1109/JETCAS.2017.2673863. [2] A. Valletta et al., IEEE Trans. Electron Devices, vol. 61, no. 12, pp. 4120–4127, Dec. 2014, doi: 10.1109/TED.2014.2364451. [3] J. Leise et al., IEEE Trans. Electron Devices, vol. 67, no. 11, pp. 4672–4676, Nov. 2020, doi: 10.1109/TED.2020.3018094 [4] A. Valletta et al. in 2016 46th European Solid-State Device Research Conference (ESSDERC), Lausanne, Switzerland, Sep. 2016, pp. 460–463, doi: 10.1109/ESSDERC.2016.7599685. [5] A. Valletta et al. in 2017 European Conference on Circuit Theory and Design (ECCTD), Catania, Sep. 2017, pp. 1–4, doi: 10.1109/ECCTD.2017.8093225. [6] F. Torricelli et al., IEEE Trans. Electron Devices, vol. 56, no. 1, pp. 20–30, Jan. 2009, doi: 10.1109/TED.2008.2007717. Figure 1

The technology based on organic devices and sensors is becoming attractive for a wide range of applications. Indeed, the intrinsic characteristics of the organic materials, as the low-temperature process, flexibility, lightweight, biocompatibility, and even biodegradability, make them the basis for devices for the emerging flexible plastic electronics. Among the different possible applications, the electro-optical properties of organic semiconductors can be exploited for the development of devices for photosensing [1], imaging array [2], and optical memory [3]. The wide number of organic materials with different absorption spectra allows the development of photosensors with large spectral sensitivity or tuned to specific wavelengths. In particular, organic phototransistors (OPTs) are particularly promising since they combine light detection, typical of the photodiodes (OPD), with the intrinsic signal amplification that increases the device sensitivity. The response of the OPTs to light irradiation was widely studied in the last years. The photons with energy above the optical gap generate excitons that can dissociate into free holes and electrons and, in p-type devices, the photo-generated electrons are trapped. Negative trapped charges induce the shift of the flat band voltage as well as the threshold voltage of the OPT resulting in the increase of the drain current [4]. The location and the nature of the defect states are still under investigation. Depending on the organic semiconductor, gate dielectric and device structure, the defects have been identified as interface states between semiconductor and insulators [2], defects into the semiconductors [3], defects induced by the diffusion of oxygen or moisture into the OSC [5]. Trapped charge near the source/drain electrodes can also reduce the injection contact barrier, increasing the drain current [6]. In any case, photo-induced effects appear to be a quite general effect since they are observed in devices with different semiconductor molecules and different gate dielectric (both organic and inorganic). In this presentation, the different mechanisms will be reviewed and the photo-induced effects will be discussed for OTFTs with evaporated and solution-processed semiconductors and different device structures. The high stability of these devices under gate bias stress, allows to investigate in detail the effects induced by the light. Furthermore, this presentation will show the application of the electro-optical properties of the OTFTs to the development of radiation detectors based on Organic Photo Transistors (OPTs), made on flexible substrate, and coupled with plastic scintillators. The OPTs are based on organic semiconductor dinaphtho [2,3-b:2′,3′-f] thieno[3,2-b] thiophene (DNTT) and have Bottom Gate/Top contact multi-finger device structure in order to simplify the device coupling with scintillator and increase the device area. The channel length, L, and channel width, W, are 100 µm and 2 cm, respectively. The gate, source and drain, and the semiconductor layer (DNTT, 30 nm thick) are thermally evaporated through metal masks. Spin coated layers of Cytop are used as gate dielectric and passivation layer. Thanks to the high quality of the semiconductor and of the dielectric/semiconductor interface, the devices show good electrical characteristics, with field effect mobility of about 1 cm2/Vs, a threshold voltage of the order of -10 V and subthreshold voltage of about 1V/dec. Furthermore, the devices do not show hysteresis of the transfer characteristics and are quite stable under bias stress. The OPTs have been characterized by electrical and optical measurement in order to evaluate the figures of merit parameters of the photodetectors, such as the photo-switching speed, the responsivity, and the photocurrent on/off ratio (also indicated as photosensitivity). The measurements have been carried out under monochromatic light with λ= 450 nm (above the optical gap of the DNTT). At this wavelength, these OPTs are able to detect very low light intensity (of the order of few nW/cm2), with a responsivity of 0.25 A/W and sensitivity of 2x10-2. The OPTs are successfully coupled with siloxane based scintillator. This work is supported by INFN-CNS5 project "FIRE". [1] J. Huang et al., Adv. Mater. 2020, 32, 1906027 [2] Y. Chu et al., Adv. Sci. 2016, 3, 1500435 [3] K. Pei et al., Adv. Mater. 2018, 30, 1706647 [4] A. Pierre and A.C. Arias, Flex. Print. Electron 1 (2016) 043001 [5] R. Jia and e. al., Adv. Funct. Mater., vol. 29, p. 1905657, 2019. [6] X. Wang et al., J. Appl. Phys. 107, 024509 (2010).

We present a compact model for the DC and small signal AC analysis of Organic Thin Film Transistors (OTFTs). The DC part of the model assumes that the electrical current injected in the OTFT is limited by the presence of a metal/organic semiconductor junction that, at source, acts as a reverse biased Schottky junction. By including this junction, modeled as a reverse biased gated diode at source, the DC model is able to reproduce the scaling of the electrical characteristics even for short channel devices. The small signal AC part of the model uses a transmission line approach in order to compute the impedances of the channel and parasitic regions of the device. The overlap capacitances and the presence of non-ideal metal/organic semiconductor junctions are taken in account as well and the model can be easily adapted to different device geometries. The model is particularly well suited for printed devices, often realized with large process tolerances, since it takes into consideration the presence of parasitic regions and their effect on the AC operation. The model has been validated on printed OTFTs using a pentace-derivative as organic semiconductor with a quite peculiar device layout. It has been fully implemented in Verilog-A programming language.

This work introduces a compact DC model developed for organic thin film transistors (OTFTs) and its SPICE implementation. The model relies on a modified version of the gradual channel approximation that takes into account the contact effects, occurring at nonohmic metal/organic semiconductor junctions, modeling them as reverse biased Schottky diodes. The model also comprises channel length modulation and scalability of drain current with respect to channel length. To show the suitability of the model, we used it to design an inverter and a ring oscillator circuit. Furthermore, an experimental validation of the OTFTs has been done at the level of the single device as well as with a discrete-component setup based on two OTFTs connected into an inverter configuration. The experimental tests were based on OTFTs that use small molecules in binder matrix as an active layer. The experimental data on the fabricated devices have been found in good agreement with SPICE simulation results, paving the way to the use of the model and the device for the design of OTFT-based integrated circuits.

We studied, by 2D numerical simulations, the effects of poor semiconductor morphology near the source and drain contacts of BGBC-OTFTs. The variations of the electrical characteristics and of the path of the injected carriers in the transistor channel have been analyzed considering different defective regions, parameters (mobility, density of states) and contact thicknesses. The results showed that 100 nm wide defective regions can induce high contact resistance, resulting in large variation in the electrical characteristics. However, the typical S-shape in the low-Vds output characteristics is clearly observed only considering a combination of highly defected regions and Schottky barrier at the contacts. Furthermore, the simulations showed that most of the current is injected and extracted, at the source and drain contact, within a few nanometers from the semiconductor- dielectric interface. This explains the small influence of the contact thickness on the simulated electrical characteristics, at least for a contact thickness down to 10 nm.

Here, electron-transporting semiconducting organic channels made of N,N′-1H, 1H-perfluorobutyl dicyanoperylenecarboxydiimmide (PDIF-CN2) molecules were thermally evaporated on flexible polyethylene-naphtalate (PEN) plastic substrates equipped with gold (Au) electrodes. This multilayer structure represents the basic component for the fabrication of staggered top-gate n-type organic thin-film transistors (OTFTs) to be completed with the addition of a polymeric dielectric layer and an aluminum gate electrode. PEN substrate was treated with hexamethyldisilazane (HMDS) in order to make it more hydrophobic. Indeed, the hydrophobized surface of the plastic substrate was shown to induce a more ordered supramolecular structure of the semiconductor layer during the evaporation process. The hybrid organic/inorganic formally trilayer non-passivated OTFT structure was successfully profiled in a single run through ToF-SIMS depth profiling experiments with low energy cesium ions. High mass molecular fragment ions were obtained and used as indicators of interfaces, leading to an increase of information on molecular specificity. The HMDS surface modification was clearly detected and spatially located. Finally, a chemometric approach was also adopted to evaluate depth profiling data. In particular, principal component analysis (PCA) and K-means algorithm were tested as innovative method for the identification of molecular fragments useful for the OTFT multi-layer structure characterization and the determination of the number of OTFT layers, respectively.

Here, electron-transporting semiconducting organic channels made of N,N′-1H, 1H-perfluorobutyl dicyanoperylenecarboxydiimmide (PDIF-CN2) molecules were thermally evaporated on flexible polyethylene-naphtalate (PEN) plastic substrates equipped with gold (Au) electrodes. This multilayer structure represents the basic component for the fabrication of staggered top-gate n-type organic thin-film transistors (OTFTs) to be completed with the addition of a polymeric dielectric layer and an aluminum gate electrode. PEN substrate was treated with hexamethyldisilazane (HMDS) in order to make it more hydrophobic. Indeed, the hydrophobized surface of the plastic substrate was shown to induce a more ordered supramolecular structure of the semiconductor layer during the evaporation process. The hybrid organic/inorganic formally trilayer non-passivated OTFT structure was successfully profiled in a single run through ToF-SIMS depth profiling experiments with low energy cesium ions. High mass molecular fragment ions were obtained and used as indicators of interfaces, leading to an increase of information on molecular specificity. The HMDS surface modification was clearly detected and spatially located. Finally, a chemometric approach was also adopted to evaluate depth profiling data. In particular, principal component analysis (PCA) and K-means algorithm were tested as innovative method for the identification of molecular fragments useful for the OTFT multi-layer structure characterization and the determination of the number of OTFT layers, respectively.

In this work, staggered top-gate n-type organic thin film transistors (OTFTs) with evaporated PDIF-CN2 semiconducting layers, spin-coated Cytop™ dielectric barriers and channel lengths ranging from 100 to 2 μm were fabricated on polyethylene-naphtalate (PEN) substrates. Hexamethyldisilazane (HMDS) treatment of the PEN surface was successfully tested as an effective strategy to achieve flexible devices with improved electrical response. Following this approach, maximum field-effect mobility (μFE) values exceeding 0.4 cm2/V⋅s were observed in air. Moreover, the self-encapsulating features of the investigated top-gate configuration, employing the highly hydrophobic Cytop™ dielectric films, allowed getting considerable performances in terms of un-sensitivity to hysteresis and bias stress phenomena.

We studied the capacitance characteristics of printed p-type organic thin-film transistors (OTFTs) under vari- ous frequencies and dc bias conditions. The experimental results show that the device capacitance is largely influenced by parasitic capacitances, related to the large gate-active layer overlap areas required by the printing processes. We developed a nonquasi- static small-signal capacitance model that adopts a transmission line approach and considers the specific layout of the OTFTs, taking into account for the parasitic capacitances and, hence, is particularly well suited for printed devices. In addition, the model included parasitic impedance at the metal-organic semiconductor contacts, related to the nonohmic behavior of source-drain contacts. The model has been shown to nicely reproduce the experimental capacitance characteristics in all their features. It should be pointed out that the proposed model allows the reproducing of any device layout and could be implemented in device simulator to analyze small-signal dynamic characteristics.

Multi-flngered OTFTs, with staggered top-gate configuration have been fabricated on flexible polyethylene-naphtalate (PEN) substrates (100 μm thick). Inkjet printing technique has been used to setup the silver contacts, while the organic layers and the dielectric fluoropolymer have been deposited by spin-coating. The p-type polymeric semiconductor is a solution processed 6,13-bis(triisopropyl-silyletynyl) pentacene. The semiconductor layer thickness is about 30 nm, while the dielectric fluoropolymer is 400 nm thick. These transistors have been characterized and a DC, and a transient accurate models have been developed and imported in CADENCE. Finally, SPECTRE has been used to simulate model circuits based on such a device. In this work we describe the design of high frequency logic gates and preliminary flip-flops design, exploiting PMOS organic transistor and its expected performances.

The electrical characteristics of organic thin film transistors (OTFTs) are frequently affected by contact effects, which can seriously reduce the transistor performance. The “parasitic” voltage drop at the contacts, induced by contact resistance, decreases the effective drain-source and gate-source voltages applied to the intrinsic channel of the transistor, reducing the device current. The importance of the contact resistance, Rc, is more relevant in the case of high carrier mobility and/or small channel length devices, where its value may become comparable or even larger than the channel resistance. Rc appears to be strongly affected by the device architecture and much higher Rc-values are typically observed, at low drain voltages, in coplanar structures (i.e. Bottom Gate/Bottom Contact, BGBC devices) than in staggered structures (i.e. Top Gate/Bottom Contact, TGBC devices). The presence of Schottky barriers, trap states, field dependence of carrier mobility and defected regions near the electrodes have been suggested as the origin of Rc. In this work, the contacts effects in devices with different architectures (staggered and coplanar) will be discussed. Devices characteristics have been measured at different temperature and the results have been analysed by using 2D numerical simulations (fig. 1 and 2). The electrical characteristics of both type of devices can be reproduced considering a Schottky barrier at the source contact with an “effective” barrier lowering, that takes into account different field-dependent effects occurring at the contacts (Shottky effect, tunnelling, trap assisted tunneling) that can increase the current injected by the electrode (fig.1 and 2). In the case of staggered devices, the detailed analysis of the current density shows that, at low Vds and for a given Vgs, the current is mainly injected from an extended source contact region overlapped by the gate electrode, inducing a current spreading along the contact (Ic - current in fig.3). The distribution of the current spreading remains basically constant for increasing Vds up to a value Vdsat1 (fig. 1), when the depletion layer of the Schottky contact expands reaching the insulator-semiconductor interface and causing the pinch-off of the channel at the source end. For Vds>Vdsat1 the current injected from the edge of the source contact rapidly increases (Iedge in fig.3a), due to field enhanced injection mechanisms, while the current injected from the remaining part of the source contact basically saturates. At higher drain voltage (Vds>Vdsat2, see fig.1), pinch off at the drain occurs. In the case of coplanar devices, current spreading, obviously, does not occurs and even at low Vds the current increase is related to the field enhanced injection mechanisms that take place at the edge of the source contact (fig.3b). The lack of the extended contact contribution to the injected current explains the higher contact resistance usually observe in coplanar devices at low Vds compared to staggered OTFTs. On the other hand, at high Vds (saturation condition) higher electric fields are present, in coplanar structure, near the source, that is in direct contact to the channel region. This results in a more efficient carrier injection that allows obtaining an almost ohmic contact condition in coplanar devices in saturation condition.

L’articolo prende le mosse dal chiedersi perche l’Italia sia oggi un Paese senza forma, avviluppato in una crisi al tempo stesso economico-sociale e politico-istituzionale. Si sostiene che tutto questo e il risultato di una lunga catena di scelte sbagliate e di scelte mancate in tema di sistema elettorale, riforme istituzionali e politiche del lavoro. Ripercorrere gli snodi essenziali delle occasioni perdute nell’ultimo ventennio e quindi una operazione necessaria, preliminare all’individuazione di una possibile via d’uscita alla crisi italiana.

Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon TFTs, fabricated with a spacer technology providing submicron (0.35 mu m) LDD regions, have been analyzed by using two-dimensional numerical simulations. The numerical analysis was used to explain the observed reduced kink effect and short channel effects presented by FSA GOLDD devices, compared to SA devices. The reduction of the kink effect has been attributed to the reduced impact ionization rate, and related to reduced electric fields at the channel/LDD junction. In addition, the role of the LDD dose on the kink effect has been also investigated, clarifying the observed current inflection occurring in the kink effect regime and the LDD dose dependence of the breakdown. Reduced short channel effects were attributed to reduced floating body effects, since drain induced barrier lowering was apparently not affected by the SA GOLDD structure, when compared to SA devices.

Organic Thin film Transistors (OTFT) have been widely investigated in these last years as potential candidate for the development of low cost, flexible and lightweight active-matrix backplanes for display applications. Indeed the organic semiconductors provide both promising electrical performances tunable by chemistry and the ability to be processed at low temperature with innovative printing technics on various large scale substrates. Thanks to the recent developments on both n-type and p-type solution-processed organic semiconductors, we have developed a printable organic CMOS technology compatible with flexible PEN substrates. By combining state of the art materials exhibiting mobility in the range of 1 cm2/V.s and silicon inspired compact modeling and simulation approach, we were able to design and fabricate circuit's building blocks that provide the switching, digital and analog functions required for the fabrication of printed systems on foil.

Contact effects in staggered SBTs with three different active layers (organic semiconductor (pentacene derivative), a-Si:H and IGZO) have been analyzed by using numerical simulations. In general, in staggered SBTs the presence of a Schottky barrier at the source severely limits the carrier injection, thus substantially reducing the on-current and, consequently, the on-off ratio, if compared to conventional TFT structures. On the other hand, depending upon barrier height and barrier lowering mechanisms, staggered SBTs can show interesting features, such as: 1) very low saturation voltage, resulting in much lower operating drain voltages and power dissipation; 2) increased output impedance, leading to larger voltage gain; 3) simpler fabrication, as doped regions are not necessary. Device characteristics of these devices are seriously influenced by contact effects, with the parasitic voltage drops at the contacts reducing the effective voltages applied to the channel of the transistor. A simple method to extract the contact I-V characteristics is presented and also a distributed diode model is discussed to reproduce the output characteristics and implementable in circuit simulations.

In this work we present a large signal non quasi static (LSNQS) compact model based on the discretization of the current continuity equation using a spline collocation approach. The underlying charge/current model is based on the VRH theory. The LSNQS model takes in consideration the presence of parasitic regions and is particularly suited for simulations of printed organic thin film transistors. Some results obtained by a Verilog-A implementation are presented.

Low-frequency noise (LFN) has been used in order to gain insight into the physical properties of the materials involved in organic thin-film transistors (OTFTs) fabrication, often with contradictory results. Besides the physical origin of noise, contact effects on noise have been a source of concern and discussion. In this paper, we report on accurate LFN measurements in p-type staggered top-gate OTFTs over four decades of channel current, from the subthreshold to the strong accumulation region. The measured spectra follow a clear 1/ $f$ behavior attributed to the trapping/detrapping of channel charge carriers into interface and oxide defects, while the influence of noise sources at contacts is found to be negligible. However, contacts affect the measured noise by a nonnegligible differential resistance. Noise data are interpreted in the context of a multitrap correlated mobility fluctuations (CMFs) model, showing that noise is dominated by acceptor-like traps. Despite the low mobility ( $\mu _{{\mathrm{eff}}}\sim $ 2 cm2/V/s), the large scattering parameter ( $\alpha \sim 10 ^{7}$ Vs/C) produces an increase of the noise at the higher currents due to CMFs. The product $\alpha \mu _{{\mathrm{eff}}} \approx 2\cdot 10^{7}$ cm2/C, which measures the strength of CMFs, is similar to what was reported for a-Si:H and much higher with respect to crystalline silicon MOSFETs revealing a strong correlation between CMFs and the state of disorder of the active layer.

As fabrication and positioning of micro- and nanocrystals grow in importance in a wide range technological applications, there is an increasing requirement for the development of a shared technological platform that is able to process materials from solutions on large areas. Here, the application of lithographically controlled wetting (LCW) for the manipulation and positioning of single crystals directly on devices is reported. In the LCW, a stamp, consisting of a metallic grid, is positioned in contact with a liquid thin film spread on a substrate; under these conditions, the capillary forces pin the solution to the stamp protrusions, thus splitting the continuous film in separated droplets or channels. As the solvent evaporates and the solution reaches the saturation, the solute precipitates onto the substrate within the menisci, giving rise to a structured thin film, in correspondence of the protrusion of the stamp. The possibility to achieve a patterning of crystals of conjugated molecules with a defined shape and with controlled size directly on device is demonstrated and pattern of crystals are investigated using polarized optical microscopy, atomic force microscopy, X-ray diffraction; they are also electrically characterized. The application of lithographically controlled wetting on the manipulation and positioning of single crystals directly on devices. It is demonstrated that it is possible to achieve patterning of crystals of conjugated molecules with a defined shape and with controlled size directly on a device.

Investigation of gate dielectric conduction properties in organic p-type staggered thin-film transistors is reported by means of direct-current, capacitance–voltage, and noise measurements. Results suggest that transport in the CYTOP™ gate dielectric is dominated, at low currents, by Schottky conduction due to the emission at the aluminum gate interface through a barrier $\phi _{B} \approx 1$ eV, while is limited, at higher currents, by space-charge conduction in the trap-limited regime with an effective mobility $\mu \theta $ estimated in the order of $10^{-9}$ cm2/(Vs). Gate current noise follows a 1/ $f$ law and it is found to be proportional to $I_{G}^{2}$ , which is inconsistent with the commonly assumed mobility fluctuation. Traps responsible for gate noise are dielectric-bulk traps, not located at the semiconductor interface, since the gate noise is found to be uncorrelated with drain noise.

We studied environmental stability of top contact pentacene TFTs with active layer evaporated at different growth rates. We measured the transfer characteristics in vacuum and in air and after storing the devices in oxygen for several days. Different pentacene growth rates result in different grain size of active layer. This morphology difference influences the hysteresis of transfer characteristics induced by water absorption. On the contrary, aging effects on the transfer characteristics of pentacene O-TFTs, induced by oxygen diffusion into the active layer, are not related to structural characteristics of pentacene film.

(Polytetrafluoroethylene) PTFE-like films, deposited by using CHF3/Ar gas mixtures in a plasma reactor, have been used as encapsulation layers in pentacene thin film transistors. The PTFE-like encapsulation layers allow to carry out photolithographic processes without damaging pentacene film. However, the PTFE-like encapsulation layers are not effective in reducing hysteresis of electrical characteristics when measured in air. On the contrary, the degradation of the device electrical characteristics, induced by oxygen diffusion into pentacene film after storing the devices in air, is almost completely suppressed by the encapsulation with the PTFE-like films.

Future system-on-panel applications require further performance improvement of circuits based on polycrystalline silicon thin film transistors (TFTs). The biggest leverage in circuit performance can be obtained by reducing channel length from the typical current values of 3-6 micron to 1 micron, or less. Therefore, short channel effects in scaled down polysilicon TFTs will have to be controlled in order to allow proper operation of the circuits. In this work we review a number of specific aspects of the electrical characteristics of short channel devices (channel lengths down to 0.4 micron) combining electrical characteristics measurements and two-dimensional numerical simulations.

The presence of high electric fields at the drain junction in polycrystalline silicon (polysilicon) thin film transistors (TFTs), enhances several undesired effects, such as hot-carrier related instabilities and kink effect. In order to reduce the drain electric field, non-self-aligned (NSA) device architecture can be adopted. In this case, dopant activation and active layer crystallization are achieved at the same time by excimer laser annealing, resulting in a substantial lateral dopant diffusion. The gradual doping profile provides not only a reduction of the drain electric field, but also a channel length shortening. Therefore, an effective channel length (L eff ) has to be determined in such devices, in order to successfully design circuit applications. In this work, L eff and parasitic resistance (Rp) modulation effects have been investigated in both n- and p-channel NSA polysilicon TFTs. Three different parameter extraction methods, originally proposed for the crystalline MOSFETs technology, have been used and compared in order to extract L eff and R p , including: the "channel resistance" method; the "paired V g " method; the "shift and ratio" method. These methods indicate a channel length reduction up to 1 μm and a non negligible parasitic resistance effect. The reliability of the results of the three methods are discussed in terms of applicability of the underlying assumptions in the case of polysilicon TFTs and numerical simulations are used to support the analysis.

We have fabricated bottom contact pentacene TFTs on flexible polyimide substrate and silicon substrate using different passivation layers in order to reduce the electrical instability of pentacene devices, induced by water diffusion in the film, as evidenced by electrical measurements under different environments. Experimental data show that parylene passivation layer does not introduce appreciable degradation of device characteristics and allows standard lithographic process, but it is not an effective barrier for water diffusion. The encapsulation of pentacene TFTs with an additional acryl layer does not reduce the device sensitivity to the water, whereas devices encapsulated by a parylene/acryl/aluminum triple layer do not show increase of transfer characteristics hysteresis when measured in air.

The electrical instabilities in p-channel polysilicon TFTs induced by negative bias temperature stress (NBTS) and self-heating have been investigated. From NBTS experiments performed at different temperatures and gate bias, we derived an empirical relationship that provides the T and electric field dependence of the interface state generation. To explain the device instability related to self-heating we considered a spatially non uniform interface state distribution, as a non uniform transverse electric field is present during bias stress. The interface state distribution can be deduced using the empirical relationship, determined from NBTS experiments, and considering the spatial distribution of the oxide electric field, obtained from numerical simulations. Using the so determined interface state distribution it was possible to perfectly reproduce not only the transfer characteristics but also the asymmetry observed in the output characteristics, when source/drain contacts are reverted after bias stress.

In this work, we investigated self-heating related instability in polysilicon thin film transistors (poly-Si TFTs) fabricated on polyimide (PI) substrates. Indeed, when Joule heating becomes relevant, the temperature of the active layer can substantially rise, since the devices are fabricated on thermally insulating substrates. As a result, electrical instability is triggered and attributed to the generation of interface states, due to the Si–H bond breaking, and charge trapping into the gate insulator. In addition, by using 3-dimensional numerical simulations, coupling the thermodynamic and transport models, we analyzed the temperature distribution of the device under operating conditions and found that self-heating is more severe for devices fabricated on plastic substrates.

In this work we present a study of the electrical stability of self-aligned p-channel TFTs fabricated using excimer laser annealing. The electrical stability was tested performing bias stress experiments and accelerated stability tests and we found that the device characteristics were seriously degraded upon application of large negative gate bias. From extensive analysis of the phenomenon through numerical simulations, we found that the device degradation could be perfectly reproduced by positive charge injection into the gate oxide in narrow (300–400 nm) regions at the edges of the gate, near the source and drain contacts. From the present results we conclude that the observed degradation is closely related to the residual damage, induced by ion implantation, present in the gate oxide near the gate edges.

An unambiguous characterisation of the polycrystalline-Si grain boundary behaviour has been obtained by studying thin film transistors, TFTs, realized on sequentially lateral solidified, SLS, material. The grain boundary, GB, carrier trapping has been distinguished from intra-grain trapping by analysing TFTs with channels aligned along two orthogonal directions in this anisotropic material: the thermal activation energy of the channel current was measured in the two orthogonal directions, and the difference in activation energy was related to carrier flow over perpendicular GBs. Two dimensional numerical simulations show that the experimental behaviour is correctly reproduced by a finite-width GB, in which carrier flow is controlled by transport across a resistive GB region, rather than by emission over a barrier.

The optical diagnostic of spectroscopic ellipsometry is shown to be an effective tool to investigate the mechanism of excimer laser crystallization (ELC) of silicon thin films. A detailed spectroscopic ellipsometric investigation of the microstructures of polycrystalline Si films obtained on SiO2/Si wafers by ELC of a-Si:H and nc-Si films deposited, respectively, by SiH4 plasma enhanced chemical vapor deposition (PECVD) and SiF4-PECVD is presented. It is shown that ellipsometric spectra of the pseudodielectric function of polysilicon thin films allows to discern the three different ELC regimes of partial melting, super lateral growth and complete melting. Exploiting ellipsometry and atomic force microscopy, it is shown that ELC of nc-Si has very low energy density threshold of 95 mJ/cm2 for complete melting, and that re-crystallization to large grains of ∼ 2 μm can be achieved by multi-shot irradiation at an energy density as low as 260 mJ/cm2 when using nc-Si when compared to 340 mJ/cm2 for the ELC of a-Si films.

We present, for the first time, the application of the asymmetric fingered thin film transistor (AF-TFT) architecture to self-aligned p-channel TFTs for kink effect suppression. In AF-TFT the transistor channel region is split into two zones with different lengths ( L 1 > L 2 ) separated by a floating p + region. A fourth electrode, contacting the floating p + region, allowed us to measure the individual electrical characteristics of the two sub-TFTs. Output characteristics show that substantial kink effect reduction can be achieved when the sub-TFT placed at the drain end of the device has an L 2 ≪ L 1 . The electrical characteristics were analysed by using numerical simulations in the framework of the two-transistor model and we show that kink effect suppression arises from the operation in saturation regime of the source sub-TFT. The electrical characteristics of the fabricated p-channel AF-TFTs show a complete kink effect suppression, making these devices very attractive for current drivers in organic light emitting displays.

We have investigated the stability of the electrical performances in staggered organic thin film transistors (OTFTs) manufactured by using a CYTOP fluoropolymer as a gate dielectric, after the devices underwent reliability cycles in a high moisture and temperature controlled environment chamber. The results of such testing cycles showed a very high stability against the environmental conditions that might be related to the device top-gate structure, working as an efficient encapsulation, and to the hydrophobic properties of the fluoropolymer used as gate dielectric.