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A detailed study of gate length scalability and device performance of undoped-body with extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates is presented. The results demonstrated that the improvement of short channel characteristics leads to higher drive current [I.sub.DSAT] and lower extrinsic gate delay CV/I at a fixed OFF-state current [I.sub.OFF].

The Glasgow 'atomistic' simulator was used to perform the 3-D statistical simulations of random-dopant-induced threshold voltage variation in state-of-the-art 35- and 13-nm bulk MOSFETs consisting of statistical samples of [10.sup.5] or more microscopically different transistors. The results showed that the random-dopant-induced threshold voltage distribution is positively skewed with increasing asymmetry as the channel length of the device reduced.

A study was conducted to examine the quasi-ballistic hole transport in nanoscale pMOSFETs using new self-consistent multi-subband Monte Carlo (MSMC) simulator. Findings reveal that ballistic ratios in pMOS are not much worse than in nMOS transistors.

The article studies the dependence of detailed simulation analysis on the biaxial strain of the Coulomb-limited mobility in n-type silicon MOSFETs using momentum relaxation time (MRT) approximation. Findings reveal that strain-induced changes of the substrate-impurity-limited mobility are very small.

The article studies 4H-SiC {0001} p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with deposited Si[O.sub.2] followed by [N.sub.2]O annealing. Findings suggest that the deposited oxides annealed in [N.sub.2]O are efficient in improving the performance of 4H-SiC p-channel MOSFETs.

The length of thin oxide definition area (LOD) effects and the incorporation of the dummy poly gates on the performance of 45-nm P-MOSFETs with and without strained SiGe source/drain (S/D) are examined. The compressive stress from the SiGe S/D has dominated the LOD effect for dummy poly gate located outside the active area, whereas the LOD effect is controlled by the SiGe S/D stress within the dummy gate and the STI stress for dummy poly gate located within the active area.

Random-dopant-fluctuation (RDF) effects on the trigate bulk MOSFET versus the planar bulk MOSFET is studied by using atomistic 3-dimensional (3-D) device simulation for devices with a 20-nm gate length. The trigate bulk MOSFET has provided a new method of threshold voltage adjustment by tuning the retrograde body doping depth in order to mitigate tradeoffs in threshold voltage variation and short-channel effect control.

Modern ultrathin films can be characterized by reconsidering the pseudo-MOS transistor physics and models. Updated models are derived that have accounted for the density of interface states and channel-to-surface coupling effects in ultrathin silicon-on-insulator (SOI) wafers with passivated and nonpassivated surfaces.

The impact of random discrete dopants in the source/drain (S/D) leads on the current variability of a gate-all-around Si nanowire transistor is analyzed. A full 3-dimensional (3-D) real-space nonequilibrium Green's function (NEGF) formalism is used for estimating the variability in the [I.sub.D]-[V.sub.G] characteristics of a future-generation Si nanowire transistor induced by random dopants (RDs) in the source/drain (S/D) extensions.

The development and experimental verification of physics-based compact channel noise models which can predict the noise performance of deep-submicron MOSFETs in all operation regions is reported. The models for thermal noise, flicker noise and corner frequency are derived, and the proposed models are validated, also considering the effect of the mobility fluctuations on the flicker noise and the dependence of the mobility on the inversion carrier density.

An analytical surface potential model and 3-D ATLAS device simulations are used to investigate the impact of gate misalignment on the performance of dual-material double-gate (DMDG) silicon-on-insulator (SOI) n-MOSFET (metal-oxide-semiconductor field-effect transistor). Analytical and simulation results are consistent, which validates the proposed model for the DMDG SOI n-MOSFET.

The pulsed drain current-voltage ([I.sub.d]-[V.sub.g]) measurement technique with a range of pulse durations is used to investigate the intrinsic electron-trapping properties of high-[kappa] gate stacks and the impact of fast transient charging on the threshold voltage shift ([Delta][V.sub.t]) of MOSFETs. The ([Delta][V.sub.t]) values are observed to be strongly dependent on the high-[kappa] and interfacial layer thicknesses, with hafnium-based gate stacks exhibiting a similar trap density profile.

A statistical simulation is used to investigate the impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) and SRAM cell's stability in the device and circuit level. Results reveal that the LER effect on the variation of threshold voltage and drive current is more substantial than in DG FinFETs, and the SBFET SRAM cell is more vulnerable to noise disturbance than its FinFET counterpart during the read operation.

The article explains the formulation of a new comprehensive physics-based compact model developed for the undoped silicon-nanowire MOSFETs with Schottky-barrier (SB) source/drain. The thermionic/tunneling transport is shown to play a more significant role in the channel, as compared to the conventional drift-diffusion transport.

The article presents a new contact resistance reduction technology, which employs the selenium segregation (SeS) phenomena for the n-MOSFETs with silicon-carbon source/drain. SeS technology is shown to lead to better process integration and hence can be used for the improvement of performance of several other devices.

Several theoretical, as well as experimental studies are conducted to explain the optimization of the process of hot-carrier injection (HCI) in germanium-on-silicon pMOSFETs. The results demonstrate that the lifetime of the transistors can be easily improved by increasing the Si-passivation thickness.

The article presents various different techniques that can be employed for the evaluation of the threshold voltage shift induced by the negative bias temperature instability (NBTI). The effects of sensing and recovery are shown to be the major factors that need to be considered during the process of voltage evaluation.

The analysis and comparison of the RF reliabilities of hot-carrier and Fowler-Nordheim (FN) tunneling stresses on 40-nm PMOSFETs with and without SiGe source/drain (S/D) is described. The studies have shown that the degradation difference between the strained and nonstrained PMOSFETs has become less as the stress has changed from the hot carrier to the vertical-only, that is, the FN tunneling stress.

A circuit point of view is used for designing a high-performance negative differential resistance (NDR) element and describing a possible compact device implementation. A single-NDR element static-random-access-memory cell prototype with a compact size and high speed is described as an interesting application suitable for embedded memory.

The effects of top-cut stress liners for damascene gate MOSFETs are examined by stress simulation. The results have shown that high channel stress is induced for shorter gate lengths and hence high drive current n- and pFETs are achieved by using top-cut stress liners with dual metal/high-k gates and eSiGe for damascene gate devices.

A comparative computational study on the strain effects in Si nanostructures including bulk, thin film and nanowire configurations is described. First principles calculation is used for identifying the bandstructure parameters such as band splitting energy and transport effective mass and it is shown that bulk Si and Si thin films have similar strain effects on the bandstructure parameters under uniaxial strain.

A new parameter extraction method is described for the series resistance of thin-film transistors (TFTs) and it is applied for analyzing amorphous silicon (a-Si) TFTs. The advantages and the ease of usage have made the new method and the series resistance model useful for the design, evaluation and modeling of TFTs.

A new dual-material-gate-trench power MOSFET is described that has displayed improvement in its transconductance and breakdown voltage without any degradation in on-resistance. The improvement in peak transconductance and breakdown voltage is achieved in the new device when compared to the conventional trench MOSFET by using [N.sup.+] poly-Si as a lower gate material and [P.sup.+] poly-Si as an upper gate material.

The combination of magnetoresistance (MR) and Pseudo-MOSFET measurements is described as an improved method for characterizing silicon-on-insulator (SOI) materials. The correlation between the MR mobility and effective mobility has helped in the analysis of the electron transport and scattering mechanisms in the silicon thin film.

The performance comparison between conventional n-i-n MOSFET transistors and tunneling field-effect transistors (TFETs) based on the p-i-n geometry is described by using semiconducting carbon nanotubes as the model channel material. Quantum-transport simulations are performed by using the nonequilibrium Green's function formalism considering realistic phonon-scattering and band-to-band tunneling mechanisms and the p-i-n TFETs are well suited for low-power applications.

The experimental ballistic ratio, injection velocity and carrier mean-free path evolutions with the transistor gate length, the inversion charge and the temperature are examined in n- and p-FDSOI devices. The evaluation of the device mean-free path and its evolution with both the inversion charge in the channel and the temperature is used for examining the mobility degradation with decreasing gate lengths, signifying the importance of Coulomb scattering on the mobility behavior.

Pd incorporated Ni germanide is used to construct highly thermally stable Ni germanide technology for high performance germanium metal-oxide-semiconductor field-effect transistors (Ge MOSFETs). The developed [Ni.sub.0.95][Pd.sub.0.05] alloy could find potential use for the high mobility Ge MOSFET applications.

A geometry-scalable parasitic deembedding technique for on-wafer S-parameter measurements of silicon MOSFETs is presented. The developed method is observed to be accurate, area efficient, and time saving for evaluating the intrinsic characteristics of silicon-based devices.

The development of a technology to atomically flatten the silicon surface on (100) orientation larger-diameter wafer and the formation technology of an atomically flat insulator film/silicon interface are reported. The fabricated MOSFETs with an atomically flat interface exhibited near ideal subthreshold swing factors with much smaller fluctuations, extremely lower 1/f noise, and higher MOS dielectric breakdown field intensity when compared to MOSFETs constructed with conventional technologies.

A comprehensive study of the analog performance for uniaxial strained PMOSFETs with sub-100 nm gate length is presented. The low-frequency noise and matching properties for strained and unstrained devices are nearly identical at a given [g.sub.m]/[I.sub.d] and might be used for analog design using advanced strained devices.

A phenomenological method is used for isolating the hole-trapping and interface trap generation components during negative bias temperature instability (NBTI) stress in plasma nitrided oxide (PNO) p-MOSFETs. The robustness and uniqueness of the separation procedure of the isolation technique is demonstrated by degradation data obtained from a wide range of operating conditions and a wide variety of PNO processes.

A novel modified charge pumping (MCP) measurement method for the characterization of the interface-trap generation in p-MOSFETs under negative-bias stress is presented. The recovery-free MCP method could be applied for the other BTI configurations such as the negative-bias temperature instability (NBTI) in n-MOSFETs and the PBTI in n- and p-MOSFETs.

The development of a new physically based classical continuous potential distribution model based on the channel center for a short-channel effect undoped body symmetrical double-gate transistor is reported. The newly developed technique could be used to solve the two-dimensional Poisson's equation analytically in a rectangular coordinate system.

The results from several qualitative 'benchmark' tests that are used to verify the physical behavior of the PSP model and its future application in generations of CMOS IC design are presented. The test performed includes new experimental data obtained from low-power, RF, mixed-signal, and analog applications of MOSFETs.

The quantitative analysis of the variability of encroached growth (VEG) of nickel silicide is used to study the association between the nickel silicide encroachment and the gate-edge leakage current. The [Si.sup.+] ion-implantation (Si-I.I.) technique can be applied to achieve low leakage current n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) without any disturbance of the transistor performance.

Low-temperature MOS-gated Hall measurements and gated diode capacitance-voltage (C-V) measurements are used for characterizing both trap density and Hall mobility on 4H-silicon carbide MOSFETs with gate oxides grown by sodium enhanced oxidation (SEO) and thermally grown in [N.sub.2]O. The temperature-dependent Hall mobility measurements have revealed that inversion layer mobility in both the SEO and baseline samples are limited by Coulomb scattering from interface trapped charge and surface roughness.

The general charge pumping model is used to determine impact of density, energy, and depth position for MOSFET with Si[O.sub.2] and high-K gate stacks. The results showed that at large biases, the energy region probed becomes fully depth dependent and is nearly the same regardless of the CP curve type.

A mathematical model for the dc/dynamic current of organic thin-film transistors (OTFTs) based on the variable-range hopping transport theory is presented. The simple formulation of the model is found to be suitable for implementation in a circuit simulator such as SPICE.

The development of a gate-induced drain-leakage current model for fully depleted double-gate MOSFETs using tunneling theory of Poisson's equation is described. The device was equated for drain voltages, gate-oxide thickness, body widths, and drain doping concentrations over a wide range of leakage currents by comparing it with simulation results.

The article studies the effect of n-channel hot electron and p-channel gate oxide breakdown (BD) on the MOSFET third-order intermodulation. The intermodulation intercept point characteristics and the value of gate-source voltage show a similar shift and in the threshold region, the device VIP3 is sensitive to BD leakage current and BD location effect.

TCAD modeling is used to study the performance of symmetric double-gate MOSFETs with dopant-segregated Schottky source/drain (S/D) regions and compared with raised S/D (RSD) MOSFETs. The results show that the doped extension region adjacent to the S/D Schottky barrier (SB) enhances the drive current by shrinking the SB but is limited by its dual role as a heavily doped S/D extension region to improve drive current and a lightly doped S/D region to reduce BTBT leakages.

The development of a new analytical electron low field mobility model using the shear-strain component and quantum confinement effect for use in drift-diffusion simulator is discussed. This model proves the advantage of (110) channel nMOSFETs with higher stress contact etch stop layer in reproducing the gate-bias dependence of (100) piezoresistance coefficients in bending experiments.

TCAD simulations of the hot-carrier-reliability assessment of the gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET is carried out. The simulation results showed a reduction in the hot-carrier-reliability metrics, which suggests the feasibility of the GEWE-RC MOSFET design for high-performance application in which hot-carrier reliability plays an important role.