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Transition metal dichalcogenides (TMDC) have remarkable properties for the next generation of electronic devices [1]. A complementary metal-oxide-semiconductor (CMOS) inverter consisting of pairs of p-type and n-type field-effect transistor (FET) is a fundamental building block in modern digital electronics [2]. Therefore, realization of both p-type and n-type FETs based on semiconducting TMDC is of particular importance. Among various semiconducting TMDC, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [3]. These prominent features of WSe2 motivates the fabrication and characterization of a CMOS inverter. One of the significant challenges is to develop a high-gain CMOS inverter for operation at a low power supply voltage (Vdd) for future low power digital electronics. Previous studies on a WSe2 CMOS inverter were limited to operation with a low gain of 3 or a high Vdd of more than 1 V under conditions of relatively low gate capacitance and degraded interfacial properties [3-5]. This study addressed these issues by developing a doping technique and gate stack technology to demonstrate the high-gain with low-Vdd operation of a WSe2 CMOS inverter [6]. The focus is on the doping technique of both electrons and holes to a WSe2 layer by simple spin-coating. Of particular interest in this study is the impact of gate stack technology on the CMOS inverter characteristics in low-Vdd operation. In this study, a hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is applied to a WSe2 CMOS inverter for high-gain low-Vdd operation since superior interfacial properties with high gate capacitance have been reported in molybdenum disulfide (MoS2) FETs. For p-type WSe2 FETs, the fluoropolymer CYTOP (AGC, CTX-809A) was applied since polarization in CYTOP due to the difference in electronegativity between C–F bonds generates holes in WSe2. On the other hand, poly(vinyl alcohol) (PVA) was utilized for n-type WSe2 FETs because positive charges in PVA accumulates electrons in WSe2. The resin solutions of both CYTOP and PVA were purchased from a commercial supplier. A heavily doped p-type silicon substrate (p+-Si) was thermally oxidized to form a 60 nm thick silicon dioxide (SiO2) layer for the global back-gate architecture. Palladium (Pd) and gold (Au) as the source and drain contacts for p-type and n-type WSe2 FETs were fabricated by the lift-off process, respectively. An aluminum (Al) gate was prepared and a hybrid SAM/AlOx gate dielectric was formed by oxygen (O2) plasma and an immersion process. After that, mechanically exfoliated WSe2 was transferred with a poly(dimethylsiloxane) (PDMS) stamp. Finally, CYTOP and PVA were deposited by spin-coating for p-type and n-type WSe2 FETs, respectively. Figures 1 (a) and (b) show the Id–Vg characteristics of fabricated FETs. For the p-type WSe2 FET, a small SS of 78 mV/dec and an on/off ratio of about 106 order were observed. On the other hand, the Id–Vg characteristics of the n-type WSe2 FET were degraded compared with those of the p-type WSe2 FET because of the Schottky contacts. Figures 2 (a) and (b) show the transfer characteristics and gain as a function of Vdd in CMOS inverter. The gain of the CMOS inverter increased to as high as 9 at Vdd of 0.5 V. Figure 3 shows the benchmark of this study. Our proposed concepts enabled the operation with high gain at a low Vdd as low as 0.5 V for the WSe2 CMOS inverter, which had not been realized in previous studies. The dangling-bond-free and ultrathin SAM/AlOx gate dielectric has an important role in the low-Vdd operation of the WSe2 CMOS inverter. This study opens up interesting directions for the research and development of TMDC-based devices and circuits. References [1] Q. H. Wang, K. K. Zadeh, A. Kis, J. N. Coleman, and M. S. Strano, Nat. Nanotechnol. 7, 699 (2012). [2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices (Cambridge University Press, Cambridge, 1998). [3] L. Yu, A. Zubair, E. J. G. Santos, X. Zhang, Y. Lin, Y. Zhang, and T. Palacios, Nano Lett. 15, 4928 (2015). [4] C.-S. Pang and Z. Chen, 2018 76th Device Research Conf. (DRC), p. 1, 2018. [5] M. Tosun, S. Chuang, H. Fang, A. B. Sachid, M. Hettick, Y. Lin, Y. Zeng, and A. Javey, ACS Nano 8, 4948 (2014). [6] T. Kawanago, T. Matsuzaki, R. Kajikawa, I. Muneta, T. Hoshii, K. Kakushima, K. Tsutsui, and H. Wakabayashi, Jpn. J. Appl. Phys. 61, SC1004 (2022). Figure 1

In this paper, we report on the device concepts for high-gain operation of a tungsten diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter at a low power supply voltage (V dd ), which was realized by developing a doping technique and gate stack technology. A spin-coating with a fluoropolymer and poly(vinyl alcohol) (PVA) results in the doping of both electrons and holes to WSe2. A hybrid self-assembled monolayer/aluminum oxide (AlO x ) gate dielectric is viable for achieving high gate capacitance and superior interfacial properties. By developing the doping technique and gate stack technology, we experimentally realized a high gain of 9 at V dd of 0.5 V in the WSe2 CMOS inverter. This study paves the way for the research and development of transition metal dichalcogenides-based devices and circuits.

We have successfully fabricated chip-level integrated nMISFETs with sputtered molybdenum disulfide (MoS 2 ) thin channel using sulfur-powder annealing (SPA) and molybdenum disilicide (MoSi 2 ) contact which show n-type-normally-off operation in accumulation. SPA intentionally compensated sulfur vacancies of sputtered MoS 2 film. Eventually, we achieved a normally-off operation, which realizes industrial chip-level LSIs with MoS 2 channel.

The annealing temperature dependent electrical characteristics of La2O3 gate dielectrics for W gated AlGaN/GaN high electron mobility transistors (HEMTs) have been characterized. The threshold voltage (Vth) has been found to shift to positive direction with higher temperature annealing, exceeding those of Schottky HEMTs, presumably attributed to the presence of negative fixed charges at the interface between La2O3 and AlGaN layers. At a high temperature annealing over 500 °C, a high dielectric constant (k-value) of 27 has been achieved with poly-crystallization of the La2O3 film, which is useful to limit the reduction in gate capacitance. A high k-value for La2O3 gate dielectrics and the presence of negative charges at the interface are attractive for AlGaN/GaN HEMTs with low gate leakage and normally-off operation.

This study reposts the fabrication of top-gate molybdenum disulfide (MoS2) field-effect transistor (FET) by the transfer printing of a gate dielectric in conjunction with a poly(vinyl-alcohol) (PVA) coating for carrier doping. The spin-coated PVA film increases the carrier concentration in MoS2, while the back-gate MoS2 FET cannot be turned off. The transferred top-gate structure with the PVA coating makes it possible to turn off the fabricated device without permanent damage to MoS2. The results of this study suggest interesting directions for the research and development of two-dimensional material-based functional devices.

Since layered semiconductor tungsten diselenide (WSe2) has no dangling bond and a relatively large band gap, it is expected as a channel material for an application of field effect transistor (FET)[1]. On the other hand, high energy process destroys the crystal structure of the layered semiconductor. In this context, carrier doping by the low energy process is important for improving the electrical characteristics. This study reports that CYTOP (9 wt%) was applied as a doping material on the WSe2 FET for p-type operation by spin coating and the impact of contact doping on the electrical characteristics was investigated. A SiO2 gate dielectric was formed on a heavily-doped p-Si substrate (p+-Si) using thermal oxidation for back-gate structure. Next, a source / drain of Au (40 nm) / Ti (10 nm) was prepared by using photolithography and lift-off. Using a PDMS stamp and a micromanipulator, WSe2, which was mechanically peeled off using Scotch tape, was transferred between the source and drain to fabricate a back-gate WSe2 FET. After measuring the electrical characteristics without CYTOP, CYTOP was applied on the WSe2 FET surface using a spin coating. Then, the electrical characteristics with CYTOP were measured again. In this study, the annealing was performed for 30min at 200 ° C and 250 ° C. Id-Vg characteristics as a function of annealing temperature of the fabricated back gate WSe2 FET are shown in Fig. 1. From the Fig. 1, it can be confirmed that WSe2 FET shows p-type operation. Moreover, it can be confirmed that the drain current increases by applying the CYTOP, while the low drain current was observed without CYTOP. It was found that the drain current was increased with increasing the annealing temperature. [Acknowledgments] The authors would like to thank Professor Y. Kawano, Professor T. Hoshii, Professor I. Muneta, Professor K. Kakushima, Professor K. Tsutsui, and Professor H. Wakabayashi of Tokyo Institute of Technology for their continuous support in the experiments. This study was supported by JST CREST (Grant No. JPMJCR16F4) and a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616). [References] [1] In-Tak Cho et al., Applied Physics Letters 106, 023504 (2015). Figure 1

We demonstrate chip-level integrated n-type metal–insulator–semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS2) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al2O3) film and interface trap densities between the MoS2 and Al2O3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future.

Recent progress of nanotechnology has made possible observations of unique characteristic of nano-structure which are not possible in bulk semiconductors. In this talk, novel properties and possible device applications of quantum dots (OD), nanowires (1D) and atomic layer (2D) devices are discussed.

This study reports the impact of interfacial engineering by means of SAM (Self-assembled monolayer)-based gate dielectric on channel mobility in molybdenum disulfide (MoS 2 ) field-effect transistors (FETs). A gated four-probe method was implemented to eliminate the effect of contact resistance on channel mobility. The formation of SAM significantly plays an important role in the improvement of channel mobility as high as 19 cm2/Vs in Mos2FETs because the superior interfacial properties can be realized in MoS 2 /SAM structure. This study opens up interesting direction of interface engineering for research in the applications and developments of 2-dimensional materials-based thin film devices.

This study reports the polarity control in WSe 2 FET using global p+-type Si back gate architecture in conjunction with Al gate. By using WSe 2 as channel material and Au as source and drain contact metal, both hole and electron can be injected into the channel layer. As a result, p-type and n-type operation was experimentally demonstrated by applying appropriate back bias condition.

This paper describes a basic concept relevant to deterministic transfer of molybdenum disulfide (MoS 2 ) with optically transparent elastomeric stamp for constructing field-effect transistors (FETs). A simple fabrication process involving the formation of gate dielectrics and gate electrode, the deposition of source/drain contacts and the lamination of MoS 2 flakes is established. The proposed method is suitable for research in electrical characteristics of various TMDC FETs.

Layered semiconductors of transition metal dichalcogenides (TMDC) have been considerable attention for both scientific interest and practical applications [1]. This paper describes a method to fabricate TMDC field-effect transistors (FETs) with heavily-doped silicon on insulator (SOI) substrate. The FETs are constructed by transfer of TMDC crystals on the surface of pre-patterned SOI substrate. This method can eliminate the deposition of metals and dielectrics on a TMDC surface [2]. In addition, various TMDC can be applied to the fabrication of FETs. The heavily-doped SOI serves as a gate electrode, while an efficient injection of carriers into TMDC can be accomplished because of overlap structure between gate electrode and source/drain contacts. The device characteristics are investigated.

Contributions of gate metal to electrical characteristics in AlGaN/GaN Schottky HEMT are reported. The focus is on the collapse of drain current associated with Schottky metals. Ni and W gate introduce electrically active defects under the gate metal in AlGaN layer. These electrically active defects induce the current collapse, higher gate leakage current, and frequency dispersion in C-V characteristics. Contrarily, TiN metal seems to mitigate the appearance of such electrically active defects. The observed current collapse is not the permanent but the recoverable degradation by means of light exposure irrespectively of the gate metals, suggesting the involvement of electron trapping on defects, particularly at the gate edge on the drain side where the electric field is the highest. The nitrogen vacancies in the AlGaN layer underneath the Schottky gate are plausible origin that is responsible for the electrically active defects based on the dependence of nitrogen concentration in TiN metal on the current collapse, which can be explained in terms of nitrogen diffusion from the AlGaN layer to the gate metal.

This study describes the fabrication of top-gate molybdenum disulfide (MoS2) field-effect transistor (FET) using transfer printing of an Al2O3 gate dielectric. Semiconducting MoS2 has been considerable attention for applications as channel materials of FETs because a two-dimensional (2D) crystal is free from dangling bonds at the surface [1]. On the other hand, atomic layer deposition (ALD) of high-k gate dielectric is incompatible with MoS2 since an ALD precursor cannot be chemisorbed onto the surface of MoS2 due to the absence of dangling bonds [2]. Furthermore, ALD disrupts the surface structure and induces the oxidation of the channel layer [2], leading to the degradation of FET characteristics or the failure of devices. This study addresses these issues by utilizing the transfer printing of a high-k gate dielectric on a MoS2 layer [2], [3]. Transfer printing can avoid the deposition of a high-k gate dielectric directly on a fragile MoS2 surface. An abrupt and sharp interface can be anticipated by implementing the transfer printing of high-k gate dielectric. A key component for developing the transfer printing of the Al2O3 gate dielectric is to find out an appropriate sacrificial layer on the handling substrate. In this study, nickel (Ni) metal was adopted as the sacrificial layer for the transfer printing of the Al2O3 gate dielectric. It was revealed that the adhesion strength at Ni and thermally grown SiO2 interface is reduced by immersion in deionized water (DIW) [3]. The penetration of water into the interface results in the separation of Ni from the SiO2 surface. This Ni layer can be etched by using dilute nitric acid (HNO3). On the other hand, HNO3, which is an oxidizing agent, cannot etch an oxide gate dielectric. A 50-nm-thick Ni layer was deposited on the SiO2 (400 nm)/Si substrate by thermal evaporation (Fig. 1 (a)). The Al2O3 gate dielectric was deposited on the Ni layer by ALD with trimethylaluminum (TMA) and a H2O oxidant at a substrate temperature of 300 oC. Polymethyl methacrylate (PMMA) was prepared on Al2O3 by spin-coating as a protective layer. Next, a thermal release tape was attached to the PMMA layer. Then, the entire substrate was immersed in DIW for 5 min to weaken the adhesion strength between Ni and SiO2. The laminated structure was peeled off from the SiO2 surface in DIW. After the etching of Ni layer with dilute HNO3 (60% HNO3 : H2O = 1 : 10), the Al2O3 gate dielectric was transferred on MoS2 flakes. The Al2O3 gate dielectric and PMMA bilayer can be released from the thermal release tape by baking on a hot plate. After the removal of PMMA by oxygen plasma ashing, Al (40 nm) for the gate and Au (40 nm)/Ti (10 nm) for the source/drain were fabricated by the lift-off process. Finally, forming gas annealing (FGA) was performed in ambient (H2 : N2 = 3% : 97%) at 300 oC for 30 min to improve the electrical contacts at source/drain. The fabricated FET has small hysteresis, low leakage current, a subthreshold slope of 120 mV/dec, and a carrier mobility of 7.3 cm2/Vs (Fig. 1 (b)). The abrupt and sharp interface was demonstrated for transfer printing of the Al2O3 gate dielectric on the MoS2 channel layer. Process mismatches including temperature and chemical compatibility are avoidable by adopting the transfer printing method. The use of transferred high-k gate dielectrics is not restricted to MoS2 FETs. It is also applicable to various 2D layered materials. This study opens up the interesting direction for the research and development of 2D material-based functional devices. Acknowledgments The authors would like to thank Professor Y. Kawano, Professor T. Hoshii, Professor I. Muneta, Professor K. Kakushima, Professor K. Tsutsui, and Professor H. Wakabayashi of Tokyo Institute of Technology for their continuous support in the experiments. This study was supported by JST CREST (Grant No. JPMJCR16F4) and a JSPS Grant-in-Aid for Young Scientists (B) (Grant No. 17K14662). References [1] B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti, and A. Kis, Nat. Nanotechnol. 6, 147 (2011). [2] X. Duan, C. Wang, A. Pan, R. Yu, and X. Duan, Chem. Soc. Rev. 44, 8859 (2015). [3] C. H. Lee, J. H. Kim, C. Zou, I. S. Cho, J. M. Weisse, W. Nemeth, Q. Wang, A. C. T. van Duin, T. S. Kim, and X. Zheng, Sci. Rep. 3, 2917 (2013). Figure 1

This study describes the transfer printing of an Al2O3 gate dielectric for the fabrication of a top-gate MoS2 FET. The transfer printing of the Al2O3 gate dielectric involves the peeling-off process, etching of the sacrificial layer, and stacking on the MoS2. This method eliminates the direct deposition of Al2O3 gate dielectric on fragile MoS2 and provides an abrupt Al2O3/MoS2 interface. The fabricated FET has small hysteresis, low leakage current, a subthreshold slope of 120 mV dec−1, and a carrier mobility of 7.3 cm2 V−1 s−1. The transfer printing approach is applicable to various high-k gate dielectrics and layered materials for constructing functional devices.

This study reports on the electrical characteristics of (1 1 0)-oriented nMOSFETs with a direct contact La-silicate/Si interface structure and the detailed comparison with (1 0 0)-oriented nMOSFETs. Precise control of oxygen partial pressure can provide the scaled EOT down to 0.73 nm on (1 1 0) orientation in common with (1 0 0) orientation. No frequency dispersion in Cgc–V characteristic for (1 1 0)-oriented nMOSFETs is successfully demonstrated at scaled EOT region, while higher amount of available bonds on (1 1 0) surface results in a larger interface state density, leading to the degradation of sub-threshold slope. High breakdown voltages of 2.85 V and 2.9 V for (1 0 0)- and (1 1 0)-oriented nMOSFETs are considered to be due to superior interfacial property. The electron mobility on (1 1 0) orientation is lower than that on (1 0 0) orientation because of the smaller energy split between fourfold valleys and twofold valleys as well as the larger density of states for lower-energy valleys in the (1 1 0) surface. Moreover, electron mobility is reduced with decreasing EOT in both (1 0 0)- and (1 1 0)-oriented nMOSFETs. It is found that threshold voltage instability by positive bias stress is mainly responsible for bulk trapping of electron even with a larger interface state density in (1 1 0) orientation and influence of surface orientation on threshold voltage instability is negligibly small.

This study describes the fabrication of molybdenum disulfide (MoS 2 ) field-effect transistors (FETs) using adhesion lithography and self-assembled monolayer (SAM)-based gate dielectrics. The adhesion lithography involves the formation of a SAM on metal oxides and selective removal of metal layer from the surface of SAM. Electrical characteristics of MoS 2 FETs in this study resemble those of MoS 2 FETs fabricated by photolithography. Hysteresis in I d -V g characteristics is found to be reduced by forming gas annealing at 150 °C for 30 min. Furthermore, it is found that the SAM-based gate dielectrics is thermally stable at annealing temperature up to 300 °C. This study opens up new directions for research in the applications and developments of the SAM for functional electronic devices.

The gate leakage current in advanced metal gate/high- K (EOT ≈ 0.6 nm) nMOSFETs with severe gate-to-drain dielectric breakdown is investigated in detail. Even though several models have been proposed in the past to deal with this issue, they are mainly intended to be used in circuit simulation environments. On the contrary, we report in this work an analytic expression for the gate current based on the solution of the generalized diode equation. The model has been tested not only for positive drain and gate voltage conditions but also for negative biases.

This study focuses on studying the effective electron mobility in direct contact La-silicate/Si structure based nMOSFETs and searching for the difference of the mobility characteristics compared with the SiO 2 MOSFETs. In this study, three types of gate electrode structure were prepared to investigate the mobility characteristics over a wide EOT range; W for EOT of 1.63 nm, TiN/W for EOT of 1.02 nm and metal-inserted poly-Si (MIPS) for EOT of 0.71 nm. Since the silicate formation is basically caused by the presence of oxygen, Si layer in MIPS can suppress the oxygen in-diffusion from atmosphere, resulting in scaled EOT. It is found that the E eff dependence of mobility with La-silicate is observed to differ from the mobility of SiO 2 MOSFETs. The electron mobility with La-silicate shows the weaker E eff dependence than the mobility of SiO 2 nMOSFETs in middle and high E eff region. This suggests an existence of additional mobility component related to the direct contact La-silicate/Si structure. The effective electron mobility is degraded with decreasing EOT in entire E eff region. This means that the scattering sources including Coulomb scattering, phonon scattering and surface roughness scattering are located not at La-silicate/Si interface but the inside of gate stacks and approach the Si inversion channel. Coulomb scattering and phonon scattering are thought to be strengthened by increasing k -value because of the enhancement of Coulomb scattering potential and higher ionicity in La-silicate gate dielectrics. The influence of metal/high- k interface is also considered to affect on the mobility with decreasing the EOT.

This paper reports on the control of the direct-contact La-silicate/Si interface structure with the aim of achieving scaled equivalent oxide thickness (EOT) and small interface state density. The interface state density at the direct-contact La-silicate/Si interface is found to be reduced to 1.6 × 1011 cm-2eV-1 by annealing at 800 °C for 30 min in forming gas ambient, whereas excess silicate reaction concurrently induced a significant increase in EOT. By utilizing metal-inserted poly-Si (MIPS) stacks and their annealing at high temperature, the increase in EOT is drastically suppressed. At the same time, a superior interfacial property is obtained because the Si layer in the MIPS stacks prevents the excess oxygen diffusion from the atmosphere during the annealing process. As a result, the effective electron mobility of 155 cm2/V·s at 1 MV/cm and an EOT of 0.62 nm are successfully achieved by utilizing direct-contact La-silicate/Si structure. This result is comparable with the recorded effective electron mobility achieved by utilizing Hf-based oxides/Si structure. This demonstrates the advantage of our proposed method to realize the scaled EOT with a superior interfacial property for state-of-the-art metal-oxide-semiconductor field-effect transistors.

Effects of a thin metal layer (W, Ta, or Mo) inserted at the interface between La2O3 high-k gate dielectric and TiN gate metal were studied. It was found that the inserted metal layer plays crucial role in determining the electrical characteristics of the TiN/Metal/La2O3/Si gate stack. Our results show that EOT can be scaled to 0.5nm and below by inserting a W layer with optimum thickness at the interface between La2O3 high-k gate dielectric and the TiN gate metal.

Metal-Inserted Poly-Si (MIPS) stacks for gate oxide scaling have been presented with La2O3 gate dielectrics. An equivalent oxide thickness (EOT) of 0.69nm can be achieved with good interfacial property by high temperature annealing. The flatband voltage (VFB) can be modulated by oxygen incorporation in conjunction with Si removal process while EOT degradation is less than 1Aå.

Electrical properties of TiN/W/La2O3 high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La2O3 is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved in the gate stack with a 3nm W inserted layer after annealed at 800oC in a forming gas ambient. Our results show that TiN/W/La2O3 gate stack is one of the promising candidates in realizing high-k gate stack with EOT 0.5nm and beyond.

An aggressive equivalent oxide thickness (EOT) scaling with high-k gate dielectrics has been demonstrated by ultra-thin La"2O"3 gate dielectric with a proper selection of rare earth (La-, Ce- and Pr-) silicates as an interfacial layer. Among silicates, Ce-silicate has shown the lowest interface-state density as low as 10^1^1cmv^-^2/eV with a high dielectric constant over 20. n-Type field-effect transistor (FET) with a small EOT of 0.51nm has been successfully fabricated with a La"2O"3 gate dielectric on a Ce-silicate interfacial layer after annealing at 500^oC. Negative shift in threshold voltage and reduced effective electron mobility has indicated the presence of fixed charges in the dielectric. Nonetheless, the high dielectric constant and nice interfacial property of Ce-silicate can be advantageous for the interfacial layer in highly scaled gate dielectrics.

In this paper, we developed a model for remote surface roughness scattering (RSR)-limited electron mobility in the inversion layer of nMOSFETs with high-k dielectrics. A Numerical method is applied to calculate RSR-limited electron mobility. It has been demonstrated that the RSR-limited electron mobility is highly degraded in the high electric field region.

Chemical bonding states and electrical characteristics of a La-silicate formed as a compositional transition layer at La2O3/Si interface has been examined. A direct contact of a high-k gate dielectric with Si substrate has been achieved without forming SiO2-based interfacial layer by forming a compositionally graded La-silicate layer, which is advantageous for equivalent oxide thickness (EOT) scaling. A transistor operation with an EOT of 0.48 nm has been demonstrated with low temperature annealing, however a degradation of effective mobility (μeff) has been observed. A high μeff of 300 cm2/V s with relatively low interfacial state density (Dit) of 1011 cm−2/eV can be achieved when annealed at 500 °C, indicating fairly nice interface properties of silicate/Si substrate. Mobility analysis has revealed an additional Coulomb scattering below an EOT of 1.2 nm, which is in good agreement with the negative shifts in threshold and flatband voltages. Moreover, increase in Dit and subthreshold slope have been observed while decreasing the EOT, suggesting the influence of metal atoms diffused from the gate electrode. A mobility degradation model is proposed using metal induced defects generation.

The chemical bonding states and electrical characteristics of SrO capped La2O3/CeOx gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5 nm has been demonstrated. A strongly degraded effective electron mobility of 78 cm2/V s at 1 MV/cm has been obtained, which fit well with the general trend in small EOT range below 1 nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling.

This study reports the electrical characteristics of La-Sc oxides complex and effect of nitrogen incorporation for applications to high-k gate stack. We found that V"f"b can be controlled by the ScO concentration. Moreover, large bumps in C-V curves, which indicate high interfacial state density, can be suppressed with large ScO concentration. nMOSFETs using the La-Sc oxides complex in the gate stack are fabricated. In addition, nitrogen incorporation into the La-Sc oxide films was fond to be useful to suppress the EOT growth during annealing at high temperatures.

A simple yet accurate model for the postbreakdown output characteristics of advanced n-MOS transistors with metal gate (W) and high-κ (La2O3, equivalent oxide thickness=0.6 nm) gate insulator is reported. The model specifically deals with the so-called linear response regime in which the transistor action is no longer operative after the failure event. By analyzing three particular cases of interest, it is shown that the proposed model is able to account for the conduction characteristics corresponding to failure sites located both at the center of the channel region and close to the source and drain contacts. A compact model for the bulk-drain current is included in order to simulate the departure from linearity occurring at the negative drain bias.

This letter focuses on studying the characteristic behavior of oxygen in La-silicate dielectrics by comparison with HfO2 dielectrics. VFB shift of La-silicate caused by oxygen annealing is found to be stable even after reduction annealing unlike with HfO2. Moreover, reduced gate leakage current and improved effective mobility of nMOSFETs with La-silicate are observed by oxygen incorporation, suggesting the annihilation of oxygen vacancy. Since the oxygen in La-silicate covalently exists adjacent to the Si atom, stability of oxygen in La-silicate can be understood in terms of strong bonding of covalent nature.

In this study, radical oxidation is applied to the fabrication of a hybrid self-assembled monolayer (SAM)/hafnium oxide (HfOx) gate dielectric in molybdenum disulfide (MoS2) field-effect transistors. The fabrication process involves radical oxidation to form HfOx at the surface of metallic HfN, SAM formation by immersion, and the deterministic transfer of MoS2 flakes. A subthreshold slope of 75 mV/dec and small hysteresis were demonstrated, indicating superior interfacial properties. Cross-sectional transmission electron microscopy revealed the uniform formation of the HfOx layer at the surface of HfN. The SAM is indispensable for the superior interfacial properties in MoS2 field-effect transistors. The radical oxidation is not restricted to the oxidation of silicon and germanium substrates and was also found to be applicable to the fabrication of a high-k gate dielectric. This study opens up interesting possibilities of radical oxidation for research on functional electronic devices.

Semiconducting transition metal dichalcogenides (TMDC) have been growing interest for both scientific interest and practical applications because of their various material properties. Potential applications and fundamental understanding in new classes of semiconductor materials motivates the fabrication of field-effect transistors (FETs) that are indispensable for probing of carrier transport properties, accumulation of charge and interfacial phenomena. This paper reports a fabrication and characterization of TMDC FETs with heavily-doped silicon-on-insulator substrate. The silicon processing is sophisticated technology that can be extended to the reliable operation of TMDC FETs with high reproducibility. In this presented approach, the heavily-doped SOI can work as a gate electrode in FETs, while the carrier injection into TMDC layer is possible by preparing overlap structure between gate electrode and source/drain contacts. The effectiveness of our approach was demonstrated through the fabrication and characterization of FETs. P-type SOI(88 nm)/BOX(145 nm) wafer was cleaned with SPM and HF solutions. For heavily-doped n-type SOI (n+ SOI), phosphorus-doped spin-on-glass (SOG) was deposited with spin coating and baked on a hot plate at 180 oC. The substrate was annealed at 1000 oC in N2 for 30 min to perform solid phase diffusion. Then, SOG was removed by 1 % HF for 30min. For heavily-doped p-type SOI (p+ SOI), B+ ions were implanted into SOI layer. Activation was performed at 1000 oC in Ar for 30 min. SOI layer was patterned by chemical dry etching with CF4/O2. Thermal SiO2 was grown by dry oxidation at 900 oC for 10 min. Next, AlOx was deposited by RF sputtering. After contact opening with 1 % HF, Al (20 nm)/TiN (20 nm) were deposited by RF sputtering and lift-off for electrical contact to SOI. The substrates were subjected to annealing in forming gas at 420 oC for 30 min to improve the quality of gate dielectrics and electrical contact of gate pad. Al (10 nm)/Au (40nm) was deposited by thermal evaporation and lift-off for contact electrodes. Subsequently, the substrate was exposed to oxygen plasma to form hydroxyl groups on the surface of AlOx. Then, the substrate was immersed into 2-propanol containing 5 mM n-octadecylphosphonic acid (ODPA) for 6 hours at room temperature. Annealing was conducted at 100 oC in N2 for 30 min to stabilize ODPA. The gate dielectrics consists of hybrid ODPA/AlOx/SiO2. Mechanically exfoliated WS2 was transferred to the substrate with the PDMS elastomer. Finally, devices were annealed in N2 at 150 oC for 30 min to improve source/drain contact. The FET operation was observed for both n+ and p+ SOI gate. The threshold voltage (Vth) was evaluated by linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of 0.05 V. In the case of n+ SOI gate electrode, the Vth of -0.71 V, On/Off ratio of 103～104 and subthreshold slope (SS) of 150 mV/dec were evaluated. On the other hand, the Vth of -0.13 V, On/Off ratio of 103～104 and subthreshold slope (SS) of 107 mV/dec were obtained for p+ SOI gate electrode. The difference in Vth between n+ and p+ SOI gate electrodes is derived from the difference in the Fermi level of SOI. The proposed method is suited for research in electrical characteristics of various TMDC semiconductors.

This study reports the control of threshold voltage (Vth) by engineering a gate metal electrode in molybdenum disulfide (MoS2) field-effect transistors (FETs). The fabrication process for gate stacks involves the deposition of aluminum oxides (AlOx) on a high-work-function metal and the subsequent formation of a self-assembled monolayer (SAM) by an immersion method. A positive Vth of 0.15 V was demonstrated using a platinum (Pt) metal as a gate electrode accompanied by a low density of traps at the interface owing to the close-packed SAM. Raman spectroscopy revealed that the transferred MoS2 has a multi-layer structure. The Pt gate electrode exhibits a Vth shift of about 1 V in the positive direction compared with the aluminum (Al) gate electrode. This Vth shift is consistent with the difference in the work function of Pt and Al gate metal electrodes. The low–temperature process employed in this study makes it possible to assemble dissimilar materials including the Pt metal, deposited AlOx, and organic SA...

and a Proposal for Uniform LaSiON Gate Dielectric Formation Y. M. Lei, S. Munekiyo, T. Kawanago, K. Kakushima, K. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, M. Furuhashi, N. Miura, S. Yamakawa a Frontier Research Center, Tokyo Institute of Technology, Yokohama, Japan Email: yimgin.l.aa@m.titech.ac.jp b Department of Electronics and Applied Physics, Tokyo Institute of Technology, Yokohama, Japan c Mitsubishi Electric Corp., Amagasaki, Japan

We experimentally examine the effective mobility in nMOSFETs with La"2O"3 gate dielectrics without SiO"x-based interfacial layer. The reduced mobility is mainly caused by fixed charges in High-k gate dielectrics and the contribution of the interface state density is approximately 30% at N"s=5x10^1^1cm^-^2 in the low 10^1^1cm^-^2eV^-^1 order. It is considered that one of the effective methods for improving mobility is to utilize La-silicate layer formed by high temperature annealing. However, there essentially exists trade-off relationship between high temperature annealing and small EOT.

The flat band voltage shifts of HfO 2 /SiO 2 /nSi capacitors with ultra-thin La 2 O 3 insertion at HfO 2 /SiO 2 interface have been confirmed using hard X-ray photoelectron spectroscopy (HX-PES). By increasing the amount of La 2 O 3 insertion, the binding energy of Si 1s core spectra increases, which means that the surface potential of Si substrate also increases. A voltage drop difference of HfO 2 and La 2 O 3 at SiO 2 interface can be estimated to be 0.40 V.

Metal induced effects on electrical characteristics in AlGaN/GaN Schottky HEMT are reported. Focus is given to the collapse of drain current attributed to Schottky metal. Of particular interest for discussion is that TiN gate can suppresses the collapse of drain current compared with conventional Ni gate. Nitrogen concentrations in TiN gate are found to be correlated to the current collapse, indicating that the nitrogen vacancy is responsible for the traps in AlGaN/GaN HEMT. The reduction in a concentration gradient of nitrogen should be accomplished for preventing the formation of the traps. Because of the metal dependent collapse of the drain current, the traps are considered to be formed under the gate edge on the drain side in AlGaN layer.

La-silicate/Si interface were investigated by measuring C-V characteristics and infra-red absorbance spectra. Interface state density (D it ) down to 1010 cm−2/eV was obtained by annealing at temperature over 800 °C. A red-shift due to Si-O-Si LO phonon toward 1250 cm−1 was found. We speculate that relaxation of SiO 4 networks in Lasilicates results in low D it .

A simple analytic model for the post-breakdown conduction characteristics in W/La2O3/p-type Si MOSFETs is reported. The model is based on the solution of the generalized diode equation and captures the behavior of the gate current (IG) as a function of the gate (VG) and drain (VD) voltages including both positive and negative biases. The devices were subjected to ramped voltage stress so as to induce the dielectric breakdown close to or at the transistor drain region.

Graphical abstractDisplay Omitted We model the effects of an oxide breakdown on the transistor behaviour.We consider the potentiometer model.We show how the relevant feature that characterize the dielectric breakdown affect the transistor's transconductances. In this work, the effects of a gate-to-channel dielectric breakdown on the output characteristics of advanced La2O3-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are investigated. The electrical behaviour is modeled using a potentiometer-like resistor network. It is shown how the relevant features that characterize a breakdown event in an MOS transistor: location of the failure site along the device channel, post-breakdown oxide resistance, and post-breakdown channel resistance, affect the mutual and drain transconductances of the device. The connection with the nonlinear current source model for broken down transistors is also discussed.