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Angular single-event (SE) mechanisms and experimental upset data for 14-/16-nm bulk fin field-effect transistor (FinFET) technologies are presented and analyzed. The discrete structure of FinFETs introduces unique geometrical and orientation dependences for angular SE mechanisms and SE upset (SEU) responses of FinFET circuits. Geometric analyses and 3-D technology computer-aided design results effectively explain the angular mechanisms behind experimentally observed SE crosssectional responses. Results show that angular SEU crosssectional characteristics can be attributed to the proportional contributions of charge deposition regions in the fin structure and the subfin bulk substrate. [ABSTRACT FROM PUBLISHER]

A set of upset criteria based on circuit characteristic switching time frame is developed and used to bridge transistor-level TCAD simulations to circuit-level single-event (SE) upset cross sections for advanced (fast and small) digital circuits. Interpretation of the measured and 3D TCAD simulated single-event upset (SEU) responses of bulk planar circuits and bulk FinFET circuits using the short-time based upset criteria quantitatively explains the observed divergence of low-LET FinFET cross sections from simple geometric scaling predictions. Comparisons of measured and computed single-event cross section responses show excellent agreement. [ABSTRACT FROM PUBLISHER]

Heavy-ion experimental results were used to characterize single-event upset trends in 16 nm bulk FinFET, 20 nm bulk planar, and 28 nm bulk planar D flip-flops. Experimental data show that 16 nm bulk FinFET flip-flops have considerably lower SEU cross sections than their sub-32 nm planar counterparts for linear energy transfer (LET) less than 10~\MeV-cm^2/\mg. However, FinFET SEU cross section improvement compared to the planar technologies is weak for high LET particles. Three-dimensional technology computer-aided design simulations are used to investigate charge collection mechanisms and single-event transient (SET) pulse widths at these advanced fabrication nodes. Simulation results show that SETs follow conventional scaling trends, which are that SET pulse widths reduce with technology scaling. [ABSTRACT FROM AUTHOR]

A new error correction circuit (ECC) for delay-locked loops (DLLs) using combinational logic and a “peeled” voltage-controlled delay line (VCDL) layout is proposed. The ECC can be used to mitigate missing output pulses due to single-event effects in scaled CMOS processes. The implementation of the ECC results in no significant area penalty or performance degradation of the DLL. Simulations at LETs up to 100~\MeV\-\cm^2/\mg show that the ECC mitigates missing pulses in DLLs fabricated at features sizes down to 40 nm and operating frequencies up to 1 GHz. In addition, any ion strike within the error correction logic components will have no significant impact on the DLL output signal. Emulated results obtained through an FPGA implementation of the ECC demonstrate the effectiveness and portability of the hardening technique. [ABSTRACT FROM PUBLISHER]

A novel “quad-path” radiation hardening technique is implemented in a switched-capacitor sample/hold amplifier and validated by laser testing. The proposed technique eliminates the signal-range limitations of the original dual-path hardening technique by using both n- and p-type switches with separate dual and complementary signal paths. Single-event effect sample errors are reduced by up to 90%, with minimal speed, power and area penalties. [ABSTRACT FROM PUBLISHER]

Negative bias temperature instability has been experimentally demonstrated to increase the cross-section of the single event response for 40 nm flip-flops. Analysis on the underlying mechanisms, including threshold voltage shift, is presented. [ABSTRACT FROM AUTHOR]

Perturbations in N-well potential have been shown to strongly affect the charge collection, charge sharing, and parasitic bipolar transistor characteristics. In this paper, temporal and spatial characteristics of the well-potential modulation are characterized through 3-D TCAD simulations. Effects of well-contact layout, ion energy, and technology process parameters for a 90-nm bulk CMOS process are investigated. [ABSTRACT FROM PUBLISHER]

Heavy-ion experiments on spatially isolated inverters and densely populated inverters demonstrate the effects of transistor density on single-event (SE) transients in bulk CMOS. Increased transistor density reduces SE cross section dramatically while having little impact on transient pulse width. [ABSTRACT FROM PUBLISHER]

Heavy-ion data from a 130-nm bulk CMOS process shows a counterproductive result in using a common single-event charge collection mitigation technique. Guard bands, which are well contacts that surround individual transistors, can reduce single-event pulsewidths for normal strikes, but increase them for angled strikes. Calibrated 3-D TCAD mixed-mode modeling has identified a multiple-transistor charge collection mechanism that explains the experimental data, namely that angled strikes result in charge collection in the normally ON device that increases the restoring current on the struck device. [ABSTRACT FROM PUBLISHER]

A layout technique that exploits single-event transient pulse quenching to mitigate transients in combinational logic is presented. TCAD simulations show as much as 60% reduction in sensitive area and 70% reduction in pulse width for some logic cells. [ABSTRACT FROM AUTHOR]

A radiation-hardened-by-design (RHBD) voltage- controlled delay line (VCDL) for single-event mitigation in delay-locked loops (DLLs) is proposed. A modified fully differential delay cell topology is used to harden the VCDL, resulting in a dramatic reduction of the missing pulses generated by the DLL after an ion strike. By increasing the width-to-length ratios of the feedback transistors of the VCDL delay cells, this topology provides substantially reduced single-event errors while maintaining high operating frequency, wide tuning range and small area penalty. [ABSTRACT FROM AUTHOR]

A first-order linear model is formulated in closed-form for the examination of transient propagation through charge pump phase-locked loops (PLL). As a result, a novel PLL design parameter-the PLL critical time constant-is discovered as the primary factor influencing extraneous transient generation and propagation through the PLL independent of technology node. Various simulations and experiments have been performed on PLL circuits designed in 130 nm and 90 nm technology nodes. Using the described simulation and laser two-photon absorption (TPA) techniques, the generalized model is shown to accurately predict the output phase displacements and critical time constant of the PLL following transient perturbations, validating the analytical results independent of technology and without the need for calibration parameters. Moreover, the characteristic critical time constant is shown to be valuable for identifying and evaluating the single-event vulnerabilities in charge pump PLL designs. [ABSTRACT FROM PUBLISHER]

Single-event transients (SET) are analyzed in integer-N frequency dividers configured internal and external to a closed-loop phase-locked ioop (PLL) circuit. Simulations, corroborated by experimental results, indicate that the location and gain of the frequency divider in any PLL arrangement strongly influence both the error rate of the PLL circuit and the propagation of transients through the closed-loop. The probability of an ion-strike causing output phase displacement values on the order of the operating-period can be significantly reduced by increasing the divisor of the stand-alone output frequency divider. Conversely, increasing the feedback divisor is shown to magnify SETs propagating through the closed-loop PLL. [ABSTRACT FROM AUTHOR]

A voltage-controlled-oscillator (VCO) circuit has been designed for radiation-hardened-by-design (RHBD) single-event transient (SET) mitigation. The RHBD technique, which can be readily implemented in mixed-signal phase-locked loops and delay-locked loops, is shown to substantially improve the single-event performance of the VCO while decreasing the RMS phase jitter due to power supply noise. Additionally, using the probabilistic analysis technique presented, the RHBD VCO shows a maximally improved SET response over that of the conventional VCO, decreasing the output phase displacement to below the nominal phase jitter. [ABSTRACT FROM PUBLISHER]

A radiation-hardened-by-design (RHBD) technique is described for reducing errors due to single-event effects at the floating input nodes of a switched-capacitor comparator. The technique is shown to significantly outperform the alternative ldquobrute forcerdquo design choice of increasing capacitor size. [ABSTRACT FROM PUBLISHER]

Frequency domain analysis is shown to be useful for quantifying the single-event vulnerability of a mixed-signal circuit. Frequency domain single-event analysis is demonstrated for different pipelined analog-to-digital converter topologies. Design tradeoffs of comparator redundancy are evaluated using a signal-to-noise ratio metric. [ABSTRACT FROM PUBLISHER]

Mixed mode simulations and heavy-ion experiments indicate the presence of multinode charge collection in advanced technologies. For logic circuits, such charge collection may result in concatenation of transients, extending the width of SETs. Mixed-mode simulations of a 4-bit adder circuit indicate that the increase in SET pulse width due to two-node charge collection can be as high as 75%. An analytical model for the increase in the SET width is developed showing the increase in SET width is proportional to the width of the individual transients, the relative delay between charge collection nodes, and the circuit topology. [ABSTRACT FROM PUBLISHER]

A built-in self-test technique for testing digital logic circuits for single-events has been developed. The BIST technique can be used for single-event testing in any conventional laboratory to evaluate the circuit level response to SEs. Experimental and simulation results for multiple technology nodes show the feasibility of this approach to test circuits, with the added advantages of reduced testing time and cost. [ABSTRACT FROM PUBLISHER]

The floating amplifier inputs in switched-capacitor differential circuits are identified as extremely vulnerable to single events. A radiation hardened by design mitigation technique is presented. The vulnerability of the floating inputs is improved by an order of magnitude with negligible penalties in area, power, speed and noise performance. [ABSTRACT FROM AUTHOR]

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths produced by heavy ions for circuits with isolated contacts and for circuits with guard bands combined with larger contacts in a 130-nm process using an autonomous characterization technique. Heavy-ion test results indicate that controlling the well potential by using guard bands, along with high density well contacts, helps eliminate of SETs longer than 1 ns. [ABSTRACT FROM PUBLISHER]

Single-event transients (SETs) affecting a single side of a differential data path have been shown to cause signal degradation and data loss. A radiation hardened by design (RHBD) transistor layout technique is demonstrated that promotes charge collection on both sides of the differential data path. The induced common-mode error voltage is suppressed by the differential circuit, significantly reducing the SET amplitude. [ABSTRACT FROM AUTHOR]

Radiation effects on four common DC linear voltage regulators are investigated. Increasing total dose is shown to degrade converter regulation by degrading the loop gain and phase response. Regulator single event transient (SET) response is characterized, and a mitigation technique is proposed. Shunt regulator topologies are found to be superior to series regulator topologies in terms of radiation tolerance. [ABSTRACT FROM AUTHOR]

Watermarking is the embedding of data in a medium for ownership, verification, distribution tracking, authentication, copyright protection, and data hiding. It has been well studied for use in digital media such as in audio, digital images and video. In this work, watermarking is extended to the realm of computer-aided design (CAD) for physical design of integrated circuits (IC's) in order to protect and facilitate re-use of intellectual property (IP) blocks (circuitry). As designs become more complex and cycle times shorter, the re-use of IP blocks is becoming more and more important. However, in order to aid in this re-use, improved methods of securing and tracking ownership need to be in place. Watermarking these valuable design blocks, whether custom transistors or standard cells, is shown to be a practical method of securing ownership of the property, even after local perturbations in the design. A method of watermarking circuit elements in both fully-custom analog or digital macrocell designs as well as analog or digital standard cell based designs is presented. This protection scheme thus applies to analog, digital, and mixed signal designs, with the only exception being that of a gate array implemented circuits. [ABSTRACT FROM AUTHOR]

Presents information as it relates to the fabrication of an integrated noise source (INS) in a standard 1.2 m digital CMOS technology. How wideband noise is generated; Details on the INS; Inclusions in the potential applications of the INS.