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We report a comprehensive study on a layered-structure compound of NaZn4As3, which has been predicted to be an ideal topological semimetal (TSM) candidate. It is found that NaZn4As3 undergoes a structural transformation from high temperature rhombohedral to a low temperature monoclinic phase. The electric resistivity exhibits a metal-to-insulator-like transition at around 100 K, and then develops a plateau at low temperature, which might be related to the protected topologically conducting surface states. Our first-principles calculation confirms further that NaZn4As3 is a topological insulator (TI) for both different phases rather than a previously proposed TSM. The Hall resistivity reveals that the hole carriers dominate the transport properties for the whole temperature range investigated. Furthermore, an obvious kink possibly associated to the structure transition has been detected in thermopower around ~ 170 K. The large thermopower and moderate κ indicate that NaZn4As3 and /or its derivatives can provide a good platform for optimizing and studying the thermoelectric performance.

Based on the charge balance principle, an optimal impurity distribution variation of lateral doping termination (OID-VLD) and its ion-injection mask design method are proposed and verified. The comparative simulations and experiments show that OID-VLD can achieve better blocking ability and reliability than the traditional VLD (T-VLD). Vertical double diffusion MOSFET (VDMOS) with OID-VLD achieved breakdown voltage (BV) of 1684 V and passed the 168 hours 100 °C–110 °C–120 °C–125 °C high-temperature reverse bias (HTRB) test, while VDMOS with T-VLD obtained BV of 1636 V and failed in the 20 hours 120 °C HTRB test.

We propose a novel high performance carrier stored trench bipolar transistor (CSTBT) with dual shielding structure (DSS-CSTBT). The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface, in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it. Compared with the conventional CSTBT (con-CSTBT), the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage (BV), but also well reduces the gate-collector capacitance C GC, gate charge Q G, and turn-off loss E OFF of the device. Furthermore, lower turn-on loss E ON and gate drive loss E DR are also obtained. Simulation results show that with the same CS layer doping concentration N CS = 1.5 × 1016 cm−3, the BV increases from 1312 V of the con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate (T og2) of 1 μm. Moreover, compared with the con-CSTBT, the C GC at V CE of 25 V and miller plateau charge (Q GC) for the proposed DSS-CSTBT with T og2 of 1 μm are reduced by 79.4% and 74.3%, respectively. With the V GE increases from 0 V to 15 V, the total Q G for the proposed DSS-CSTBT with T og2 of 1 μm is reduced by 49.5%. As a result, at the same on-state voltage drop (V CEON) of 1.55 V, the E ON and E OFF are reduced from 20.3 mJ/cm2 and 19.3 mJ/cm2 for the con-CSTBT to 8.2 mJ/cm2 and 9.7 mJ/cm2 for the proposed DSS-CSTBT with T og2 of 1 μm, respectively. The proposed DSS-CSTBT not only significantly improves the trade-off relationship between the V CEON and E OFF but also greatly reduces the E ON.

The original variational quantum eigensolver (VQE) typically minimizes energy with hybrid quantum-classical optimization that aims to find the ground state. Here, we propose a VQE based on minimizing energy variance and call it the variance-VQE, which treats the ground state and excited states on the same footing, since an arbitrary eigenstate for a Hamiltonian should have zero energy variance. We demonstrate the properties of the variance-VQE for solving a set of excited states in quantum chemistry problems. Remarkably, we show that optimization of a combination of energy and variance may be more efficient to find low-energy excited states than those of minimizing energy or variance alone. We further reveal that the optimization can be boosted with stochastic gradient descent by Hamiltonian sampling, which uses only a few terms of the Hamiltonian and thus significantly reduces the quantum resource for evaluating variance and its gradients.

An n-GaO x thin film is deposited on a single-crystal boron-doped diamond by RF magnetron sputtering to form the pn heterojunction. The n-GaO x thin film presents a small surface roughness and a large optical band gap of 4.85 eV. In addition, the band alignment is measured using x-ray photoelectron spectroscopy to evaluate the heterojunction properties. The GaO x /diamond heterojunction shows a type-II staggered band configuration, where the valence and conduction band offsets are 1.28 eV and 1.93 eV, respectively. These results confirm the feasibility of the use of n-GaO x as a termination structure for diamond power devices.

Space radiation with inherently broadband spectral flux poses a huge danger to astronauts and electronics on aircraft, but it is hard to simulate such feature with conventional radiation sources. Using a tabletop laser-plasma accelerator, we can reproduce exponential energy particle beams as similar as possible to these in space radiation. We used such an electron beam to study the electron radiation effects on the surface structure and performance of two-dimensional material (FePS3). Energetic electron beam led to bulk sample cleavage and damage between areas of uneven thickness. For the FePS3 sheet sample, electron radiation transformed it from crystalline state to amorphous state, causing the sample surface to rough. The full widths at the half maximum of characteristic Raman peaks became larger, and the intensities of characteristic Raman peaks became weak or even disappeared dramatically under electron radiation. This trend became more obvious for thinner samples, and this phenomenon was attributed to the cleavage of P–P and P–S bonds, destabilizing the bipyramid structure of [P2S6]4– unit. The results are of great significance for testing the maximum allowable radiation dose for the two-dimensional material, implying that FePS3 cannot withstand such energetic electron radiation without an essential shield.

We utilize three parallel reservoir computers using semiconductor lasers with optical feedback and light injection to model radar probe signals with delays. Three radar probe signals are generated by driving lasers constructed by a three-element laser array with self-feedback. The response lasers are implemented also by a three-element lase array with both delay-time feedback and optical injection, which are utilized as nonlinear nodes to realize the reservoirs. We show that each delayed radar probe signal can be predicted well and to synchronize with its corresponding trained reservoir, even when parameter mismatches exist between the response laser array and the driving laser array. Based on this, the three synchronous probe signals are utilized for ranging to three targets, respectively, using Hilbert transform. It is demonstrated that the relative errors for ranging can be very small and less than 0.6%. Our findings show that optical reservoir computing provides an effective way for applications of target ranging.

We report the transport properties of a topological insulator candidate, LiMgBi. The electric resistivity of the title compound exhibits a metal-to-semiconductor-like transition at around 160 K and tends to saturation below 50 K. At low temperatures, the magnetoresistance is up to ∼260 % at 9 T and a clear weak antilocalization effect is observed in the low magnetic-field region. The Hall measurement reveals that LiMgBi is a multiband system, where hole-type carriers (n h ∼ 1018 cm−3) play a major role in the transport process. Remarkably, LiMgBi possess a large Seebeck coefficient ∼440 μV/K) and a moderate thermal conductivity at room temperature, which indicate that LiMgBi is a promising candidate in thermoelectric applications.

A new scheme is proposed to improve the electron beam quality of ionization-induced injection by tailoring gas profile in laser wakefield acceleration. Two-dimensional particle-in-cell simulations show that the ionization-induced injection mainly occurs in high-density stage and automatically truncates in low-density stage due to the decrease of wakefield potential difference. The beam loading can be compensated by the elongated beam resulting from the density transition stage. The beam quality can be improved by shorter injection distance and beam loading effect. A quasi-monoenergetic electron beam with a central energy of 258 MeV and an energy spread of 5.1% is obtained under certain laser-plasma conditions.

We present detailed investigations of structural and static/dynamic magnetic properties of hydrogenated hcp-Co80 57Fe4Ir16 soft magnetic thin films. Two different kinds of defects, i.e., destructive and non-destructive, were demonstrated by controlling the negative bias voltage of the hydrogenation process. Our results show that the structure and magnetic properties of our sample can be tuned by the density of the induced defects. These results provide better understanding of the hydrogenation effect and thus can be used in the future for materials processing to meet the requirements of different devices.

In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis (ΔV th,sub) of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs), 4H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal–oxide-semiconductor (MOS) capacitors are fabricated and characterized. Compared with planar MOSFEF, the trench MOSFET shows hardly larger ΔV th,sub in wide temperature range from 25 °C to 300 °C. When operating temperature range is from 25 °C to 300 °C, the off-state negative V gs of planar and trench MOSFETs should be safely above –4 V and –2 V, respectively, to alleviate the effect of ΔV th,sub on the normal operation. With the help of P-type planar and trench MOS capacitors, it is confirmed that the obvious ΔV th,sub of 4H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level (E i) and valence band (E v). The maximum ΔV th,sub of trench MOSFET is about twelve times larger than that of planar MOSFET, owing to higher density of interface states (D it) between E i and E v. These research results will be very helpful for the application of 4H-SiC MOSFET and the improvement of ΔV th,sub of 4H-SiC MOSFET, especially in 4H-SiC trench MOSFET.

We study the dynamics of single electron in an inhomogeneous cylindrical plasma channel during the direct acceleration by linearly polarized chirped laser pulse. By adjusting the parameters of the chirped laser pulse and the plasma channel, we obtain the energy gain, trajectory, dephasing rate and unstable threshold of electron oscillation in the channel. The influences of the chirped factor and inhomogeneous plasma density distribution on the electron dynamics are discussed in depth. We find that the nonlinearly chirped laser pulse and the inhomogeneous plasma channel have strong coupled influence on the electron dynamics. The electron energy gain can be enhanced, the instability threshold of the electron oscillation can be lowered, and the acceleration length can be shortened by chirped laser, while the inhomogeneity of the plasma channel can reduce the amplitude of the chirped laser.

We present a new charge trapping memory (CTM) device with the Au/Ga2O3/SiO2/Si structure, which is fabricated by using the magnetron sputtering, high-temperature annealing, and vacuum evaporation techniques. Transmission electron microscopy diagrams show that the thickness of the SiO2 tunneling layer can be controlled by the annealing temperature. When the devices are annealed at 760 °C, the measured C–V hysteresis curves exhibit a maximum 6 V memory window under a ±13 V sweeping voltage. In addition, a slight degradation of the device voltage and capacitance indicates the robust retention properties of flat-band voltage and high/low state capacitance. These distinctive advantages are attributed to oxygen vacancies and inter-diffusion layers, which play a critical role in the charge trapping process.

A novel silicon controlled rectifier (SCR) with high holding voltage ( for electrostatic discharge (ESD) protection is proposed and investigated in this paper. The proposed SCR obtains high by adding a long N+ layer (LN+) and a long P+ layer (LP+), which divide the conventional low voltage trigger silicon controlled rectifier (LVTSCR) into two SCRs (SCR1: P+/Nwell/Pwell/N+ and SCR2: P+/LN+/LP+/N+) with a shared emitter. Under the low ESD current (, the two SCRs are turned on at the same time to induce the first snapback with high (. As the increases, the SCR2 will be turned off because of its low current gain. Therefore, the will flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high (. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like (Transmission Line Pulse-like) simulation. An optimized of 7.4 V with a maximum failure current ( of 14.7 mA/ is obtained by the simulation.

Due to its high computational efficiency and ability to consider nonparallel and nonlinear effects, nonlinear parabolized stability equations (NPSE) approach has been widely used to study the stability and transition mechanisms. However, it often diverges in hypersonic boundary layers when the amplitude of disturbance reaches a certain level. In this study, an improved algorithm for solving NPSE is developed. In this algorithm, the mean flow distortion is included into the linear operator instead of into the nonlinear forcing terms in NPSE. An under-relaxation factor for computing the nonlinear terms is introduced during the iteration process to guarantee the robustness of the algorithm. Two case studies, the nonlinear development of stationary crossflow vortices and the fundamental resonance of the second mode disturbance in hypersonic boundary layers, are presented to validate the proposed algorithm for NPSE. Results from direct numerical simulation (DNS) are regarded as the baseline for comparison. Good agreement can be found between the proposed algorithm and DNS, which indicates the great potential of the proposed method on studying the crossflow and streamwise instability in hypersonic boundary layers.

An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (Qntop) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

A more reasonable trial ground state wave function is constructed for the relative motion of an interacting two-fermion system in a one-dimensional (1D) harmonic potential. At the boundaries both the wave function and its first derivative are continuous and the quasi-momentum is determined by a more practical constraint condition which associates two variational parameters. The upper bound of the ground state energy is obtained by applying the variational principle to the expectation value of the Hamiltonian of relative motion on the trial wave function. The resulted energy and wave function show better agreement with the analytical solution than the original proposal.

A novel substrate trigger semiconductor control rectifier-laterally diffused metal–oxide semiconductor (STSCR-LDMOS) stacked structure is proposed and simulated using the transimission line pulser (TLP) multiple-pulse simulation method in a 0.35-μm, 60-V biploar-CMOS-DMOS (BCD) process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metal–oxide semiconductor (SCR-LDMOS) in high-voltage electro-static discharge (ESD) protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

In this study, the bidirectional reflectance distribution function (BRDF) of a one-dimensional conducting rough surface and a dielectric rough surface are calculated with different frequencies and roughness values in the microwave band by using the method of moments, and the relationship between the bistatic scattering coefficient and the BRDF of a rough surface is expressed. From the theory of the parameters of the rough surface BRDF, the parameters of the BRDF are obtained using a genetic algorithm. The BRDF of a rough surface is calculated using the obtained parameter values. Further, the fitting values and theoretical calculations of the BRDF are compared, and the optimization results are in agreement with the theoretical calculation results. Finally, a reference for BRDF modeling of a Gaussian rough surface in the microwave band is provided by the proposed method.

A novel high performance trench field stop (TFS) superjunction (SJ) insulated gate bipolar transistor (IGBT) with a buried oxide (BO) layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT (Conv-SJ), the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop (Vce(on)) and an improved tradeoff between Vce(on) and turn-off loss (Eoff), with no breakdown voltage (BV) degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5 μm and Nn = Np = 3 × 10 cm−3, the Vce(on) and Eoff of the proposed structure are 1.08 V and 2.81 mJ/cm2 with the collector doping concentration Nc = 1 × 1018 cm−3 and 1.12 V and 1.73 mJ/cm2 with Nc = 5 × 1017 cm−3, respectively. However, with the same device parameters, the Vce(on) and Eoff for the Conv-SJ are 1.81 V and 2.88 mJ/cm2 with Nc = 1 × 1018 cm−3 and 1.98 V and 2.82 mJ/cm2 with Nc = 5 × 10 cm−3, respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.

A low specific on-resistance SOI LDMOS with a novel junction field plate (JFP) is proposed and investigated theoretically. The most significant feature of the JFP LDMOS is a PP—N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buried oxide layer (BOX) and thus widens the vertical conduction area. As a result, the breakdown voltage (BV) is improved and the specific on-resistance (Ron,sp) is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩcm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.

An analysis model of the dV/dt capability for a metal—oxide—semiconductor (MOS) controlled thyristor (MCT) is developed. It is shown that, in addition to the P-well resistance reported previously, the existence of the OFF-FET channel resistance in the MCT may degrade the dV/dt capability. Lower P-well and N-well dosages in the MCT are useful in getting a lower threshold voltage of OFF-FET and then a higher dV/dt immunity. However, both dosages are restricted by the requirements for the blocking property and the forward conduction capability. Thus, a double variable lateral doping (DVLD) technique is proposed to realize a high dV/dt immunity without any sacrifice in other properties. The accuracy of the developed model is verified by comparing the obtained results with those from simulations. In addition, this DVLD MCT features mask-saving compared with the conventional MCT fabrication process. The excellent device performance, coupled with the simple fabrication, makes the proposed DVLP MCT a promising candidate for capacitor discharge applications.

This paper describes the successful fabrication of 4H-SiC junction barrier Schottky (JBS) rectifiers with a linearly graded field limiting ring (LG-FLR). Linearly variable ring spacings for the FLR termination are applied to improve the blocking voltage by reducing the peak surface electric field at the edge termination region, which acts like a variable lateral doping profile resulting in a gradual field distribution. The experimental results demonstrate a breakdown voltage of 5 kV at the reverse leakage current density of 2 mA/cm2 (about 80% of the theoretical value). Detailed numerical simulations show that the proposed termination structure provides a uniform electric field profile compared to the conventional FLR termination, which is responsible for 45% improvement in the reverse blocking voltage despite a 3.7% longer total termination length.

A novel single order diffraction grating in the soft X-ray region, called quasi-random radius pinhole array spectroscopic photon sieves (QRSPS), is proposed in this paper. This new grating is composed of pinholes on a substrate, whose radii are quasi-random, while their centers are regular. Analysis proves that its transmittance function across the grating bar is similar to that of sinusoidal transmission gratings. Simulation results show that the QRSPS can suppress higher-order diffraction effectively. And the QRSPS would still retain its characteristic of single order diffraction when we take the effect of X-ray penetration into account. These properties indicate that the QRSPS can be used in the soft X-ray spectra measurement.

A novel low specific on-resistance (Ron,sp) lateral double-diffused metal oxide semiconductor (LDMOS) with a buried improved super-junction (BISJ) layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage (BV). The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 m??cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 ?m, respectively.

A novel reverse-conducting insulated-gate bipolar transistor (RC-IGBT) featuring a floating P-plug is proposed. The P-plug is embedded in the n-buffer layer to obstruct the electron current from flowing directly to the n-collector, which achieves the hole emission from the p-collector at a small collector size and suppresses the snapback effectively. Moreover, the current is uniformly distributed in the whole wafer at both IGBT mode and diode mode, which ensures the high temperature reliability of the RC-IGBT. Additionally, the P-plug acts as the base of the N-buffer/P-float/N-buffer transistor, which can be activated to extract the excessive carriers at the turn-off process. As the the simulation results show, for the proposed RC-IGBT, it achieves almost snapback-free output characteristics with a uniform current density and a uniform temperature distribution, which can greatly increase the reliability of the device.

A new silicon-on-insulator (SOI) power lateral MOSFET with a dual vertical field plate (VFP) in the oxide trench is proposed. The dual VFP modulates the distribution of the electric field in the drift region, which enhances the internal field of the drift region and increases the drift doping concentration of the drift region, resulting in remarkable improvements in breakdown voltage (BV) and specific on-resistance (Ron,sp). The mechanism of the VFP is analyzed and the characteristics of BV and Ron,sp are discussed. It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V, and the Ron,sp decreases from 366 mΩcm2 to 110 mΩcm2.

In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor (DGDI LTIGBT) structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp, but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 Acm−2 with a small half-cell pitch of 10.5 μm, a specific on-resistance Ron,sp of 187 mΩmm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.

A novel super-junction lateral double-diffused metal—oxide semiconductor (SJ-LDMOS) with a partial lightly doped P pillar (PD) is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P− junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage (BV). In addition, due to the same conduction paths, the specific on-resistance (Ron,sp) of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.

A novel low specific on-resistance (Ron,sp) silicon-on-insulator (SOI) p-channel lateral double-diffused metal—oxide semiconductor (pLDMOS) compatible with high voltage (HV) n-channel LDMOS (nLDMOS) is proposed. The pLDMOS is built in the N-type SOI layer with a buried P-type layer acting as a current conduction path in the on-state (BP SOI pLDMOS). Its superior compatibility with the HV nLDMOS and low voltage (LV) complementary metal-oxide semiconductor (CMOS) circuitry which are formed on the N-SOI layer can be obtained. In the off-state the P-buried layer built in the N-SOI layer causes multiple depletion and electric field reshaping, leading to an enhanced (reduced) surface field (RESURF) effect. The proposed BP SOI pLDMOS achieves not only an improved breakdown voltage (BV) but also a significantly reduced Ron,sp. The BV of the BP SOI pLDMOS increases to 319 V from 215 V of the conventional SOI pLDMOS at the same half cell pitch of 25 μm, and Ron,sp decreases from 157 mΩ·cm2 to 55 mΩ·cm2. Compared with the PW SOI pLDMOS, the BP SOI pLDMOS also reduces the Ron,sp by 34% with almost the same BV.

A new high voltage trench lateral double-diffused metal—oxide semiconductor (LDMOS) with ultra-low specific on-resistance (Ron,sp) is proposed. The structure features a dual gate (DG LDMOS): a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce Ron,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage (BV). Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, Ron,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench (HK TG VDMOS) is proposed in this paper. The HK TG VDMOS features a high-k (HK) trench below the trench gate. Firstly, the extended HK trench not only causes an assistant depletion of the n-drift region, but also optimizes the electric field, which therefore reduces Ron,sp and increases the breakdown voltage (BV). Secondly, the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration. Thirdly, compared with the superjunction (SJ) vertical double-diffused metal-oxide semiconductor (VDMOS), the new device is simplified in fabrication by etching and filling the extended trench. The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩcm2 is obtained by simulation; its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%, in comparison with those of the conventional trench gate VDMOS (TG VDMOS) and conventional superjunction trench gate VDMOS(SJ TG CDMOS).

A high voltage (> 600 V) integrable silicon-on-insulator (SOI) trench-type lateral insulated gate bipolar transistor (LIGBT) with a reduced cell-pitch is proposed. The LIGBT features multiple trenches (MTs): two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX). Firstly, the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si. Secondly, oxide trenches bring in multi-directional depletion, leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field (RESURF) effect. Both increase the breakdown voltage (BV). Thirdly, oxide trenches fold the drift region around the oxide trenches, leading to a reduced cell-pitch. Finally, the oxide trenches enhance the conductivity modulation, resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop (Von). The oxide trenches cause a low anode?cathode capacitance, which increases the switching speed and reduces the turn-off energy loss (Eoff). The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 ?m, a Von of 1.03 V at 100 A/cm?2, a turn-off time of 250 ns and Eoff of 4.1?10?3 mJ. The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits, simplifying the fabrication processes.

We present a novel numerical model and simulate preliminarily the charging process of a polymer subjected to electron irradiation of several 10 keV. The model includes the simultaneous processes of electron scattering and ambipolar transport and the influence of a self-consistent electric field on the scattering distribution of electrons. The dynamic spatial distribution of charges is obtained and validated by existing experimental data. Our simulations show that excess negative charges are concentrated near the edge of the electron range. However, the formed region of high charge density may extend to the surface and bottom of a kapton sample, due to the effects of the electric field on electron scattering and charge transport, respectively. Charge trapping is then demonstrated to significantly influence the charge motion. The charge distribution can be extended to the bottom as the trap density decreases. Charge accumulation is therefore balanced by the appearance and increase of leakage current. Accordingly, our model and numerical simulation provide a comprehensive insight into the charging dynamics of a polymer irradiated by electrons in the complex space environment.

In this paper, we present a monolithic integration of a self-protected AlGaN/GaN metal—insulator field-effect transistor (MISFET). An integrated field-controlled diode on the drain side of the AlGaN/GaN MISFET features a self-protected function for a reverse bias. This diode takes advantage of the recessed-barrier enhancement-mode technique to realize an ultra-low voltage drop and a low turn-ON voltage. In the smart monolithic integration, this integrated diode can block a reverse bias (> 70 V/μm) and suppress the leakage current (< 5 × 10−11 A/mm). Compared with conventional monolithic integration, the numerical results show that the MISFET integrated with a field-controlled diode leads to a good performance for smart power integration. And the power loss is lower than 50% in conduction without forward current degeneration.

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon on insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.

A novel high-voltage light punch-through (LPT) carrier stored trench bipolar transistor (CSTBT) with buried p-layer (BP) is proposed in this paper. Since the negative charges in the BP layer modulate the bulk electric field distribution, the electric field peaks both at the junction of the p base/n-type carrier stored (N-CS) layer and the corners of the trench gates are reduced, and new electric field peaks appear at the junction of the BP layer/N− drift region. As a result, the overall electric field in the N− drift region is enhanced and the proposed structure improves the breakdown voltage (BV) significantly compared with the LPT CSTBT. Furthermore, the proposed structure breaks the limitation of the doping concentration of the N—CS layer (NN—CS) to the BV, and hence a higher NN—CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop (Vce(sat)) can be obtained with almost constant BV. The results show that with a BP layer doping concentration of NBP = 7 × 1015 cm−3, a thickness of LBP = 2.5 μm, and a width of WBP = 5 μm, the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V, with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3. However, with the same N−-drift region thickness of 150 μm and NN—CS, the BV of the CSTBT decreases from 1598 V to 247 V. Meanwhile, the Vce(sat) of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3.

In the present work, vertically aligned ZnO nanorod arrays with tunable size are successfully synthesized on nonseeded ITO glass substrates by a simple electrodeposition method. The effect of growth conditions on the phase, morphology, and orientation of the products are studied in detail by X-ray diffraction (XRD), scanning electron microscopy (SEM), and transmission electron microscopy (TEM). It is observed that the as-prepared nanostructures exhibit a preferred orientation along c axis, and the size and density of the ZnO nanorod can be controlled by changing the concentration of ZnCl2. Field emission properties of the as-synthesized samples with different diameters are also studied, and the results show that the nanorod arrays with a smaller diameter and appropriate rod density exhibit better emission properties. The ZnO nanorod arrays show a potential application in field emitters.

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage (BV) for an ultra-high-voltage (UHV) high-side thin layer silicon-on-insulator (SOI) p-channel lateral double-diffused metal-oxide semiconductor (LDMOS). Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state (on-state) BV of the SOI p-channel LDMOS can reach 741 (620) V in the 3-μm-thick buried oxide layer, 50-μm-length drift region, and at −400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.