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${p}$ -channel GaN field-effect transistors (FETs) with a SiNx/GaON gate stack have been demonstrated with enhanced stability within a wide range of voltage bias and temperature. In this letter, the gate leakage characteristics and reliability of this unconventional staggered gate stack are investigated. At relatively low gate voltages, the gate current is suppressed owing to the buried-channel structure and the presence of GaON that presents an effective hole barrier. With more negative gate biases, the gate leakage was found to be dominated by the transport of holes that spillover from the ${p}$ -channel through the SiNx via Poole-Frenkel emission. Based on this gate leakage mechanism at large gate bias, $\sqrt {{\mathrm {E}}} $ model was used for gate lifetime prediction. The maximum applicable ON-state gate voltage of −7.3 V is obtained for a 10-year lifetime with a 1% gate failure rate. [ABSTRACT FROM AUTHOR]

In a ${p}$ -channel field-effect-transistor (${p}$ -FET) bridge HEMT device recently realized on a commercial ${p}$ -GaN/AlGaN/GaN-on-Si power HEMT epi-wafer, it is revealed that the device’s reverse-conduction turn-on voltage (${V}_{\text {RT}}$) can be effectively decoupled from the forward threshold voltage (${V}_{\text {TH}}$) of Schottky-type ${p}$ -GaN gate HEMTs. Unlike the conventional Schottky-type ${p}$ -GaN gate HEMTs, of which ${V}_{\text {RT}}$ is closely linked to ${V}_{\text {TH}}$ , the ${p}$ -FET-bridge HEMT enables separate designs of ${V}_{\text {RT}}$ and $V_{\text {TH}}$ so that low-loss reverse conduction and high threshold voltage can be simultaneously realized. In addition, ${V}_{\text {RT}}$ can be further reduced by engineering the AlGaN barrier layer, which will also benefit a lower channel sheet resistance without lowering ${V}_{\text {TH}}$. [ABSTRACT FROM AUTHOR]

In this work, we study the gate leakage mechanisms of E-mode p-n junction/AlGaN/GaN (PNJ) high electron mobility transistors (HEMTs), which have been shown to deliver low gate leakage and wide safe operating gate-bias range. The intrinsic gate leakage through the PNJ-gate was found to be limited by the transport of holes through the p-GaN layer, which occurs via Poole-Frenkel emission and phonon-assisted tunneling in low and high gate bias region, respectively. In addition, lateral leakage current and the role of variable hopping process (VRH) are also discussed. Gate leakage current models based on the revealed mechanisms can quantitatively reproduce the gate-leakage behavior in the entire relevant range of gate biases and temperatures. [ABSTRACT FROM AUTHOR]

When the gated channel region of a GaN high-electron-mobility transistor (HEMT) is configured into multiple sub-channels in parallel and separated by embedded isolating patterns, the effective resistance of the access regions could be reduced, and consequently, the knee voltage (${V}_{{\text {K}}}$) of the transistor could be lowered. In this work, each sub-channel is defined as a convergent funnel-like shape, with its width gradually shrunk from the source side to the drain side. Different from conventional channels with uniform width under the entire gate, the funnel-shaped channel could converge electrons as they transport from source side to drain side, which facilitates electrons’ acceleration toward saturation velocity under a smaller drain-to-source bias, leading to a reduced intrinsic ${V}_{{\text {K}}}$ in the gated channel. Thus, more desirable ${I}$ - ${V}$ characteristics and more balanced performance enhancement in RF linearity and power added efficiency are achieved at a low supply voltage, making the convergent-channel HEMT attractive for power amplifiers in mobile terminals. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a GaN-based $\textit {p-n}$ junction gate (PNJ) HEMT featuring an ${n}$ -GaN/ ${p}$ -GaN/AlGaN/GaN gate stack. Compared to the more conventional ${p}$ -GaN gate HEMT with a Schottky junction between the gate metal and ${p}$ -GaN layer, the $\textit {p-n}$ junction can withstand higher reverse bias at the same peak electric-field as the depletion region extends to both the ${n}$ -side and ${p}$ -side, while exhibiting lower leakage current. The PNJ-HEMT shows a positive threshold voltage (${V}_{\text {TH}}$) of 1.78 V, a small gate leakage $(\sim 10^{-3}$ mA/mm @ ${V}_{\text {GS}} = {10}\,\, \text {V}$). In particular, a large forward gate breakdown voltage of 19.35 V at 25 °C and 19.70 V at 200 °C was achieved with the PNJ-gate HEMT. [ABSTRACT FROM AUTHOR]

The drain induced dynamic threshold voltage (${V}_{\textrm {th}}$) shift of a ${p}$ -GaN gate HEMT with a Schottky gate contact is investigated, and the underlying mechanisms are explained with a charge storage model. When the device experiences a high drain bias ${V}_{\textrm {DSQ}}$ , the gate-to-drain capacitance (${C}_{\textrm {GD}}$) is charged to ${Q}_{\textrm {GD}}$ (${V}_{\textrm {DSQ}}$). As the drain voltage drops to ${V}_{\textrm {DSM}}$ where ${V}_{\textrm {th}}$ is measured, ${C}_{\textrm {GD}}$ is expected to be discharged to ${Q}_{\textrm {GD}}$ (${V}_{\textrm {DSM}}$). However, the metal/ ${p}$ -GaN Schottky junction could block the discharging current, resulting in storage of negative charges in the ${p}$ -GaN layer. For the device to turn on, additional gate voltage is required to counteract the stored negative charges, resulting in a positive shift of ${V}_{\textrm {th}}$. The dynamic ${V}_{\textrm {th}}$ shift is an intrinsic and predictable characteristic of the ${p}$ -GaN gate HEMT which is linearly correlated with $\Delta \!{Q}_{\textrm {GD}}={Q}_{\textrm {GD}}$ (${V}_{\textrm {DSQ}}$) $- {Q}_{\textrm {GD}}$ (${V}_{\textrm {DSM}}$). The ${V}_{\textrm {th}}$ shift is dependent on ${V}_{\textrm {DSQ}}$ as well as ${V}_{\textrm {DSM}}$ , indicating that the ${V}_{\textrm {th}}$ shift is varying along the load line during a switching operation. [ABSTRACT FROM AUTHOR]

The OFF-state drain leakage characteristics in 600-V p-GaN HEMTs with an ohmic gate contact are investigated under dynamic switching conditions instead of commonly used quasi-static measurement setup. It is found that fast dynamic OFF-state leakage current (dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$) is substantially higher than the slow-ramping quasi-static ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ due to the weaker trapping effect in the buffer layer. With sufficiently large positive ON-state gate bias, further increase in dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ is observed and is attributed to ON-state hole injection that leads to energy band lowering in the buffer. The underlying physical processes are explained by the dynamic behavior of the traps in the buffer layer. This letter indicates that the ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under practical switching operations is much higher than the static measurement results and should be used to evaluate dynamic OFF-state power consumption in the p-GaN HEMTs with an ohmic gate contact. [ABSTRACT FROM AUTHOR]

An MOS field plate-protected Schottky-drain (gated Schottky-drain) is successfully integrated on a double-channel AlGaN/GaN MOS-HEMT to provide reverse blocking capability. The leakage suppression MOS field plate is deployed on the etched upper GaN channel layer after a barrier fully recess process, leading to a low reverse OFF-state leakage current of −20 nA/mm (at −100 V). The drain metal is deployed adjacent to the MOS field plate, contacting the upper MOS-channel and lower heterojunction channel from the sidewall. A metal-2DEG Schottky contact with a low turn-ON voltage of 0.5 V is achieved. Since the lower channel (below the MOS field plate) is separated from the etched surface of upper GaN channel layer, a high-conductivity MOS-gated channel with a sheet resistance of 806 $\Omega$ /Square is obtained. The device exhibits a threshold voltage of +0.6 V (at $10~\mu \text{A}$ /mm and +1.9 V from linear extrapolation) and an ON-resistance of ~18 $\Omega {\cdot} \text {mm}$. Besides, a high forward (and reverse) breakdown voltage of 790 V (and −656 V, all at $10~\mu \text{A}$ /mm) is achieved. [ABSTRACT FROM AUTHOR]

In this letter, we investigated the threshold voltage V\text {TH} stability under reverse-bias step-stress in the E-mode LPCVD-SiNx/PECVD-SiNx/GaN MIS-FET. Under the OFF-state reverse-bias stress with the same net gate-to-drain voltage ( V\text {GD} ), the V\text {TH} shift shows an obvious dependence on the negative gate bias. With a V\text {GS} of 0 V, the V\text {TH} shift is small and recoverable, while the V\text {TH} shifts are substantially larger with more negative gate bias ( V\text {GS}=-20 V). This larger V\text {TH} shifts caused by the negative V\text {GS} can be explained with a hole-induced degradation model. An important indication revealed by this model is that negative gate bias should be well confined in high-power switching applications of GaN E-mode MIS-FET for a stable V\text {TH} . [ABSTRACT FROM PUBLISHER]

An AlGaN/GaN double-channel Schottky barrier diode (DC-SBD) with dual-recess gated anode is demonstrated in this letter. The DC-SBD features two recess steps. The deep one cuts through two channels, and the anode metal contacts 2DEG directly from the sidewall of the recessed heterostructure. The shallow one terminates at the upper channel layer and is located adjacent to the Schottky contact. A MOS field plate is placed on the shallow recess region to pinchoff the underlying channels, so the off-state leakage current of the DC-SBD can be suppressed. Since the lower channel is separated from the etched surface, the field-effect mobility beneath this MOS structure shows a high peak value of 1707 cm2/( \text V\cdot \text s ). The DC-SBD with an anode-to-cathode length ( L\text {ac} ) of 15~\mu \textm exhibits a turn-on voltage ( V\text {T} ) of ~0.6 V (at 1 mA/mm), a leakage current of 7.8 nA/mm (at −100 V), and a breakdown voltage of 704 V (at 1~\mu \textA /mm). The double-channel design also allows both the deep and shallow recesses to be terminated at GaN layers that results in high uniformity of V\text {T} . [ABSTRACT FROM PUBLISHER]

Dynamic ON-resistance ( \mathrm RON ) of 650-V GaN-on-Si lateral power devices with a floating Si-substrate termination is investigated. Compared with the grounded substrate termination, the floating substrate could deliver smaller dynamic \mathrm RON under higher drain bias (> 400 V) switching operation, but leads to larger dynamic \mathrm RON under low-drain bias (< 400 V). The underlying physical mechanisms are explained by the tradeoff between charge storage in the Si substrate and electron trapping effect in the GaN buffer layer. [ABSTRACT FROM AUTHOR]

Developing effective technique to protect the etched- GaN surface from the degradation in a high-temperature (i.e., at ~ 780°C) process, such as low-pressure chemical vapor deposition (LPCVD), is essential for fabricating normally-off GaN MIS-FETs with high-quality dielectric/GaN interface and highly reliable gate dielectric. In this letter, we developed an approach of obtaining such a protection layer using oxygen-plasma treatment followed by in situ annealing prior to the LPCVD-SiNx deposition. A sharp and stable crystalline oxidation interlayer (COIL) between the LPCVD-SiNx and etched-GaN was successfully formed. The LPCVD-SiNx/GaN MIS-FETs with COIL deliver normally-off operation with a VTH of 1.15 V, small on-resistance, small hysteresis, and thermally stable VTH . [ABSTRACT FROM AUTHOR]

In this letter, we demonstrate an integrated process that illustrates the compatibility of AlN/SiNx passivation with high-performance (i.e. low leakage and high breakdown) low-pressure chemical vapor deposition (LPCVD) SiNx gate dielectric for GaN-based MIS-HEMT. It is shown that the AlN/SiNx passivation structure maintains its superior capability of suppressing the current collapse after enduring high temperature of 780 °C during the LPCVD-SiNx deposition. The AlN/SiNx passivation is shown to be significantly better than the LPCVD-SiNx passivation by delivering small dynamic $R_{{\mathrm{\scriptscriptstyle ON}}}$ degradation, especially under high drain bias switching with $V_{{\mathrm{DS}}} > 100$ V. [ABSTRACT FROM PUBLISHER]

A low on-resistance normally-off GaN double-channel metal–oxide–semiconductor high-electron-mobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with V\mathrm {th} of +0.5 V at I\mathrm {DS}= 10 ~\mu \text{A} /mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm2/( \textV\cdot \texts ). The on-resistance is as small as 6.9 \Omega \cdot \text mm for a DC-MOS-HEMT with LG/L\mathrm {GS}/L\mathrm {GD} = 1.5/2/15~\mu \text{m} , and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained. [ABSTRACT FROM AUTHOR]

In this letter, silicon nitride (SiNx) film deposited at 780 °C by low-pressure chemical vapor deposition (LPCVD) was employed as gate dielectric for GaN-based metal–insulator–semiconductor high-electron-mobility transistors. The LPCVD-SiNx exhibit improved gate dielectric performance than the plasma enhanced chemical vapor deposition-SiNx, including smaller forward and reverse gate leakage, and higher forward gate breakdown voltage. [ABSTRACT FROM AUTHOR]