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Field-Coupled Nanocomputing technologies have great potential to surpass CMOS technology because of their lower power consumption and higher device concentration. To ease the burden of placement and routing (P&R) problems for FCN circuits, many delicate two-dimensional clocking schemes have been proposed, upon which algorithms can solve the P&R problems more strategically. In this paper, we propose a two-level optimization strategy by using a genetic algorithm (GA) combined with an enhanced A* algorithm. Some circuit design requirements, such as clock synchronization, layout area, etc., are cleverly designed in the fitness value function of the GA. Numerical results demonstrate the effectiveness of the hybrid algorithm. In particular, compared to current tools, such as fiction and Ropper, the proposed algorithm can achieve an optimal solution with a higher success rate and a sizeable applicable circuit scale. In addition, the concept of design rule checking (DRC) was proposed in FCN and integrated into the algorithm, making the P&R results mapping from gate-level to cell-level more smoothly. Besides, the number of cross wires is significantly reduced, and the distribution of IO ports can be more effectively controlled. [ABSTRACT FROM AUTHOR]

The divider is one of the most complex hardware units in Stochastic Computing (SC); even though several new designs have been presented to reduce the computation latency of the conventional divider, all of them still require a considerable number of clock cycles. Moreover, they incur in low performance due to the employed arithmetic computational scheme. In this paper, a Delta Sigma Modulator (DSM) based stochastic divider is proposed. As an entirely digital circuit, the proposed divider offers the best computation latency and accuracy over all existing stochastic dividers found in the technical literature (with a typical reduction between 66.8% and 96.9% in the number of clock cycles and a reduction from $10^{\mathrm {-3.4}}$ to $10^{\mathrm {-3.9}}$ in the average mean square error for a 10-bit resolution). An SC-based Neural Network (NN) is considered as an initial case study to evaluate the advantages of the proposed design in an emerging application; results show that the proposed divider enables an SC-based NN to achieve a higher classification accuracy and hardware efficiency than existing designs. To show the flexibility of the proposed divider design, its application to Sobol-based sequences is also presented; also in this case, its superiority over other designs is confirmed. These features make the proposed design very attractive for hardware-constrained platforms; moreover, such a novel design approach that incorporates ideas from analog/mixed signal circuit design into a digital circuit design, can motivate other researchers to design efficient SC designs using similar schemes. [ABSTRACT FROM AUTHOR]

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18- $\mu \text{m}$ standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved $\sim 1.24\times $ more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%. [ABSTRACT FROM AUTHOR]

In the Mesochronous Pipeline (MP), the clock period is the maximal of differences between the maximum/minimum delays of all stages. This value is less than the maximum delay between the memory elements, so MP is operating faster than the conventional pipeline (CP). To take full advantages of MP, in this paper, Automated Mesochronous Pipeline Scheduler (AMPS) for high performance digital circuits, is proposed which provides all allowed partitioning options generated by register allocation procedures obtained with varying maximum delay differences of stages. This allows a designer to select from design space produced by AMPS based on the desired specification. Unlike the traditional MP, AMPS utilizes automated scripts to extract the timing characteristics of the synchronizers and gates. This enables a designer to explore trade-offs between latency, power, and frequency. To evaluate our toolset, an 8-bit Carry Increment Adder (CIA), a 4-bit Binary-Coded Decimal (BCD) adder, a 4-bit ALU, and a set of circuits from ISCAS85 and ISCAS89 benchmarks are considered. All circuit level simulations are performed in the 65nm CMOS standard technology node. AMPS improves the frequency for its best solutions about 127.94% (on average) in comparison to the conventional pipeline scheme. [ABSTRACT FROM AUTHOR]

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively. [ABSTRACT FROM AUTHOR]

In this paper we present the Standard Cell Delay-based Dual-rail Pre-charge Logic (SC-DDPL), a novel logic style which is able to counteract Power Analysis Attacks (PAAs) also in the presence of capacitive mismatch at the output of dual-rail gates. The SC-DDPL is based on a standard-cell design flow and it is suitable to be implemented on ASICs or FPGAs without any routing constraint on differential lines, supporting the Time Enclosed Logic protocol along with a DPL structure. The security provided by SC-DDPL has been firstly investigated in simulation on some basic logic gates, designed adopting a commercial 40nm CMOS technology. Simulated experiments have highlighted the capability of SC-DDPL gates to guarantee a high-level of security also in presence of extreme capacitive mismatch, exhibiting strongly reduced NED/NSD metrics, as well as a reduction of the FED, compared to a reference RTZ-based WDDL implementation. In order to compare the proposed logic against other state-of-the-art countermeasures we have implemented a 4bit PRESENT crypto-core adopting several logic styles, evaluating different security metrics on a 65nm Intel Cyclone-IV FPGA. Experimental results have confirmed that the SC-DDPL outperforms other gate-level countermeasures in terms of security metrics with a reasonable area and power consumption overhead. [ABSTRACT FROM AUTHOR]

This paper presents a gain-boosting technique for two-port N-path band-pass filters (BPFs) based on the principle of discrete-time parametric amplification in MOS devices. The proposed technique also acts as a noise figure (NF) reduction technique due to the low-noise amplification before the output commutation. Analytical expressions for gain, NF, and input impedance of the proposed parametrically gain-boosted N-path BPF are derived using linear periodically time-variant (LPTV) network analysis and have been verified through simulations. The measurement results of a pseudo-differential eight-path BPF, implemented in a 180 nm CMOS technology, are presented. The center frequency of the implemented filter is tunable from 0.05 GHz to 0.4 GHz with a Q varying from 4 to 18. The gain of the filter is programmable with the input common-mode voltage. At 0.4 GHz, the filter achieves a variable gain of 2–8 dB over the input common-mode range of 0.55 V to 0.85 V. At every tuned frequency, the filter has a peak gain ≥8 dB, NF < 4.1 dB, and in-band third-order intercept power (IB-IIP3) >0 dBm. It is also shown in simulations that the proposed gain-boosting technique reduced the NF of the filter by >2.2 dB while consuming a dynamic power in the range of 3.8-31 mW per filter. [ABSTRACT FROM AUTHOR]

This paper presents an all-digital bandpass $\Delta\Sigma $ time-to-digital converter (BP) $\Delta \Sigma $ TDC) for IF data conversion. The proposed TDC is based on a second-order resonator implemented by a cascade of two time-mode lossless discrete integrators (LDI), and a digital-to-time converter (DTC) in a feedback loop. The DTC is based on a new topology of double-edge voltage-controlled delay unit. The proposed TDC achieves bandpass quantization noise shaping and it does not require any complex calibration circuit to compensate for timing errors. To realize the time-mode LDI-based resonator, time-latches with some digital gates are employed. Moreover, a direct feed-forward compensation is utilized in the TDC to attain high signal-to-noise and distortion ratio (SNDR) by reducing the internal time-mode swing, thus relaxing the speed and area requirements on digital circuits leading to low-voltage operation. The prototype BP $\Delta \Sigma $ TDC achieves a 39.5-dB peak SNDR over a 0.2 MHz signal bandwidth at 42.8 MS/s while consuming less than 5 mW in a 1.2 V IBM 130-nm CMOS process. The proposed TDC is highly digital and occupies a core area of only 0.048 mm2. [ABSTRACT FROM AUTHOR]

This paper identifies novel directions of standard-cell-based synthesizable memory design. A compact 18T-bitcell of OR-AND-Invert (OAI) and AND-OR-Invert (AOI) logic gates is presented with bit-selective write and multiplexed read accesses. It reduces the bitcell area by 11%–40% compared to the state-of-the-art clock-gating-based D-latch schemes while avoiding custom-cell design. The improved storage density comes from the tight integration on two levels–coupling the read multiplexing within each bitcell and taking advantage of structured datapath placement in bitcell arrays by using commercial CAD tools. As measured on a 40 nm SRAM of 90 kb, the OAI/AOI-gate-based synthesizable memory features 0.4 V minimum access voltage, 30 fJ minimum read energy per bit, and a leakage power of 1.4 pW per bit at 0.3 V data retention voltage. It is ideally suited for IoT-node design operating in sub- $V_{\mathrm {t}}$ for joint dynamic energy and leakage power reduction. Further, it enables fast turn-around times by IP reuse over technology nodes with minimal (re)design effort. [ABSTRACT FROM AUTHOR]

Speed-path debugging at the post-silicon stage due to timing variations is a challenging problem in designing high-performance digital circuits. In this paper, we propose an efficient and scalable method for automatic speed-path debugging which is based on quantified Boolean formulas (QBF) to detect multiple erroneous paths when taking into account the timing variations. We have proposed new gate-level timing variation and path slowdown models which enable us to formulate such a debugging problem as a QBF problem. The results on the ISCAS’85 and ISCAS’89 benchmarks show that our method enjoys on average 52.4% decrease in the size model, and 63.1% decrease in debugging time in comparison with existing methods. Moreover in situations where existing methods due to the size explosion of abundant copies cannot be applied, the proposed method detects erroneous gates in a reasonable runtime. [ABSTRACT FROM AUTHOR]

This paper presents experimental results on a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions. The proposed logic family is based on the time enclosed logic (TEL) encoding and can be viewed as an improvement of the delay based dual rail pre-charge logic (DDPL) logic style. The DDPL logic gates have been redesigned to avoid the early evaluation effect and to reduce area and power consumption. A library of TEL secure gates and flip-flops has been implemented in a 65 nm CMOS process. The developed library allows adopting a semi-custom design flow (automatic place and route) without any constraint on the routing of the complementary wires. A four bit lightweight crypto core has been implemented on a 65 nm CMOS testchip by using the developed TEL library and compared against a SABL implementation of the same crypto core on the same chip. Comparisons have been carried out by means of extensive transistor level simulations and measurements on the 65 nm testchip which allowed to evaluate a wide set of security metrics. Experimental results have shown a strong reduction of the information leakage with respect to the sense amplifier based logic logic style under mismatched load conditions with an improvement in the measurements to disclosure of more than three orders of magnitude. [ABSTRACT FROM AUTHOR]

Semiconductor technologies bring the possibility of embedding billions of components in a chip, allowing the design of complex integrated circuits. However, such levels of integration are not free and delay uncertainties grow steadily, which is increasingly challenging. Quasi-delay-insensitive (QDI) design promises to cope with such challenges, being less timing constrained than synchronous or bundled-data designs. However, two barriers to its wider adoption are: 1) missing methods to automatically implement QDI circuits and 2) enabling QDI semi-custom design. This paper proposes a new QDI design method that extends the null convention logic (NCL) asynchronous template. Also, it describes an associated semi-custom design flow for the extended template, which uses conventional electronic design automation tools to synthesize QDI circuits down to layout. The method enables using the full power of synthesis and optimization commercial tools. Illustrating this, the ISCAS85 benchmarks take 35%–43% less gates to implement, compared with conventional, pattern-based NCL design. A comparison with the Uncle tool provides indication that the proposed method is indeed a flexible and powerful approach to design asynchronous QDI circuits. Lastly, 16-b multiplier designed with the method until the layout level exhibits 170%–240% larger operations/Watt compared with an equivalent NCL design, and an almost 400% better operations/mm2 figure. [ABSTRACT FROM PUBLISHER]

This paper proposes charge pumps with improved power efficiency suitable for low-power on-chip applications. Undesired charge transfer, which has a direction opposite to that of the intended current flow, presents a significant source of power loss in charge pumps. The proposed charge pump circuit utilizes charge transfer switches with a complementary branch scheme to significantly reduce undesired charge transfer, thereby improving power efficiency and increasing output voltage effectively. An optimized gate control strategy is applied to further decrease the power loss caused by undesired charge transfer. Simulations of 8-stage charge pumps in a 0.13~\mu \textm standard CMOS technology show that for an input supply voltage of 1.2 V, the proposed charge pump circuit reaches a power efficiency of 58.72% with an output voltage of 7.45 V, when delivering 5-mA load current, and is able to maintain a power efficiency of around 50% and an output voltage of over 5 V as the load current increases to 10 mA. Compared with the other charge pump circuits, the simulation results demonstrate better performance of proposed charge pump circuits in terms of both voltage pumping gain and power efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a 44.2-mW 3.2-GHz 3-port register file (RF) that demonstrates measured operation from 1.2 V down to 0.4 V. The 32-entry \times \,32 -bit/word 2-read/1-write RF is fabricated in TSMC 65-nm low-power low threshold voltage (low- \text {V}_{\mathrm {t}} ) CMOS process. A four-transistor read port is presented that permits the design of low-capacitance dynamic local bitlines (LBLs). Switching power in the LBLs and the LBL precharge buffer is thereby reduced. Based on extensive simulation results, the proposed read port is recommended for use in wide-worded RFs, which employ a wide dynamic-OR structure at the LBL stage. The proposed RF outperforms the conventional design in terms of power consumption for frequencies exceeding 3-GHz. The read port exploits intrinsic capacitive coupling to achieve robust operation over a wide voltage range. The architecture of the read port simultaneously enhances robustness of the dynamic bitline by 58.8% as compared to the conventional low- \text {V}_{\mathrm {t}}$ bitline. [ABSTRACT FROM PUBLISHER]

This paper presents novel designs of static dual-edge-triggered (DET) flip-flops that exhibit unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are presented including two high-performance designs and designs that improve upon common Latch-MUX DET flip-flops so that none of their internal circuit nodes follow changes in the input signal. A common characteristic of the presented flip-flops is their low energy dissipation due to glitches at the input. Novel DET flip-flops are compared to existing DET flip-flops using simulation in a high performance 28 nm CMOS technology and are shown to have superior characteristics such as power and power-delay product (PDP) for a range of switching activities. Extensive Monte Carlo and voltage scaling simulations are performed to show that the presented designs are robust under PVT variations. [ABSTRACT FROM PUBLISHER]

Power analysis attacks have become one of the most significant security threats to modern cryptographic digital systems. In this paper, we introduce a new CMOS-based blurring gate (BG) which increases the immunity of a cryptographic system to these attacks. The BG switches randomly between two operational-modes, static and dynamic. When embedded in the crypto-core, the BGs enforce different and unpredictable arrival times (propagation delays) along the logic paths from inputs to outputs. This results in blurred power profiles and random propagation delays, which in turn mitigate power attacks. Simulation results and security analyses using system with embedded BG units with standard 65-nm technology, clearly show higher immunity to power analysis attacks over other standard-library based randomization technologies. The signal-to-noise ratio (SNR) decreases rapidly below 1 for a relatively small amount of BGs even with a large number of power traces in the worst case test environment. [ABSTRACT FROM PUBLISHER]

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based transmitters via equation-based optimization and provides practical design guidelines that can help achieving optimum power efficiency. An accurate equation-based optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific design specifications and process technologies. The proposed optimization framework can determine optimum clock edge-rate (i.e., ratio of rise/fall time to clock period) and inter-stage voltage swings that enable significant power savings without affecting performance. Various transmitter design tradeoffs were analyzed for 45-nm, 65-nm, and 90-nm technologies considering data rate, clock edge-rate, and inter-stage swing optimization. Based on the analysis results, we determined the most energy-efficient data rate that can be achieved with acceptable power overhead for each technology node. Also, we identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to 43% with inter-stage swing optimization with all other design constraints held constant. [ABSTRACT FROM AUTHOR]

For anti-fuse or flash-memory-based field-programmable gate arrays (FPGAs), single-event transient (SET)-induced faults are significantly more pronounced than single-event upsets (SEUs). While most existing work studies SEU, this paper proposes a retiming algorithm for mitigating variational SETs (i.e., SETs with different durations and strengths). Considering the reshaping effect of an SET pulse caused by broadening and attenuation during its propagation, SET-aware retiming (SaR) redistributes combinational paths via postlayout retiming and minimizes the possibility that an SET pulse is latched. The SaR problem is formulated as an integer linear programming (ILP) problem and solved efficiently by a progressive ILP approach. In contrast to existing SET-mitigation techniques, the proposed SaR does not change the FPGA architecture or the layout of an FPGA application. Instead, it reconfigures the connection between a flip-flop and an LUT within a programmable logic block. Experimental results show that SaR increases mean-time-to-failure (MTTF) by 78% for variational SETs with a 10-min runtime limit while preserving the clock frequency on ISCAS89 benchmark circuits. To the best of our knowledge, this paper is the first in-depth study on FPGA retiming for SET mitigation. [ABSTRACT FROM PUBLISHER]

A united-reference fractional counter (URFC) is proposed for multi-level time-to-digital converters (TDCs) used in direct time-of-flight (dToF) light detection and ranging (LiDAR) applications. The URFC combines the integer counter and the second-level interpolation in one functional block that derives both the integer part and the fractional part from the same synchronization result. Thus the proposed TDC has a more robust structure to deal with misalignment errors, and measurement results from different levels can be perfectly matched. High linearity and high precision can be guaranteed because of the united reference without calibration. The response time of the URFC decreases to hundreds of picoseconds, which makes it suitable for all output pulses from the avalanche photodiode. A TDC with the proposed URFC was implemented in 65nm standard CMOS technology with a detection range of $2.5~\mu \text{s}$ ($\sim 375\text{m}$) and a single shot precision of 27.63ps (~4.0mm). The power consumption is 51.4mW with a reference clock at 200MHz and a repetition rate at 999kHz. The INL and DNL are ±2.751 LSB and ±1.679 LSB, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a new ADC architecture called partially active flash ADC. A 10 GS/s 6 b four-way time-interleaved ADC prototype in 65 nm CMOS demonstrated that this new ADC architecture offers better power efficiency than traditional ADC architectures in the \geq10 GS/s speed range. Various considerations towards high-speed ADC designs are discussed including a proposed source-follower based boot-strap track-and-hold circuit to reduce input kickback and improve the ADC bandwidth. Also discussed is the generation and skew calibration of the four-phase clocks for the interleaved channels to improve the ADC effective resolution at high input frequencies. By deriving the four-phase clocks from a Nyquist frequency input clock through pass gates, accurate timing skew calibration is achieved through a simple duty-cycle correction. Measured SNDR is 34.3 dB at low input frequencies and 32.0 dB at the Nyquist input frequency. The ADC including the input clock buffer consumes 83 mW with a FOM of 197 fJ/cs. [ABSTRACT FROM AUTHOR]

This paper describes a fully-integrated 77-GHz ultra-wideband pseudo-random noise (PRN) radar transceiver in a Silicon-Germanium technology. The transceiver is equipped with a programmable pseudo-random binary sequence (PRBS) generator, which is realized in a current-mode logic topology and can be operated with a clock rate of up to 4.25 GHz to enable a range resolution of 3.5 cm. The signal generation unit is simplified by including a frequency multiplier to create a 76.5-GHz carrier signal from a single 4.25-GHz input, that is also used as a clock for the PRBS generator. The transceiver achieves a phase noise of -105.3 dBc/Hz at 1-MHz offset frequency, a transmit output power of 6.2 dBm, a receive gain of 24 dB and an input-referred 1-dB compression point of -14 dBm. Track&hold circuits included in the receive path allow the use of a sub-sampling technique to reduce the IF data rate down to 1 MHz. Radar measurements with two PRN transceivers with different primitive polynomials were done concurrently to show a fundamental function of the programmable PRBS generator. Radar measurements with the PRN and the frequency-modulated continuous-wave (FMCW) principles show comparable results and the PRN radar proves to be a real alternative to the FMCW radar. [ABSTRACT FROM AUTHOR]

Clock gating is very useful for reducing the power consumed by digital systems. Three gating methods are known. The most popular is synthesis-based, deriving clock enabling signals based on the logic of the underlying system. It unfortunately leaves the majority of the clock pulses driving the flip-flops (FFs) redundant. A data-driven method stops most of those and yields higher power savings, but its implementation is complex and application dependent. A third method called auto-gated FFs (AGFF) is simple but yields relatively small power savings. This paper presents a novel method called Look-Ahead Clock Gating (LACG), which combines all the three. LACG computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. It avoids the tight timing constraints of AGFF and data-driven by allotting a full clock cycle for the computation of the enabling signals and their propagation. A closed-form model characterizing the power saving per FF is presented. It is based on data-to-clock toggling probabilities, capacitance parameters and FFs' fan-in. The model implies a breakeven curve, dividing the FFs space into two regions of positive and negative gating return on investment. While the majority of the FFs fall in the positive region and hence should be gated, those falling in the negative region should not. Experimentation on industry-scale data showed 22.6% reduction of the clock power, translated to 12.5% power reduction of the entire system. [ABSTRACT FROM AUTHOR]

This paper extends the analysis of the effectiveness of Leakage Power Analysis (LPA) attacks to cryptographic VLSI circuits on which circuit level countermeasures against Differential Power Analysis (DPA) are adopted. Security metrics used for assessing the DPA-resistance of crypto core implementations, such as the minimum number to disclosure (MTD) and the asymptotic correlation coefficient, have been extended to the case of LPA. The LPA-resistance has been evaluated in terms of MTD as a function of the on chip noise. Noise variances up to 10000 times greater than the signal variance have been taken into account and LPA attacks have been successfully executed for all the logic styles under analysis using less than 100000 measurements. Moreover the role of process variations has been investigated through extensive Monte Carlo simulations in order to evaluate their impact on the leakage model for the logic styles under analysis. Results show that LPA attacks can be successfully carried out on the different anti-DPA logic styles even in presence of process variations. To the best of our knowledge, this work proves for the first time the effectiveness of LPA attacks in a real scenario where on chip noise and process variations are taken into account. [ABSTRACT FROM AUTHOR]

A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino-compatible, CD logic predischarges the output to logic “0” and conditionally makes a transition to logic “1” through the critical-path CLK PMOS transistors for an NMOS transistor network. The constant delay (regardless of the fan-in) feature makes it up to 2\times faster than a dynamic logic gate during the D-Q mode for a complex logic such as a two-bit binary comparator. The proposed comparator's architecture is divided into two stages, where the first stage adapts a novel tree comparator structure specifically designed for static logic to achieve low-power consumption and the second stage utilizes CD logic to realize high performance without sacrificing the overall energy efficiency. At 1-V supply, the proposed comparator's measured delay is 167 ps, and has an average power and a leakage power of 2.34 mW and 0.06 mW, respectively. At 0.3-pJ iso-energy or 250-ps iso-delay budget, the proposed comparator with CD logic is 20% faster or 17% more energy-efficient compared to a comparator implemented with just the static logic. [ABSTRACT FROM AUTHOR]

Dynamic power is a major source of power dissipation for high speed designs. Domain isolation methodology is a recently-proposed technique for reducing dynamic power based on controlling the evaluation phase of dynamic logic (toggling control). This work demonstrates some design issues in the domain isolation methodology and explains why it is inefficient with pipelined systems. We propose fixes for its identified issues, which enables using the toggling control with pipelined systems in a more efficient way. A novel flow named “Power Reduction Flow” is proposed for reducing dynamic power of digital circuits. Our flow uses novel design analytical methods, novel “Dynamic Logic Modifier Flow”, and novel “Dynmic Logic Area Validation Flow” for reducing dynamic power with conditionally improving performance. The new design analytical methods are based on probability theory, SystemVerilog covergroups, and digital circuit modeling. A new event type perspective is also proposed to analyze designs to reduce dynamic power in them. Experimental results using TSMC 65 nm and low supply voltages show up to 59% power reduction compared to the original traditional techniques with improving circuit’s performance by 3× of its original maximum operating frequency at the cost of an extra 12.3% increase in area. [ABSTRACT FROM AUTHOR]

This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis and simulation results show that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to that in the traditional pipeline topology. To verify the functions of the proposed design, two chips are implemented with the proposed 4-to-1 MUX-FF and 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the MUX-FF and the proposed serializer with MUX-FFs are almost bit-error-free (with BER <; 10-12 ), operating at up to 6 Gbits/s and 12 Gbit/s, respectively. [ABSTRACT FROM PUBLISHER]

Flying-Adder direct period synthesis is an emerging frequency synthesis technique. It is a mixed-signal technology that directly constructs the output clock period based on a multi-inputs reference. Owing to its open loop style and the usage of Time-Average-Frequency, this technique bears two important features: fine frequency resolution and instantaneous response. Although it has been used in commercial products for over a decade, the important issue associated with design/layout mismatch among its multi-inputs has not been studied in depth. In this paper, through a 55 nm Flying-Adder implementation, the cause of the mismatch is investigated. A mismatch model is created. Based on the model, the mismatch's impact is studied both in time and frequency domain. The experimental data from the chip is used to verify the observations from the analysis. Some useful insights are summarized in the end which will be useful in guiding future designs for commercial products. This study could also be helpful in developing a general theory for this problem. [ABSTRACT FROM PUBLISHER]

In this paper, three high performance, low cost and robust latches (referred to as HLR, HLR-CG1, and HLR-CG2) are proposed in 45 nm CMOS technology. The proposed latches are completely insensitive to transient faults at their internal nodes and output node independent of the size and technology of the CMOS transistor. The proposed latches tolerate transient faults regardless of the energy of the striking particle. The proposed latches offer faster speed, higher reliability to transient faults with lower costs regarding power and area than most of the latches recently proposed in the literature. The proposed designs demonstrate that the power-delay-product benefit is 13 times on average compared to previous robust latches including standard latch. [ABSTRACT FROM PUBLISHER]

This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18- μm CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply. [ABSTRACT FROM PUBLISHER]

This paper presents a new circuit technique to reduce temperature-induced delay uncertainty. Programmable temperature compensation devices (PTCDs) are used to tune logic gate pull-up and pull-down networks to their respective temperature-insensitive operating points, dramatically improving thermal resilience. Over a -55°C to 125°C temperature range, the proposed technique is shown to decrease temperature-induced delay uncertainty by up to 91% compared to other temperature resilient methods. We explore the limitations of using multi-VT and adaptive body biasing approaches to achieve temperature insensitivity; the proposed method achieves insensitive operation at larger supply voltages than prior methods, providing temperature insensitivity at nominal voltage for the first time. We explain how to integrate PTCDs into a variety of logic gates as well as larger structures such as a 1-bit mirror adder. Applying the proposed method to a clock tree is shown to reduce temperature-induced clock skew by up to 98%. Process variations degrade the temperature resilience; however, the proposed approach still improves temperature resilience by ~50% over prior methods when these variations are considered. Furthermore, we propose a process variation-compensation system to maintain our PTCD method's temperature resilience. [ABSTRACT FROM PUBLISHER]

A new quadrature tunable pulse generator is presented in this paper using 0.13 \mu \m CMOS for 22–29 GHz ultrawideband (UWB) vehicular radar. A quadrature inductor-capacitor (LC) oscillator is quickly switched on and off for the duration of the pulse, and the amplitude envelope is modulated with an impulse using a variable passive CMOS attenuator. The impulse is realized using a glitch generator (CMOS nand gate) and its duration can be changed over a wide range (375 ps to more than 1 ns). The switching technique used in the quadrature oscillator creates a large initial voltage for fast startup (0.5 ns) and locks the initial phase of the oscillations to the input clock for pulse coherence. The measured phase noise thus matches that of the clock signal, with a relatively low phase noise of -70 dBc/Hz and -100 dBc/Hz at 1kHz and 1 MHz offsets respectively. The entire circuit operates in switched-mode with a low average power consumption of less than 2.2 mW and 14.8 mW at 50 MHz and 600 MHz pulse repetition frequencies, or below 11 pJ of energy for each of the four differential quadrature pulses. It occupies an active area of less than 0.41 \mm^2. [ABSTRACT FROM PUBLISHER]

Adder structures utilizing SiGe Hetero-junction Bipolar Transistor (HBT) digital circuits are examined for use in high clock rate digital applications requiring high-speed integer arithmetic. A 4-gate deep test structure for 32-bit addition using a 210 GHz fT process has been experimentally verified to operate with 37.5 ps delay or 26.7 GHz speed. The paper documents a unique blend of CML and ECL circuit innovations, which is needed to obtain this result. The chip is estimated to have a power-delay product of 109 ps-W at a device temperature of 85^\circ~\C. A low power design is shown to have a power-delay product of 48 ps-W at 21.7 GHz. Speed-power trade-offs are explored through pure ECL logic and varying current. Additionally, with next generation SiGe HBTs, this work shows that 40 GHz is achievable at slightly above room temperature. [ABSTRACT FROM PUBLISHER]

Approximate computing is established as a design alternative to improve the energy requirements of a vast number of applications, leveraging their intrinsic error tolerance. Voltage over-scaling (VOS) is one of the most energy-efficient approximation techniques, but its exploitation is still limited due to the large errors it induces. In this work, we investigate, for the first time, the resiliency of negative capacitance transistor (NCFET) technology to VOS in comparison to conventional CMOS technology. Our work reveals that circuits implemented using the NCFET technology exhibit much less timing errors under VOS due to the inherent voltage amplification provided by the ferroelectric layer. NCFET is one of the very promising emerging technologies that is rapidly evolving for low-power circuit as it enables the transistors to switch faster without the need to increase the voltage. We demonstrate how NCFET technology allows circuit designers to effectively employ VOS to boost the efficiency of their approximate circuits, while still keeping the induced errors marginal. Our analysis shows that the VOS-resilience of NCFET circuits enables maximizing the voltage decrease and thus, NCFET based VOS approximate circuits achieve from $1.83\times$ up to $2.78\times$ higher energy reduction compared to the corresponding FinFET circuits for the same error bounds. [ABSTRACT FROM AUTHOR]

Excessive timing margins are usually added in the wide-voltage-range design due to process, voltage and temperature (PVT) variations, which can be eliminated by adaptive voltage scaling (AVS). Some traditional Razor-based designs replace endpoint flip-flops with latches and ensure data sampled correctly. The duration of time-borrowing and the short path problem make the minimum-delay constraint worthy of consideration. To overcome the minimum-delay problem in the latch-based error detection and correction (EDAC) techniques, we propose a solution using a pulsed-latch and transition detector (TD). This method utilizes time-borrowing characteristics of the latch to ensure the correct function. To detect timing violations and minimize area overhead, we design a 15-transistor transition detector which is able to operate at a wide voltage range, from near-threshold voltage (NTV) to super-threshold voltage (STV). To minimize the overhead of pulse generators, a physical allocation-aware pulse generator insertion algorithm is presented to identify each desired group of a pulse generator and a pulsed-latch group. The proposed scheme is implemented in an 8-bit AES circuit through an automatic insertion flow and fabricated in a 28nm CMOS process. Chip measurements demonstrate that the whole design achieves up to 64.3% energy saving as compared to the conventional worst-case design at a small price of 4.3% area overhead. [ABSTRACT FROM AUTHOR]

A high-speed dynamic biasing technique is presented for reducing op amp power in discrete-time, multistage, analog circuits employing op amp sharing. To exploit typical power scaling in such circuits, a charge pump, of which the on-times of up and down currents are controlled by two comparators, performs rapid change of the op amp bias condition between a low-current mode and a high-current mode during nonoverlapping clock periods of the two phase clocks. The errors caused by finite comparator delay are compensated for by embedding intentional offset voltages in the comparators, which are implemented by using asymmetric differential input pairs in the comparators. To verify the efficacy of the proposed biasing technique, an 11-b pipelined analog-to-digital converter (ADC) has been implemented using 0.15- \mu \textm devices in a 28-nm CMOS technology. With a 20-MHz sampling clock, the ADC achieves a 61.8-dB SNDR while consuming a 2.24-mW power from a 1.8-V supply. The MDAC and ADC power are reduced by about 45% and 30%, respectively, compared with a conventional pipelined ADC employing an op amp in each MDAC. Owing to the simple structure of the proposed dynamic biasing, the prototype ADC occupies only 0.052 mm2. [ABSTRACT FROM AUTHOR]

In this article, a fully digital system to detect and correct setup/hold time violations in digital circuits, is presented. The proposed system benefits from simple, low-power, small-area, and easy-to-modify design. The system is composed of two separate blocks, detector and corrector connected through a 2-bit control signal. The detector is placed near flip-flops or memory elements and sends control signals to the corrector. Corrector circuitry consists of only CMOS inverters and a multiplexer, either after global clock source to correct clock globally or before the elements to correct them locally. Because of its simplicity, this system can be repeatedly used throughout the chip. Also it is proved that the correction circuitry may be realized by employing only a few CMOS inverters without any need for adjusting the delay of the inverters. Furthermore, mathematical proof for the ability of the inverter-based correction circuitry is provided. The system continuously monitors and corrects any setup/hold time violations up to the highest possible operating frequency a given process allows. [ABSTRACT FROM PUBLISHER]

This work focuses on generation of quadrature clocks with high phase accuracy and low noise, while reducing area and power consumption. The design objective is to make these quadrature oscillators suitable for applications in power- and area-constrained SOCs. We demonstrate in this work quadrature clock generation using parametric capacitance modulation in CMOS technology. We present a quadrature-generation method that is based on parametric energy transfer to an LC resonator. The phase-sensitive nature of parametric pumping is used to generate a signal in quadrature with an incoming clock signal. The design also provides the capability of phase interpolation about quadrature, which is useful in many applications. The detailed system implementation is demonstrated and experimentally verified through a prototype in 65 nm CMOS. [ABSTRACT FROM AUTHOR]

A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UIpp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 psrms. The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm^2 only. It dissipates 12.4 mW from 1 V supply. [ABSTRACT FROM AUTHOR]

A novel Dual Mode Square (DM^2) adder is proposed. The DM^2 adder achieves low energy, high performance and small area by combining two independent techniques recently proposed by the authors: dual-mode logic (DML) and dual-mode addition (DMADD). DML is a special gate topology that allows on-the-fly adaptation of the gates to real time system requirements, and also shows a wide energy-performance tradeoff. DMADD is probability based circuit architecture with a wide energy-performance tradeoff; however its utilization in a pipelined processor requires multi-cycle operation in some cases. We show how DML circuits avoid this requirement, and thus make it possible to transparently plug-in the DM^2 adder and derive full benefits from the DMADD. Previous work showed that the DMADD can lead to energy savings of up to 50% at the same clock cycle, compared to conventional CMOS solutions. Simulation results in a 40 nm standard process shows that the proposed DM^2 approach achieves additional energy savings of 27% to 36% for 64-bit and 32-bit adders, respectively, compared to DMADD. [ABSTRACT FROM PUBLISHER]

A new low voltage charge pump is developed to help start up a step-up converter in energy harvesting applications. The proposed charge pump is the first to utilize both backward control scheme and two branches of charge transfer switches (CTSs) to direct charge flow. The backward control scheme uses the internal boosted voltage to dynamically control the CTSs' gate, and the two branches utilize both NMOS and PMOS to implement their switching structure. The combination of backward control scheme and two-branch operation allows the CTSs to be completely turned on and off. Thus, the reverse charge sharing phenomenon and switching loss are significantly reduced, which effectively improves pumping efficiency. The last stage is specially designed to improve the charge pump's charge and capacitance drivability. Using subthreshold operation and body-bias technique, the charge pump and its clock generator can operate under a low voltage supply. The proposed charge pump circuit is designed in a standard 0.18 \mum CMOS process. It consists of 6 stages, each with a 24 pF pumping capacitor (total 288 pF pumping capacitance area). Under a 320 mV supply, the measured output voltage of the proposed charge pump can rise from 0 to 2.04 V within 0.1 milliseconds. [ABSTRACT FROM AUTHOR]

Wide fan-in dynamic multiplexers are one of the critical circuits of read-out paths in high-speed register files. However, these dynamic gates have poor noise immunity, which is aggravated by their wide fan-in structure, and their high switching activity consumes significant power. We present new footer voltage feedforward domino (FVFD) and static-switching pulse domino (SSPD) designs for dynamic multiplexers. Both improve noise tolerance, and both reduce the switching power by limiting the voltage swing on the large bitline capacitance through the introduction of dual dynamic nodes. The FVFD technique is based on charge sharing, while SSPD employs a conditional pulse generator to achieve a limited-switching behavior. Adopting these dual dynamic node techniques, we implemented 32-word\,\times\,16-bits/word (0.5-Kb) 1-read, 1-write ported register files in a 1.2-V, 65-nm low-VT CMOS process. Although the SSPD and FVFD techniques respectively require 2.4 and 1.4 times more area than the established single-keeper domino technique, comparative analysis through simulations and measurement results suggests that they can be advantageous in terms of both read power and noise immunity. [ABSTRACT FROM PUBLISHER]

An all-digital 90^\circ phase shift delay lock loop (DLL) is presented, which is robust against the delay mismatch caused by process variation. Each of the four 90^\circ phase shift blocks accurately aligns its output to a 90^\circ shifted phase using its own ring oscillator and locking delay code. It is analytically proved that the phase shift accuracy of the proposed 90^\circ phase shift block is always higher than that of the conventional all-digital 90^\circ phase shift DLL. The harmonic locking problem is prevented by a ring oscillator and a counter. An area-efficient binary-to-thermometer converter is proposed to reduce the area overhead caused by the delay-line control logic. A fast operating frequency with a finer resolution is achieved through the fine delay range selector and the resistance controlled fine delay unit. The proposed 90^\circ phase shift DLL is implemented using a 45-nm CMOS process. The phase shift accuracy errors at the 90^\circ and 270^\circ phases are 0.43^\circ and 1.01^\circ, respectively, when the maximum locking delay code difference between the four 90^\circ phase shift delay lines corresponds to \pm 9.97^\circ at 800 MHz. It proves that the DLL corrects the significant phase error caused by process variation. The power consumption is 3.3 mW at 800 MHz. [ABSTRACT FROM AUTHOR]

Dual read port 6-transistor (6T) SRAMs play a critical role in high-performance cache designs thanks to doubling of access bandwidth, but stability and sensing challenges typically limit the low-voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32 nm metal-gate partially depleted SOI process technology, for low-voltage applications. Hardware exhibits a robust operation at 348 MHz and 0.5 V with a read and write power of 3.33 and 1.97 mW, respectively, per 4.5 KB active array when both read ports are accessed at the highest switching activity data pattern. At a 0.6 V supply, an access speed of 1.2 GHz is observed. [ABSTRACT FROM PUBLISHER]