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The article invites, papers from authors for a special issue of the journal "IEEE Transactions on Electron Devices" on "Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices."

The article presents the invitation of the journal to interested individuals to submit papers and articles on memory, logic and CMOS devices.

Describes the above-named upcoming special issue or section. May include topics to be covered or calls for papers. [ABSTRACT FROM AUTHOR]

The article offers information on electronics devices, complementary metal–oxide–semiconductor (CMOS) logic, power and memory. Topics discussed include electronics devices with features related to experimental results and theoretical model; include advanced transitory with features of self-heating effect and variability; and discusses power devices like the metal–oxide–semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar transistor (IGBT).

Oxide semiconductors are highly attractive for fabrication of large-area thin-film electronics because of their high electrical performance, low process temperature, high uniformity, and ease of industrial manufacturing. n-type oxide semiconductors, such as InGaZnO, are highly developed and have already been commercialized for backplane drivers of flat-panel displays. To date, developing CMOS technology is still an urgent issue in order to build low-power electronic circuits based on oxide semiconductors. In this paper, various CMOS circuits, including inverters, NAND, NOR, XOR, d-latches, full adders, and 7-, 11-, 21-, and 51-stage ring oscillators (ROs), are fabricated based on sputtered p-type tin monoxide and n-type InGaZnO. The inverters show rail-to-rail output voltage behavior, low average static power consumption of 8.84 nW, high noise margin level up to ~40% supply voltage, high yield of 98%, and high uniformity with negligible standard deviation. The NAND, NOR, XOR, d-latches, and full adders show desirably ideal input–output characteristics. The performances of ROs indicate small stage delay of $\sim 1~\mu \text{s}$ , extremely high uniformity and high yieldwhich are essential for large-area thin-film electronics. This paper may inspire constructions of low power, large area, large scale, and high-performance transparent/flexible CMOS circuits fully based on oxide semiconductors for applications beyond flat-panel displays. [ABSTRACT FROM AUTHOR]

Inverter delay is often evaluated as $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{\text {dd}}$ is the supply voltage, and ${I}_{\text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{\text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ delay metrics. However, $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{\text {stack}}$) developed in this paper maintains simplicity of the original ${I}_{\text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $\textit {CV}_{\text {dd}}/{I}_{\text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation. [ABSTRACT FROM AUTHOR]

To effectively solve the crosstalk issue in high-density crossbar array (CBA), high rectifying characteristics should be introduced in the resistance random-access memory (ReRAM) device, and in-depth understanding of the affecting factors on rectifying properties is essential for the large-scale application of ReRAM. In this paper, a high-performance self-rectifying device with CMOS compatible Pd/HfO2/TaOx/Ta structure was demonstrated in a 1-kb CBA. Forming-free, self-compliance, and high uniformity characteristics were successfully achieved. By modulating the thickness of the HfO2 rectifying layer, the rectifying ratio of device could be achieved as high as $\sim 2\times 10^{\textsf {3}}$ under ±3 V at low-resistance state (LRS). It was also experimentally confirmed that the selected unit cell in high-resistance state (logically the “ OFF” state) was stably readable when it was surrounded by unselected LRS (logically the “ ON” state) cells, in an array of up to $32 \times 32$ cells. Furthermore, a model based on interfacial barrier modulation and defects trapping/detrapping was proposed to elucidate the impact of the dielectric thickness on the self-rectifying characteristics of the device. The results presented in this paper provide a great potential for selector-free high-density memory applications. [ABSTRACT FROM AUTHOR]

This paper analyzes the performance of mosaic nonimaging passive infrared (PIR) sensors fabricated by the CMOS–SOI–MEMS technology. The elementary sensor, forming a subpixel, is a thermally isolated nanomachined CMOS transistor, dubbed TMOS, operating at subthreshold. The mosaic uncooled PIR sensors are composed of several TMOS subpixels, which are electrically connected, either in parallel or in series as well as a combination of both options. These mosaic sensors, which are manufactured by nanofabrication methods, exhibit enhanced performance and robust manufacturing on wafer level. The overall figures of merit of these sensors, which are modeled in this paper, indicate why they are most suitable for consumer electronics, including smart homes, wearables, Internet of Things as well as mobile applications. [ABSTRACT FROM AUTHOR]

In this paper, we report on the assessment of self-amplified silicon–oxide–nitride–oxide–silicon (SONOS) memory device architecture for sub-50-nm gate length (${L}_{g}$) through calibrated simulations. Self-amplification (SA) effect in tunnel field-effect transistor-based SONOS (T-SONOS) memory device has been analyzed. Results show that memory window ($\Delta {W}$) in T-SONOS cell increases as buried oxide thickness increases due to capacitive coupling between the front and back gates. Although the enhanced $\Delta {W}$ can also be achieved in inversion-mode SONOS (I-SONOS) device, its performance is deteriorated when the gate length is scaled down. We have compared the performance of I-SONOS and T-SONOS memory devices for ${L}_{g}$ varying from 100 to 25 nm. Results highlight that I-SONOS device cannot be programmed at ${L}_{g} ={25}$ nm and thus deteriorate the memory operation. However, SA T-SONOS at ${L}_{g} = {25}$ nm achieves ${W} \sim {6}$ V. In addition, the effect of underlap on the performance of T-SONOS cell has been analyzed, and it is shown that memory operation of 25-nm T-SONOS device can further improved with a drain side underlap of 20 nm. This paper provides new opportunities to design SA T-SONOS memory device for the next-generation nonvolatile memories. [ABSTRACT FROM AUTHOR]

The application of capacitive deep trench isolation (CDTI) as a shared vertical transfer gate (VTG) in a back-side-illuminated CMOS image sensor pixel is investigated using 3-D device-level simulations. The parasitic capacitance existence between CDTI and deeply buried pinned photodiode (BPD), and also between CDTI and floating diffusion (FD) region, makes the charge transfer process more difficult. In order to design a lag-free pixel and obtain complete charge transfer from BPD to FD, various considerations regarding the device-level design should be taken into account which is discussed in this paper. A CDTI neighboring two pixels can be functionalized as a shared VTG. Using CDTI as shared VTG facilitates pixel miniaturization and can result in more circuit integration at the pixel surface. This paper proposes a ${2}\,\,\mu \text{m} \times {2}\,\,\mu \text{m}$ pixel with CDTI as shared VTG, an equilibrium full-well capacity of 4605 e−, and a complete charge transfer from BPD to FD. [ABSTRACT FROM AUTHOR]

4H-silicon carbide (SiC) is a suitable candidate for high-temperature and radiation prone applications, due to its superior electrical and material properties. Several researchers have demonstrated small-scale logic circuits, entirely in 4H-SiC; however, to build a complete electronic module in 4H-SiC, a memory component is yet to be developed. This paper presents for the first time the design, optimization, and performance analysis of a 4H-SiC-based bipolar memory column including a static random access memory cell and peripherals, designed for voltages as low as 5 V. The memory column has average noise margins of 2 V and delays in the range of few nanoseconds at room temperature. The proposed memory architecture also demonstrates robust operation across a wide range of temperatures (27 °C–500 °C) with stable noise margins and speeds. This paper validates the potential of developing memory architectures in 4H-SiC, which operates reliably for varying conditions, paving the way to build complete electronic systems entirely based on 4H-SiC. [ABSTRACT FROM AUTHOR]

Performance limitations of superjunction (SJ) devices due to charge imbalance (CI) are analyzed in this paper. It is demonstrated that in the presence of CI, the specific on-resistance has a quadratic dependence on blocking voltage, similar to a conventional drift region. We also show that by designing the SJ structure with an optimally modified pillar doping, we can achieve better performance under conditions of CI. The design guidelines presented in this paper are applicable to any semiconductor, although all calculations are based on silicon carbide. [ABSTRACT FROM AUTHOR]

In this paper, a ZnO-based semiconductor thin film memristor (300 nm in thickness) device is fabricated using metallic top and bottom electrodes by direct-current reactive magnetron sputter. The memristive characteristics of the device were completed by time-dependent current--voltage (I--V-t) measurements, and the typical pinched hysteresis I--V loops of the memristor were observed. This paper is continued with the designing memristor emulator circuit, which has only four MOS transistors. The proposed circuit is suitable both for emulating the fabricated memristor and for using general memristor-based applications. Any circuit blocks such as a multiplier or active element are not used in the circuit to obtain memristive characteristics. All results of the proposed memristor emulator circuit are compatible with general characteristics of the fabricated semiconductor device. The MOSFET-based proposed memristor emulator circuit is laid out in the Analog Design Environment of Cadence Software using 180-nmTSMC CMOS process parameters and its layout area is 366 μm². So as to show its performance, the dependences of the operating frequency and process corner as well as effects of radical temperature changes have been investigated in the simulation results section. [ABSTRACT FROM AUTHOR]

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip. [ABSTRACT FROM PUBLISHER]

The metal–semiconductor interface is fundamental to any semiconductor device and the success of advanced technology nodes critically depends upon the minimization of the contact resistance at the interface. In this paper, we calculate the electronic structure of a metal–semiconductor interface (TiGe/Ge contact) within the framework of first-principles density functional theory simulations. We report the modulation of the Schottky barrier height with respect to the different phases of TiGe metal and different crystallographic orientations of Ge substrate. We further compute the I – V characteristics of the TiGe/Ge contact with nonequilibrium Green’s function formalism, using a two-terminal device configuration. The calculated transmission spectrum allows us to extract the contact resistance at the metal–semiconductor interface. Furthermore, the onset of Ohmic contact for p-doped TiGe/Ge interface is identified by studying the I – V characteristics as a function of increasing active carrier concentration. We find that a doping concentration of 1e21 is sufficient to transform the Schottky contact into Ohmic and thereby achieve a least possible contact resistance at the interfaces. Our paper thus provides useful physical insights into the nanoscale details of the TiGe/Ge interfaces and can guide further process development to minimize the contact resistance. [ABSTRACT FROM PUBLISHER]

Wafer-scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing. [ABSTRACT FROM PUBLISHER]

The effect of temperature and parasitic photocurrent on event-based dynamic vision sensors (DVS) is important because of their application in uncontrolled robotic, automotive, and surveillance applications. This paper considers the temperature dependence of DVS threshold temporal contrast (TC), dark current, and background activity caused by junction leakage. New theory shows that if bias currents have a constant ratio, then ideally the DVS threshold TC is temperature independent, but the presence of temperature dependent junction leakage currents causes nonideal behavior at elevated temperature. Both measured photodiode dark current and leakage induced event activity follow Arhenius activation. This paper also defines a new metric for parasitic photocurrent quantum efficiency and measures the sensitivity of DVS pixels to parasitic photocurrent. [ABSTRACT FROM PUBLISHER]

Gate dielectric damage caused by both internal and external stresses is becoming worse because of aggressive complementary metal–oxide–semiconductor (CMOS) scaling. However, conventional technologies for damage reduction using thermal annealing during fabrication have some limitations. As a result, there is a growing demand for technologies that will cure CMOS damage as a new paradigm for improving long-term reliability. This review paper reexamines self-recovery technologies, which are fully compatible with CMOS fabrication. Although self-heating has long been considered an unwanted operating side effect, it can also be favorably utilized to cure damage. Generated Joule heat arising from device operation can uniformly anneal the gate dielectric and effectively recover damage in various devices, such as conventional logic, memory, and aerospace CMOS devices, as well as thin-film transistors for displays. [ABSTRACT FROM AUTHOR]

This paper demonstrates the existence of dark current blooming in pinned photodiode (PPD) CMOS image sensors (CISs) with the support of both experimental measurements and TCAD simulations. It is usually assumed that blooming can appear only under illumination, when the charge collected by a pixel exceeds the full well capacity (FWC) (i.e., when the photodiode becomes forward biased). In this paper, it is shownthat blooming can also appear in the dark by dark current leakage from hot pixels in reverse bias (i.e., belowthe FWC). The dark current blooming is observed to propagate up to nine pixels away in the experimental images and can impact hundreds of pixels around each hot pixel. Hence, it can be a major image quality issue for the state-of-the-art PPD CISs used in dark current limited applications, such as low-light optical imaging and should be considered in the dark current subtraction process. This paper also demonstrates that one of the key parameter for dark current optimization, the transfer gate bias during integration, has to be carefully chosen depending on the application because the optimum bias for dark current reduction leads to the largest dark current blooming effects. [ABSTRACT FROM AUTHOR]

A transient and static hybrid-triggered active clamp is proposed in this paper. By skillfully incorporating different detection mechanisms, the proposed clamp achieves enhanced static electrical overstress protection capability over the transient one. Furthermore, the proposed clamp achieves improved electrostatic discharge reaction speed in both human body model and charged device model events over the static one. Moreover, the superior transient-noise immunity of the proposed clamp over traditional transient ones is essentially revealed in this paper. The proposed clamp is successfully verified in a 65-nm bulk CMOS process. In addition, the design flexibility of the proposed clamp for other processes is also deeply discussed in this paper. [ABSTRACT FROM PUBLISHER]

In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with L\mathrm{ eff}= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for fT , f\mathrm {\mathrm {MAX}} , and NFmin at 26 GHz up to ~13%, ~24%, and ~18% compared with the reference layout scheme, respectively. [ABSTRACT FROM PUBLISHER]

A new generation of thermal sensors based on a suspended thermal transistor MOS (TMOS), fabricated in the standard CMOS-SOI process, released by postetching, has been recently developed. One of the important features of TMOS is its high responsivity due to the transistor built-in amplification and subthreshold operation enabling a wide range of battery applications. This paper focuses on a new gas sensor, dubbed GMOS, based on the TMOS. The GMOS is a catalytic gas sensor (pellistor-like), and as such detects combustible gases in air. The CMOS-SOI technology combined with tungsten metallization enables operation at very high temperatures (450 °C was tested). The sensors and readout are processed with the same CMOS-SOI technology. Accordingly, the GMOS sensor, processed in low-cost CMOS-SOI technology, promises to become the widely accepted gas sensing approach for mobile applications, including wearables, smart homes, as well as smartphones. [ABSTRACT FROM AUTHOR]

In this paper, several fundamental pseudo-CMOS digital circuits with n-type indium tin oxide-stabilized ZnO thin-film transistors (TFTs) were implemented and investigated. The optical transmittance of circuits varied from 77% to 92% throughout the visible wavelength band. Electrically, the operation frequency of inverters, nor gates, nand gates, D latches, and D flip flops were all found to exceed 10 kHz with a supply voltage of 10 V. Besides, 13-stage ring oscillators could be operated at 42 kHz with a propagation delay time of $0.92~\mu \text{s}$ when the supply voltage was set as 20 V. Among the state-of-the-art transparent designs, these proposed circuits based on the ITO-stabilized ZnO TFTs exhibited high-speed performance, which were promising as building blocks for transparent electronics with moderate frequency requirements. [ABSTRACT FROM AUTHOR]

Silicon-based quantum computing has the potential advantages of low cost, high integration density, and compatibility with CMOS technologies. The detuning mechanism has been used to experimentally achieve silicon two-qubit quantum gates and programmable quantum processors. In this paper, the scaling behaviors and variability issues are explored by numerical device simulations of a model silicon quantum gate based on the detuning mechanism. The device physics of quantum gates modulation, tradeoff between device speed and quantum fidelity, and impact of variability on the implementation of a quantum algorithm are examined. The results indicate the attractive potential to achieve high speed and fidelity silicon quantum gates with a low operation voltage. To scale up, reducing the device variability and mitigating the variability effect are identified to be indispensable for reliable implementing a quantum computing algorithm with the silicon quantum gates based on the detuning mechanism. A scheme to use the control electronics for mitigating the variability of quantum gates is proposed. [ABSTRACT FROM AUTHOR]

In this paper, a novel on-chip circuit design approach is proposed using hybrid coupling technique. Taking advantage of this technique, a microwave bandpass filter (BPF) is proposed as a design example for proof of concept. Based on stub-loaded stepped-impedance transmission lines and folded stepped-impedance meander line from different metal layers, the proposed BPF can generate three transmission zeros (TZs) and two transmission poles (TPs), which are excited through the hybrid mutual couplings between the inductive and capacitive metals. To understand the principle of this configuration, an equivalent LC-circuit model is presented and simplified, of which the TZs and TPs of the proposed BPF are estimated by the extracted transfer function. The calculated results exhibit good agreements with the simulated and measured ones. In addition, the bandwidth and center frequency of the proposed BPF can be tuned flexibly. Finally, to further demonstrate the feasibility of this approach in practice, the structure is implemented and fabricated in a commercial 0.13- $\mu \text{m}$ SiGe (Bi)-CMOS technology. The measurement results show that the proposed BPF, whose chip size is 0.39 mm $\times0.45$ mm (excluding the test pads), can realize a wide bandwidth from 19.7 to 33.2 GHz with a return loss of 15.8 dB and insertion loss of 3.8 dB at the center frequency of 26.5 GHz. [ABSTRACT FROM AUTHOR]

On-chip electrostatic discharge (ESD) protection device with large dimension can sustain high-ESD current, but the parasitic capacitance of the ESD protection device will increase the difficulty of impedance matching and degrade the bandwidth for broadband radio frequency (RF) applications. The traditional distributed ESD protection circuit can achieve good impedance matching, but it has a worse ESD robustness because of larger resistance caused by the input inductor. In this paper, a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier is proposed to attain good ESD robustness without degrading the RF performance. The proposed ESD protection circuit has been successfully verified in a 40-nm, 2.5-V CMOS process to sustain a human-metal model of 5 kV. The proposed ESD protection circuit is suitable to protect the broadband RF circuits in advanced nanoscale CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents the detailed physical insights into the silicon-controlled rectifier (SCR) phenomena in planar equivalent Fin SCR devices. The complexity and roadblocks for SCR triggering in FinFET technology are explored. Implication of contact silicidation on Fin SCR turn- ON is discussed in detail. Device design approaches are discussed for efficient Fin-enabled SCRs. In this direction, a novel contact engineering scheme in Fin technology is disclosed for improved SCR action. Moreover, a novel Fin SCR is presented, which offers area-efficient electrostatic discharge current carrying capability. [ABSTRACT FROM AUTHOR]

This paper reports the fabrication of MEMS-based guided two-beam piezoelectric energy harvester for low-frequency operation. A highly c-axis-oriented zinc oxide thin film of 2.5- $\mu \text{m}$ thickness covered with 0.5- $\mu \text{m}$ plasma-enhanced chemical vapor deposition SiO2 is sandwiched between the aluminum electrodes to form split electrodes on the two beams. A pyramidal-shaped seismic mass that gives a higher electric potential is realized by bulk micromachining using CMOS compatible 25 wt% tetramethyl ammonium hydroxide wet etching. The thickness of the beams is optimized using deep reactive-ion etching to achieve a low-frequency operation. COMSOL Multiphysics has been used to study the stress distribution to optimize the dimension and placement of the split electrodes. The optimized split electrodes give a reduced resonance frequency by 4.2% when compared with previously used electrode pattern ensuring maximum electric potential generation for guided two-beam structure. The resonance frequency of the device measured experimentally using laser Doppler vibrometer comes to be 466 Hz. The packaged device exhibits a maximum sensitivity of 1.5089 mV/m/s2 in the frequency range from 160 to 1000 Hz. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal–ferroelectric–insulator–semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications. [ABSTRACT FROM AUTHOR]

In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts. [ABSTRACT FROM AUTHOR]

Tunnel field-effect transistors (TFETs) have shown attractive device performance making them a potential candidate to replace MOSFETs in future technologies. However, the inherent ambipolar characteristic of TFETs poses challenge in digital applications. The gate–drain overlap in conventional TFETs efficiently suppresses the ambipolar conductivity. On the other hand, in dopingless TFETs (DLTFETs), due to the requirement of separate gate and drain electrodes for electrostatically creating doped and intrinsic regions, gate–drain overlap cannot be realized. However, gate–drain overlap can be effectively realized using oversized back gate (OBG). Therefore, in this paper, we have proposed a DLTFET with an OBG that effectively suppresses ambipolar behavior even upto gate voltage ${V}_{\textsf {GS}} = -\textsf {1}$ V. Misalignment study is also performed for the gate length ${L}_{G} = \textsf {20}$ nm which has been reported to degrade the tunneling phenomenon at gate–source interface. It is observed that the proposed device is more tolerant to misalignment due to its OBG. The OBG also provides improvement in ${I}_{\textsf {on}}$ ($\sim 1.4\times $) due to enhanced band bending at gate–source interface. To demonstrate the advantage of proposed device architecture over existing architectures, we compare the performance of proposed device with other existing techniques such as dual material gate and dual material drain architectures. The OBG-DLTFET has shown better ambipolar and on-state characteristics in comparison to the existing techniques. [ABSTRACT FROM AUTHOR]

In this paper, 4 pairs of commercial 12-channel electronic and photonic dies have been assembled on a patterned wet etched silicon interposer for a terabit/s class optical interconnect. In the scheme, the optical dies are flip-chip bonded to form a ${4} \times {12}$ optical matrix with 250- $\mu \text{m}$ pitch in both the ${x}$ - and ${y}$ -directions. A single compact optical connector, which is designed based on the commercial PRIZM MT ferrule, is employed to enable a single and direct connection of four fiber ribbons to all 48 channels. The alignment tolerance of the suggested optical connector is tested, and the best case loss is 1.0 dB. The electrical interface, for the connection of CMOS ICs and vertical-cavity surface-emitting laser dies, is designed and patterned on the silicon interposer. The process and assembly are also detailed. In performance testing, clear eye patterns for all the 48 channels are captured at 15 Gb/s with a pseudorandom bit stream 231 – 1 patterns. The bit error rate curves of all the channels are recorded at 10 Gb/s and show a receiver sensitivity spread of less than 2.1 dB across all 48 channels at 10−12 level. In addition, crosstalk effects are also characterized, showing a negligible power penalty of less than 0.2 dB. The fully assembled module can offer for the first time 0.72 Tb/s optical data output, within an area of 1.32 cm2 by using low cost processes and commercially available dies. [ABSTRACT FROM AUTHOR]

Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon–germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage ($\text{V}_{T}$) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage (${I}_{ \mathrm{\scriptscriptstyle OFF}} $) variability and in the halo region at the drain sidewall for $\text{V}_{T}$ variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ random variability for scaled voltages. [ABSTRACT FROM AUTHOR]

The accurate calculation of switching voltage (${V}_{s}$) is necessary for the reliable and low-power operation of monolithic 3-D (M3D) CMOS-nanoelectromechanical (NEM) hybrid reconfigurable logic circuits because ${V}_{s}$ corresponds to the operating voltage (${V}_{\text {dd}}$) of NEM memory switches. In this paper, based on the Euler–Bernoulli equation, the physics-based analytical model is proposed to determine ${V}_{s}$. The accuracy of the proposed model is verified by both the finite-element analysis and experimental results. Our proposed model shows >3% error compared with experimental data. Also, the design guidelines of NEM memory switches are presented in terms of minimum ${V}_{s}$ (${V}_{s\_{}{m}}$) and device dimensions. [ABSTRACT FROM AUTHOR]

In this paper, a new model is successfully introduced to describe an ion-sensitive field-effect transistor in a TCAD tool. To model this device accurately, the model should evaluate surface charge density behavior of electrolyte and insulator interface as well as ion concentration according to different pH values. Performance and accuracy of the model have been examined through assessing parameters such as sensitivity and signal-to-noise ratio (SNR). The effect of silicon active layer thickness on the sensitivity and SNR and its maximum condition and relevance to silicon thickness are investigated. Results show that the model can predict the device responses accurately, in accordance with experimental reports. The proposed model reveals that although the top oxide to buried oxide capacitance ratio does not change the SNR; the silicon active layer thickness can affect it efficiently. [ABSTRACT FROM AUTHOR]

In this paper, the low-temperature (≤150 °C) fabrication and characterization of flexible indium–gallium–zinc–oxide (IGZO) top-gate thin-film transistors (TFTs) with channel lengths down to 280 nm is presented. Such extremely short channel lengths in flexible IGZO TFTs were realized with a novel manufacturing process combining two-photon direct laser writing (DLW) photolithography with Ti/Au/Ti source/drain e-beam evaporation and liftoff. The resulting flexible IGZO TFTs exhibit a saturation field-effect mobility of 1.1 cm $^{\textsf {2}}\cdot \textsf {V}^{-\textsf {1}}\cdot \text {s}^{-\textsf {1}}$ and a threshold voltage of 3 V. Thanks to the short channel lengths (280 nm) and the small gate to source/drain overlap ($5.2~\mu \text{m}$), the TFTs yield a transit frequency of 80 MHz (at 8.5-V gate–source voltage) extracted from the measured S-parameters. Furthermore, the devices are fully functional when wrapped around a cylindrical rod with 6-mm radius, corresponding to 0.4% tensile strain in the TFT channel. These results demonstrate a new methodology to realize entirely flexible nanostructures and prove its suitability for the fabrication of short-channel transistors on polymer substrates for future wearable communication electronics. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

In this paper, bias modulated synapse transistor based on ultrathin molybdenum disulfide (MoS2) was fabricated. By applying positive and negative pulses, the device can imitate the excitation and inhibition behaviors of natural synapse, respectively. The baseline and change percentage of postsynaptic current (PSC) can be tuned by the back-gate bias, enabling the reconfiguration of the weight profile in machine learning. The PSC change tendency between single pulse and multiple pulse tests is opposite, which is very useful to mimic natural synapse recovery feature. Besides, as MoS2 is utilized as channel materials, the device can be vertically scaled down to 2 nm, which is very hard for traditional materials. [ABSTRACT FROM AUTHOR]

A bond-pad charging protection design for charging-free reference transistor test structures was examined. This paper concludes that truly charging-free reference transistors cannot be realized with the one conventional bond-pad charging protection design of protecting transistor gates only. This, however, can be achieved by simultaneously protecting all terminals of the reference transistors. The simulations, in this paper, reconfirm the earlier important experimental conclusion that placing protection device(s) at transistor gates may inflict severe damage to transistor gate oxides instead of protecting them. The implication of the above suggests that attention may be required in a circuit layout design stage for those transistors which gates begin to connect, at high metal layers, to highly efficient leakage paths, such as protection devices, n-type source/drain diffusion regions, and VSS bus lines, which tend to pull transistor gates to low potentials during a backend integrated-circuit manufacturing process. This paper proposes an optimum bond-pad charging protection design for the truly charging-free reference transistor test structures by considering a minimum usage in a layout space and minimum gate oxide stress in the fuse zap-off process. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of quantum capacitance on the intrinsic inversion-capacitance ( C\mathrm{ inv}) characteristics of high-mobility multigate III–V-on-insulator nMOSFETs through a numerical simulation corroborated by the theoretical calculation. Nonmonotonic C\mathrm{ inv} characteristics stemming from the energy dependence of 1-D density-of-states and significant C\mathrm{ inv} degradation due to quantum capacitance have been found in trigate In0.53Ga0.47As and InAs devices based on the ITRS 2018–2024 technology nodes. This paper indicates that, to compensate the excess inversion-charge ( Q\mathrm{ inv} ) loss due to quantum capacitance, the needed mobility gain of the trigate InGaAs and InAs devices (against the Si counterparts) should be at least $\sim 3\times $ and $\sim 4\times $ , respectively. This paper also suggests that the quantum-capacitance-induced Q\mathrm{ inv} loss can be mitigated by raising the fin aspect ratio of the III–V multigate device. [ABSTRACT FROM AUTHOR]

In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF- and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes. [ABSTRACT FROM PUBLISHER]

An eight-FinFET fully differential SRAM cell is proposed in this paper to achieve stronger data stability and enhanced write ability. The p-type transistors are used for data access during read operations and transmission gates are employed to force new data into the cell during write operations. At the nominal process corner, the proposed SRAM cell enhances the read data stability, write voltage margin, and write data transfer speed by up to $2.7\times $ , 15.8%, and 76%, respectively, while consuming similar leakage power as compared with the previously published six-FinFET fully differential SRAM cells in 15-nm FinFET technology. Under isodata stability, the proposed SRAM cell allows the lowering of the power supply voltage by up to 44.3% as compared with the other SRAM cells that are investigated in this paper. [ABSTRACT FROM AUTHOR]

A near-threshold voltage ( $V_{{\rm {th}}}$ ) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed for super- $V_{{\rm {th}}}$ operation cannot achieve the target SRAM bit-cell margins such as the hold stability, read stability, and write ability margins in the near- $V_{{\rm {th}}}$ region. The recently proposed SRAM bit-cell s with read buffer suffer from the problems of low read 0 sensing margin and large read 1 sensing time in the near- $V_{{\rm {th}}}$ region. This paper proposes a read buffer with adjusted the number of fins or $V_{{\rm {th}}}$ to resolve the problems in the near- $V_{{\rm {th}}}$ region. This paper also proposes a design method for pull-up, pull-down, and pass-gate transistors to achieve the target hold stability and presents an effective write assist circuit to achieve the target write ability in the near- $V_{{\rm {th}}}$ region. [ABSTRACT FROM AUTHOR]

In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 nm FinFET CMOS technology is used to illustrate the sensitivity to process-induced fin shape variation and to motivate this paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out to evaluate the transistor performance ahead of silicon. Draft-diffusion simulations calibrated to the ensemble Monte Carlo simulation results are used to explore the process and the statistical variability space. This has been enabled by the automation of the tool flow and the dataset handling. The interplay between the process and the statistical variability has been examined in details. A two-stage compact model strategy is used to capture the interplay between process and statistical variability. To close the DTCO loop, the static noise margin and write noise margin sensitivity to cell design parameters and variability in FinFET-based SRAM designs are studied in details. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model of the full well capacity (FWC) in pinned photodiode (PPD) CMOS image sensors. By introducing the temperature dependence of the PPD pinning voltage, the existing model is extended (with respect to previous works) to consider the effect of temperature on the FWC. It is shown, with the support of experimental data, that whereas in dark conditions the FWC increases with temperature, a decrease is observed if FWC measurements are performed under illumination. This paper also shows that after a light pulse, the charge stored in the PPD drops as the PPD tends toward equilibrium. On the basis of these observations, an analytical model of the dynamic behavior of the FWC in noncontinuous illumination conditions is proposed. The model is able to reproduce experimental data over six orders of magnitude of time. Both the static and dynamic models can be useful tools to correctly interpret FWC changes following design variations and to accurately define the operating conditions during device characterizations. [ABSTRACT FROM AUTHOR]

During recent years, high- \(k\) spacer materials have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance that restricts researchers using these devices in high-performance circuits. For the first time, this paper demonstrates the usage of high-k spacer material with an optimized length for effective reduction of circuit delay and an improvement in robustness. An improvised symmetric dual- \(k\) spacer (SymD-k) underlap trigate FinFET architecture termed as SymD-k is employed for this purpose. From extensive 3-D simulations, this paper demonstrates that SymD-k device significantly improves overall circuit delay and robustness (noise-margins) with fully capturing the fringe capacitance effects. A CMOS inverter and a three-stage ring-oscillator (RO3) are adopted to carefully investigate the performances. In comparison with the conventional device, the SymD-k device speeds up the RO3 circuit by 27% and 33% using high-k spacer dielectric HfO2 and TiO2, respectively. However, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effect of underlap length and supply voltage on SymD-k-based RO3 delay over the conventional ones are also dealt in. [ABSTRACT FROM AUTHOR]

In this paper, high-gain hybrid complementary inverter was first designed and fabricated by coupling cosputtered ZnSiSnO and solution-processed semiconducting single-walled carbon nanotubes (SWCNTs). Field-effect transistors with ZnSiSnO and SWCNT networks show high electrical performance and acceptable bias stability. ZnSiSnO thin-film transistor shows field-effect mobility of 11.6 cm2/ $\text {V}\cdot \text {s}$ , threshold voltage of 0.98 V, and subthreshold swing of 0.18 V/decade. The corresponding values for the SWCNT transistor are 10.2 cm2/ $\text {V}\cdot \text {s}$ , 0.59 V, and 0.21 V/decade, respectively. The ZnSiSnO/SWCNT inverter shows excellent performance with a voltage gain of 41.5, a high noise margin of 2.62 V, and a low noise margin of 1.86 V at a small ${V}_{\text {DD}}$ of 5 V. The peak consumption is only $3.2\times 10^{8}$ W at ${V}_{\text {DD}} = 5$ V. Our finding underscores the coupling of cosputtered ZnSiSnO and solution-processed semiconducting SWCNT as an alternative strategy to the high-performance inverter development and has the potential for widespread technological applications. [ABSTRACT FROM AUTHOR]

Novel designs for the gain elements in electron multiplying (EM) charge-coupled devices (CCDs) have been implemented in a device manufactured in a low-voltage CMOS process. Derived with help from TCAD simulations, the designs employ modified gate geometries in order to significantly increase the EM gain over traditional structures. Two new EM elements have been demonstrated with an order of magnitude higher gain than the typical rectangular gate designs, achieved over 100 amplifying stages and without an increase in the electric field. The principles presented in this paper can be used in CMOS and CCD imagers employing electron multiplication in order to boost the gain and reduce undesirable effects such as clock-induced charge generation and gain aging. [ABSTRACT FROM AUTHOR]

This paper revisits the physics of current filamentation in grounded-gate NMOS (ggNMOS) devices and presents new physical insights which were not addressed in earlier works. A clear distinction between electrical and thermal instabilities is presented. Moreover, filament dynamics under electrical and thermal instability in both silicided and silicide blocked devices is discussed while highlighting observations which contradict with established theory of current ballasting. Interplay between electrical and thermal instabilities and its dependence on the presence or absence of silicide blocking is explored further. Filament spreading in ggNMOS devices and it is dependence on silicide blocking is discussed. Finally, while using the developed physical insights, missing correlation between TLP and HBM extracted failure current of silicided ggNMOS device is explained. [ABSTRACT FROM AUTHOR]