Search

Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 $\mu \text{m}$) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage (${V}_{{\text {knee}}})$ of −1.2 V compared with −1.9 V for the Inv MOSFETs (at ${V}_{g} = {0}$ V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%–90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells. [ABSTRACT FROM AUTHOR]

In this paper, we examine the interplay of two serious reliability issues in MOSFET devices, namely, bias temperature instability (BTI) and hot-carrier degradation (HCD). Most publications are devoted to the characterization of either BTI or HCD, and complex models have been developed to independently describe each degradation mode. However, very limited data are available on the interplay of both degradation regimes, particularly the effect of a drain bias onto the charging and discharging dynamics of oxide traps. Part I of this paper provides an extensive experimental study toward the impact of mixed-mode stress conditions on the dynamics of oxide defects. Here, we present the first microscopic modeling approach beyond a simple electrostatic approximation. We extend the existing nonradiative multiphonon theory by taking nonequilibrium processes such as full carrier distribution functions which include the effect impact ionization along the channel into account. To ultimately validate our framework, we compare simulation results and experimental data for a single-oxide defect as well as a large ensemble of traps in a MOSFET device. We show that our modeling approach accurately captures the rather puzzling measurement trends for a broad stress regime and allows developing the knowledge on how oxide defects can be affected by an increased drain stress. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

In this paper, we explored the characteristic fluctuations induced by various random discrete dopants (RDDs) on gate-all-around silicon nanowire metal–oxide semiconductor field-effect transistors. A 3-D quantum-mechanically corrected transport model was employed to analyze the simulated devices. The statistical results indicate that the variation of threshold voltage ( ${V}_{\text {th}}$ ) not only can be reduced from 28.6% to 10.7% without channel doping and penetration from the source/drain into the channel, but also the variation of 3-dB frequency can be reduced from 8% to 2.7% due to the reduction of the variation of ${V}_{\text {th}}$. We reported that the high-frequency characteristic fluctuations (voltage gain and cutoff frequency) were dominated by electron mobility. This caused by RDDs from the drain extension exhibited less variability than that caused by RDDs from the source extension due to a reduced injection velocity near the S side and a negligible difference in the electron saturation velocity near the D side. This paper provides pertinent information on the design of high-frequency amplifier circuits in relation to devices with RDDs induced by variations in the semiconductor process. [ABSTRACT FROM AUTHOR]

In this paper, a p-channel vertical 4H-silicon carbide (SiC) MOSFET (SiC p-MOSFET) has been fabricated successfully for the first time as a potential candidate for the complementary inverter application. The static characteristics and the robustness, including short circuit and avalanche capabilities of the p-MOSFET, are experimentally tested. Moreover, the comparison between the p-MOSFET and similar rating n-MOSFET is carried out. The short-circuit capability is 15% higher than that of the n-channel MOSFET. Furthermore, this paper also provides the physical insights into the failure mechanism during the short-circuit transient of the p- and n-MOSFET. Meanwhile, an electro-thermal analytical model is proposed to explain the thermal distribution during this transient. Last, the avalanche withstand time of the fabricated SiC p-MOSFET is experimentally demonstrated to be 27% higher than that of the n-channel one. It is concluded that the SiC p-MOSFET could be a competitive power switch applicable for high-frequency complementary inverters. [ABSTRACT FROM PUBLISHER]

This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal–oxide–semiconductor field-effect transistors (n-MOSFETs). The effects of the finger number, channel geometry, and biasing voltages have been tested during irradiation experiments. All Berkeley short-channel insulated gate field-effect transistor model (BSIM) parameters relevant to the transistor properties affected by TID have been modified in an algorithmic flow to correctly estimate the sub-threshold leakage current for a given dose level. The maximum error of the model developed is below 8%. A case study considering a five-stage ring oscillator is simulated with the generated model to show that the power consumption of the circuit increases and the oscillation frequency decreases around by 14%. [ABSTRACT FROM AUTHOR]

In this paper, a physics-based bias-dependent model of single-event transients (SETs) in double-gate (DG) MOSFET suitable for circuit simulation is presented. The existing approaches that use double exponential and dual double-exponential current sources to emulate these transient currents in the circuit simulators depend on the parameters extracted from TCAD device simulations. In order to capture the essential physics behind these current transients in the circuit simulations, there is a need for a physics-based bias-dependent SET current model that considers the electrostatics in the chosen device. The proposed SET current model is developed from the solution of 2-D Poisson’s equation with proper boundary conditions of DG MOSFET. It takes into account the dependence of the transient potential and drain current on linear energy transfer (LET), strike positions, drain and gate biases, device dimensions, and channel doping. The results from the model are validated with the simulation results from TCAD. The SET current model is integrated in Cadence circuit simulator and observed through simulations the voltage perturbation at the output of the CMOS inverter due to heavy ion strike on nMOS transistor in OFF state for different LETs and loads. The proposed model captures the current plateau region effect in CMOS inverter. [ABSTRACT FROM AUTHOR]

This paper presents the first analytical model for the ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) in vertical power FinFETs. The model allows to extract the channel mobility and series resistance and to separate the current conduction through the bulk fin channel and the accumulation-mode metal–oxide–semiconductor (MOS) channel. The model was validated by experiments and simulations. The extracted series resistance was verified by measuring a diode fabricated in the same wafer with the FinFETs. At the same time, simulations using the extracted channel mobility and series resistance agreed well with the experiments. The model was then used to analyze a 1200 V GaN vertical power FinFET. The main ${R}_{ \mathrm{\scriptscriptstyle ON}}$ component was identified to be from the drift layer and the substrate, while the gate-modulated channel resistance only accounts for ~13% of the total device ${R}_{ \mathrm{\scriptscriptstyle ON}}$. Our model enables parameter extraction from the dc characteristics of a single device, and therefore, provides a fast and easy way to understand, analyze, and design vertical power FinFETs. Our model can also be adjusted to allow for fast and accurate parameter extraction in other power transistors with a vertical gate-modulated channel, such as trench MOSFETs. [ABSTRACT FROM AUTHOR]

Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]

To continue with the scaling of high-performance transistors, alternate materials and device architectures are being explored as replacements for contemporary strained-silicon (s-Si) FinFETs. While III–V materials, such as In0.53Ga0.47As, offer higher electron mobilities and injection velocities than s-Si, emerging 2-D materials and nanowire (NW) device architectures promise better immunity to short-channel effects. In this paper, we present a detailed device-level performance comparison of s-Si, In0.53Ga0.47As, monolayer black phosphorus (BP), and WS2-based planar and multigate (Fin and NW) n-MOSFETs across three successive future technology nodes. The analysis incorporates both intrinsic device characteristics obtained from an advanced quantum mechanical simulation tool and the effect of nonidealities using a physics-based analytical model. The results indicate that 2-D materials, such as monolayer BP, offers higher ON currents than s-Si and In0.53Ga0.47As for planar device architectures. However, compared to modern s-Si and In0.53Ga0.47As Fin and NW FETs, monolayer BP and WS2 double-gate MOSFETs are reported to offer lower ON currents due to the smaller footprint at scaled technology nodes. [ABSTRACT FROM AUTHOR]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed for junctionless silicon on insulator ion-sensitive FET for pH sensing applications. The pH sensors detect the change of the hydrogen ion concentration in the aqueous solution. The modeled results show good agreement with the simulation results obtained by using Sentaurus. The electrolyte region has been considered by changing appropriate intrinsic semiconductor material in which the electron and hole charges represent the mobile ions in the aqueous solution. The effect of pH on surface potential, threshold voltage, and drain current has been investigated through model and simulations. In addition, the impact of different gate oxide materials, which act as adhesion layer, has been investigated. The pH response is defined as the amount of threshold voltage shift when the pH (in the injected solution) is varied from lower to higher values. Effect of the electrolyte region thickness on the pH sensitivity has also been discussed in this paper. [ABSTRACT FROM AUTHOR]

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( V\mathrm{ bs} ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive V\mathrm{ bs} due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate. [ABSTRACT FROM PUBLISHER]

In the above paper, Kim et al. present a method for extracting source and drain resistance values in MOSFETs. We explain how the proposed method corresponds to a particular case of the method already proposed by Ortiz-Conde et al. in a seminal work published in 1994 and generalized two years later, which was not cited in the above-mentioned paper. We call attention to the fact that the absence in Kim’s method of the threshold voltage dependence on body-source voltage and such disregard might eventually lead to significant errors. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

In this paper, a super-junction p-type lateral diffused metal–oxide–semiconductor transistor (SJ-pLDMOS) utilizing electron to enhance the current capability is proposed. The proposed SJ-pLDMOS has an n-channel in the drain region and is controlled by an auto-generated voltage signal (${V}_{\mathrm {\textsf {Gn}}}$). The voltage signal ${V}_{\mathrm {\textsf {Gn}}}$ is generated during the ON- and OFF-state of the hole current which flows across an integrated resistor (${R}\text{p}$) implemented in the p-base region. Thus, the proposed SJ-pLDMOS utilizes both hole and electron currents to significantly enhance the current capability. Simulation results show that the current capability of the proposed SJ-pLDMOS without any conductivity modulation effect is comparable with that of a super-junction nLDMOS (SJ-nLDMOS). The total power loss of the proposed super-junction pLDMOS (SJ-pLDMOS) is reduced by about 26.7% and 18% compared with that of the SJ-nLDMOS and Triple Resurf nLDMOS (TR nLDMOS) at a rated load current density of $25~\mu \text{A}/\mu \text{m}$ , respectively. [ABSTRACT FROM AUTHOR]

Using TCAD simulations, the silicon carbide metal–oxide–semiconductor field-effect transistor with p-type floating islands (SiC FLIMOSFET) is systematically investigated in this paper. The doping concentration (NFLI), length (L), and position (D1) of floating islands are optimized according to breakdown voltage (BV), electric field distribution, and on-resistance. The results show that $\text{N}_{\textsf {FLI}} = \textsf {1} \times \textsf {10}^{\textsf {17}}$ cm $^{\textsf {-3}}, \textsf {L}= \textsf {2.5}\,\,\mu \text{m}$ , and $\textsf {D1}=9.0\,\,\mu \text{m}$ are superior values for FLI structure considering tradeoff between BV and on-resistance. With the same BV capacity, the on-resistance of SiC FLIMOSFET is decrease by 32% comparing to the conventional SiC VDMOSFET. Besides, the dynamic property shows 16.5% reduction of FoM $\text{R}_{\textsf {on}}\cdot \textsf {Q}_{\textsf {GD}}$ in the SiC FLIMOSFET. Significantly, comparing to the conventional structure, the electro-thermal simulation indicates that the SiC FLIMOSFET has a higher robustness under short-circuit condition owing to the reduction of thermal stress in SiC/SiO2 interface. All the results show that the SiC FLIMOSFET has a good potential in SiC power device. [ABSTRACT FROM AUTHOR]

Due to outstanding properties of silicon carbide (SiC) and unipolar current conduction mechanism, the active chip size of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) is significantly shrunk, which significantly improves switching performance. However, the termination region cannot be scaled down due to the existence of high breakdown electric field enclosing active region. Therefore, a SiC MOSFET switching loss model considering termination region effect is proposed in this paper with revealing physical insights into termination region during switching process. Furthermore, through theoretical analysis, model establishment, and simulation results, the loss breakdown under various blocking voltages (800, 1000, and 1200 V) for 1-, 3-, and 6-A current rated devices is obtained. ${E}_{\textsf {term}}$ and ${E}_{\textsf {acti}}$ as intrinsic loss of turn-on process make a significant contribution to the total switching loss under fast gate drive condition. The model shows that the turn-on and turn-off losses are under and overestimated, respectively, by using the commonly used electrical measurement. The loss from termination region aggravates the underestimation of turn-on loss and overestimation of turn-off loss further. The proposed loss estimation equation could provide accurate loss to help choose device and design power circuit for power electronic community. The results also raise new perspective to edge termination of efficient/reliable SiC MOSFET for device people. [ABSTRACT FROM AUTHOR]

In this paper, we present physical insights into the role of substrate on the anomalous frequency behavior of small-signal transconductance and output conductance in the ultrathin body and buried oxide fully depleted silicon-on-insulator MOS transistors. Using the simple dc analysis, we attribute this anomalous behavior to the negative feedback originating from both minority and majority carriers in the substrate at different frequency ranges. Through measurements and detailed TCAD simulations, we have shown that back-gate bias and substrate doping strongly modulate the frequency behavior of transconductance and output conductance. It is finally proposed that circuit/device designers can smartly use the back-gate bias and substrate doping to minimize the substrate effect and improve the frequency response of the device intrinsic gain. [ABSTRACT FROM AUTHOR]

In this paper, we propose a misaligned double-gate p-i-n impact ionization MOS (MIMOS) with a deliberate misalignment between the top and bottom gates. The presence of a misaligned bottom gate leads to band-to-band-tunneling of electrons at the source-intrinsic region interface and increases the number of carriers for impact ionization. The electric field redistribution provides a longer transport path for the carriers. Therefore, carriers gain higher kinetic energy, and the impact ionization rate is enhanced in the MIMOS. This results in a significantly lower avalanche breakdown voltage compared to conventional single-gate IMOS structure. Using calibrated 2-D simulations, we demonstrate that MIMOS exhibits a steep subthreshold slope (~6 mV/dec) at a significantly low-supply voltage of (${V}_{\text {DS}}= {0.59}$ V), which is ~48% lower than that of the corresponding single-gate IMOS (${V}_{\text {DS}}= {1.15}$ V). [ABSTRACT FROM AUTHOR]

In this paper, we have comprehensively studied the performance boosts of both nLDMOS and pLDMOS under the mechanical strain. The electrical properties of LDMOS under the uniaxial tensile and compressive strains along the channel direction are examined thoroughly. We find that the uniaxial tensile strain benefits the nLDMOS, and the uniaxial compressive strain benefits the pLDMOS. Because the mechanical strain affects carriers’ transportation in bulk Si and inverted channel distinctly, the strain effects are strongly correlated with the gate voltage, drain voltage, and devices’ dimensions. It is found that the LDMOS with the longer gate length is more preferred for the strain. The piezoresistance coefficients of both nLDMOS and pLDMOS under the uniaxial strain are evaluated for the first time. It is also shown that the mechanical strain can enhance the drain current without the degradation of the breakdown voltage, which suggests a downshift of the ON-resistance versus breakdown voltage curve. [ABSTRACT FROM AUTHOR]

In this paper, a dual-gate laterally double-diffused metal–oxide–semiconductor (DG-LDMOS) device with shallow trench isolation (STI) and sinker at the source side has been proposed. STI and sinker help to provide isolation and reduce the leakage current, respectively, in the device. This is an improvement over a single-gate (SG) LDMOS device when only one gate is used and no STI and sinker are there. The study of both the devices has been carried out using the ATLAS SILVACO simulator. In the simulation studies, all the dimensions and doping parameters of both devices have been kept the same except gate length and channel doping. The distance between two gates of DG-LDMOS device has been kept smaller. This has been done to overcome the island and overlapping issues. The simulation studies have shown a significant improvement in DG-LDMOS device parameters in comparison to the SG-LDMOS device. The DG-LDMOS device provides high breakdown voltage, low ON-resistance, high $f_{\sf {T}}$ and $f_{\sf {max}}$ , low drain-induced barrier lowering, and better output conductance as compared to conventional SG-LDMOS device. These features make the DG-LDMOS device an excellent candidate for RF applications. [ABSTRACT FROM AUTHOR]

The state-of-the-art RF and millimeter-wave circuits design requires accurate prediction of the nonquasi-static (NQS) effects at high frequency for all levels of channel inversion. This paper provides a practical insight to help high-frequency performance assessment of ultrathin body and box fully depleted silicon-on-insulator MOSFETs through a powerful frequency normalization scheme. Frequency dependence of small signal characteristics derived from experimental S-parameters is analyzed and reveals that the transconductance efficiency (${g}_{\textsf {m}}/{I}_{\textsf {D}}$) concept, already adopted as a low-frequency analog figure-of-merit (FoM), can be generalized to high frequency, including under asymmetric operation. We report that the normalized frequency dependence of the generalized transadmittance efficiency (${y}_{\textsf {m}}/{I}_{\textsf {D}}$) FoM only depends on the mobility and inversion coefficient. In addition, this approach is also used to extract essential parameters such as the critical NQS frequency ${f}_{\textsf {NQS}}$. [ABSTRACT FROM AUTHOR]

In this paper, analytical gate capacitance models for a large-signal compact model of AlGaN/GaN high-electron mobility transistors are proposed. Different from the MOSFET devices, different depletion regions on either side of the gate are fully considered for high-voltage GaN devices. The depletion regions are bias-dependent to implement the capacitance models into the large-signal compact model. A transfer function is proposed to characterize the switching behavior of the capacitances between on- and off-states, which is essential to describe all the states of a device, for example, operating at Class-B. Different from previous works, the current saturation phenomenon is taken into account in determining the intrinsic capacitances which are induced by nonstatic channel charge. The capacitance models can be easily implemented into the virtual-source-based model to accurately predict the S-parameters and large-signal output characteristics. [ABSTRACT FROM AUTHOR]

This paper presents the analyses on the self-sustained oscillation of superjunction MOSFET intrinsic diode. At first, the characteristics of the self-sustained oscillation for the superjunction MOSFET intrinsic diode are identified by the double-pulse switching test. The test results show that the self-sustained oscillation with significant self-amplification phenomenon can be triggered during the reverse recovery transient of superjunction MOSFET intrinsic diode. Based on the Sentaurus TCAD simulation, the self-sustained oscillation is reproduced. The simulation results reveal the root cause of the self-sustained oscillation. Due to the snappy reverse recovery of superjunction MOSFET intrinsic diode, the steep slope of diode snap off current can generate high voltage across the common source inductance, which drives the gate–source voltage and turns on the high-side MOSFET. The unexpected MOSFET turn-on can, in return, enhance the steepness of the current slope when the diode snap off. This leads to a positive feedback process and self-sustained oscillation is generated. In the end, based on the theoretical analyses and experimental results, the necessary methods that can suppress the oscillation are presented. [ABSTRACT FROM AUTHOR]

The degradations of electrical parameters for double-trench silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under repetitive avalanche stress are investigated in this paper. The injection of hot holes into the bottom oxide of the gate trench during avalanche process is demonstrated to be the dominant degradation mechanism, while the channel is rarely influenced by the stress. The injected holes attract extra electrons in the SiC layer along the SiC/SiO2 interface, decreasing the ON-state drain–source resistance (${R}_{{dson}}$). Due to this reason, the threshold voltage (${V}_{{th}}$) of the device also reduces slightly. Moreover, other than static electrical parameters, dynamic characteristics including the gate–drain capacitance (${C}_{{gd}}$) and the switching characteristics of the device also degrade. After being stressed by repetitive avalanche stress, the depletion region beneath the bottom of the gate trench gets thinner, leading to the increase in ${C}_{{gd}}$ , which further influences the switching behaviors. The turn- ON and turn- OFF switching times of the device are calculated. It illustrates that the repetitive avalanche stress results in an obvious delay in the turn- OFF procedure, but hardly influences the turn- ON behaviors of the double-trench SiC MOSFET. [ABSTRACT FROM AUTHOR]

A lumped-circuit nonquasi-static (NQS) model, that is applicable for both large-signal transient simulations and a small-signal ac analysis, is developed in this paper. An improved physical equivalent circuit, capturing NQS effects in the millimeter waveband, is derived using a transmission line model, by incorporating the high-frequency longitudinal gate electrode and a channel distributed RC network. The proposed model is implemented in a BSIM-BULK MOSFET model and validated with dc and RF data, obtained from technology computer-aided design device simulations and experimental data. The proposed model is in very good agreement with the data up to ${50}{f}_{t}$. The transient currents, for a gate-voltage switching rate of ${5}\times {10}^{{10}}$ V/s, show excellent match with the data. The dc, transient, and ac simulations using the proposed model are much faster than a 10-segmented MOSFET model. This shows that the proposed model is better than other computationally complex compact models, for most RF applications. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the impact of spacer dielectrics on the ultrascaled silicon gate-all-around junctionless transistor in the ballistic regime based on the in-house 3-D quantum simulator that self-consistently solves mode-space nonequilibrium Green function formalism and Poisson’s equation. Then, the impact of device parameters, such as lengths of source/drain region and channel, channel width, and nanowire direction, on the static performance is also discussed in detail. An available range of spacer dielectric constant is further selected. Results show that the high-k spacer introduced in the ultrascaled junctionless transistor can effectively enhance the direct-current performance of the device and suppress the variation of drain current and subthreshold characteristics induced by the aforementioned device parameters. It will be a great benefit for the junctionless device with a gate-all-around structure as the scaling continues to approach the end of MOSFETs. [ABSTRACT FROM AUTHOR]

TFETs are promising candidates for future low-power logic applications because of their potential for outperforming conventional MOSFETs under reduced supply voltage (${V} _{\textsf {DD}}$). Among all material systems currently being explored, group IV semiconductor SiGe holds the most potential due to its very large scale integration (VLSI) compatibility, mature synthesis techniques, and tunable bandgap, making it more likely to be adopted for future VLSI technologies. It has been shown experimentally that the on-state current (${I} _{\textsf {on}}$) of SiGe TFETs improves significantly with the increasing Ge content. However, increasing the Ge content leads to excessive leakage in the off-state and poses a challenge to the pseudomorphic growth of SiGe. In this paper, the concept of Ge-pocket TFET with a counter-doped pocket is proposed. By confining Ge to the pocket region, the proposed structure circumvents those problems. Both the steep subthreshold swing and high ${I} _{\textsf {on}}$ can be achieved. The proposed TFET also demonstrates excellent scalability in terms of physical gate length (${L} _{\textsf {gate}}$) and ${V} _{\textsf {DD}}$ , which makes it a promising replacement of conventional MOSFETs for low-power logic applications. [ABSTRACT FROM AUTHOR]

In this paper, Si tunnel FETs (TFETs) with the vertical tunneling junction (nVTFETs) were demonstrated by utilizing fabrication processes compatible to those used for conventional Si MOSFETs. The vertical tunneling junction was realized by forming n-type surface pocket regions under gate overlap regions of p-type source extensions only using the ion implantation (I/I). The impacts of carbon (C) coimplantation and formation of offset spacer (OSS) on the TFET performance were examined. As a result, the performance of the fabricated nVTFETs was enhanced by applying the C coimplantation and the OSS formation before the I/I for the vertical tunneling junctions. It has been found, on the other hand, that nVTETs exhibit a reverse short-channel effect, where the threshold voltage increases with decreasing the channel length, and that this effect is correlated with the enhanced temperature dependence of subthreshold slope. These phenomena are attributable to the existence of a thermionic barrier between the source junction and the channel, formed by boron diffusion from the source region. [ABSTRACT FROM AUTHOR]

The degradations of electrical parameters for silicon carbide power MOSFETs under repetitive short-circuit (SC) stress are investigated in detail in this paper. It demonstrates that the generation of negative charges along the gate–oxide interface of the channel region is the dominant degradation mechanism, which results in the increase in the threshold voltage (${V}_{\text {th}}$) and the rise of ON-state resistance (${R}_{\text {dson}}$) under low gate voltage bias condition. Furthermore, degradations of dynamic characteristics including gate charge (${Q}_{\text {g}}$) and switching behaviors of the device after the repetitive SC stress are extracted and analyzed for the first time. It illustrates that the increased ${V}_{\text {th}}$ contributes to the rise of the Miller plateau voltage (${V}_{\text {gp}}$), which further leads to the increase in gate–source charge (${Q}_{\text {gs}}$). Meanwhile, the increase in the turn-ON time and the reduction of turn-OFF time are observed, which are also resulted from the positive shifts of ${V}_{\text {th}}$ and ${V}_{\text {gp}}$ , leading to the rise of turn-ON switching energy (${E}_{{ \text {on}}}$) and the decline of turn-OFF switching energy (${E}_{\text {off}}$), respectively. [ABSTRACT FROM AUTHOR]

In this paper, analytical modeling of a charge plasma-based nanogap embedded surrounding gate MOSFET biosensor for label-free biosensing has been presented and verified with extensive simulated device data. Along the channel, considering parabolic potential profile, surface potential, threshold voltage, and drain currents have been modeled. Sensitivity has been analyzed by measuring the shift in ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{\mathrm{\scriptscriptstyle OFF}}$ and threshold voltage when the biosensor interacts with the neutral or charged biomolecules. Less thermal budgeting scheme with simplified fabrication process flow, i.e., no ion implantation or diffusion can be achieved easily here due to new charge plasma concept. In addition, the issues related to the doping control and random dopant fluctuations have been reduced significantly to make the device immune to the process variation. Hence, the proposed device has been optimized for the enhancement in device electrostatics and sensitivity. Extensive TCAD simulations have been performed to investigate the device parameters and to verify the model data. Hence, the proposed model can be considered as an optimal model of a biosensor for the future reference. [ABSTRACT FROM AUTHOR]

The stress distributions and induced mobility gain in germanium (Ge)-based p-type MOSFETs (pMOSFETs) with an extended channel width are estimated in this paper. Several tin (Sn) concentrations of group-IV semiconductor GeSn alloys integrated with a compressive contact etching stop layer (CESL) are logically analyzed to evaluate the stress impact that results from the high lattice mismatch of embedded GeSn alloys on narrow device channels. Analytic results show that the stress intensity and corresponding mobility gain are enhanced by increasing the Sn concentration in the embedded source/drain GeSn stressors. By contrast, the performance variation of the short-channel Ge-based pMOSFET is strongly dominated by the extended width when the CESL covers the entire device. A mobility gain of up to ~124.07% is achieved for the 22-nm pMOSFET when a 100-nm extended width is considered. Moreover, the entire stress responses of high- ${k}$ /metal gate-last procedure combined with the following CESL deposition are investigated. Analytic results reveal that the stress relaxation along the channel height direction occurs after the poly gate etch process. Consequently, the adoption of a stressed CESL is demonstrated to be an effective approach to remedy the device mobility gain by stress improvement on the channel height direction. [ABSTRACT FROM AUTHOR]

This paper reports the response of an N-channel transparent gate recessed channel (TGRC) metal–oxide–semiconductor field-effect transistor (MOSFET) to X-ray radiation in the 0.5-k–10-krad dose range after irradiation. TCAD simulations for the same have been done to estimate the threshold voltage shift in MOSFET with different radiation dosages. Models accounting for electron–hole pair generation and recombination are applied along with the trap/detrap model for an insulator as well as interface charging. An improvement of 1.11 mV/krad in radiation sensitivity has been found in increasing the oxide thickness from 2 to 6 nm. The results suggest that TGRC-MOSFET can be effectively used as an X-ray dosimeter in the sub-30-nm scale. Along with a signal amplification and processing circuit, this device can find an enormous applicability in clinical and space environments. [ABSTRACT FROM AUTHOR]

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor ${Q}_{F2}={(}{\lambda {E}_{c}}/{R_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}}{)}$ along with ${Q}_{G}$ and ${T}_{j\textsf {max}}$ may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where $\lambda $ and ${E}_{c}$ are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ is the specific on-state electrical resistance, ${Q}_{G}$ is the gate charge, and ${T}_{j\textsf {max}}$ is the maximum junction temperature of the semiconductor power device, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of switching performances between the in-situ oxide, gallium nitride (GaN) interlayer FET (OG-FET) and the conventional GaN metal–oxide–semiconductor FET (MOSFET), and explores the influence of the channel electron mobility on the device switching performance. GaN OG-FET is a novel structure with a pristine GaN layer grown between the gate oxide and the p-GaN enhancing the channel mobility up to 185 cm2/ $\text {V}\cdot \text {s}$ , which is over $3{\times}$ larger than that of the typical reported value (50 cm2/ $\text {V}\cdot \text {s}$) in GaN MOSFET. Owing to the high channel electron mobility, the GaN OG-FET showed a switching loss 30% lower than that of the conventional GaN trench MOSFET. Our results indicate that GaN OG-FET has the potential to attain greater efficiency, particularly at higher frequencies, showing a possible patch toward megahertz range conversions. [ABSTRACT FROM AUTHOR]

When developing silicon carbide (SiC) devices, the reliability of the internal body diode is an important issue. Stacking faults (SFs) are expanded from basal plane defects by using a body diode. Although it is well known that ON-voltage degradation occurs due to SFs, their effects on dynamic reliability have not been studied well. Furthermore, including the effects of SFs, there are not many reports about the dynamic reliability of SiC-MOSFETs. In this paper, a double-pulse switching test using 3.3-kV SiC-MOSFETs was carried out to clarify the failure mechanism of the switching operation of SiC-MOSFETs and effects of SFs on the safe operation area (SOA). Before the switching test, current stress was applied to the body diode of the devices under test (DUTs) to expand the SFs. The circuit configuration was half-bridge type, and a double-pulse gate signal was applied to the lower arm DUT. The switching voltage was 1.8 kV, and the switching current increased at about 8-A steps to failure. As a result, reverse recovery SOA (RRSOA) reliability decreased depending on the amount of SFs in the SiC-MOSFET. Because RRSOA failure was caused by avalanche due to the hole concentration during reverse recovery and the SFs raised local current density, reverse bias SOA (RBSOA) hardly decreased even if SFs containing SiC-MOSFETs were used. This is because RBSOA failure was caused by degradation of the gate isolation layer due to overheating and the temperature coefficient of the SFs electric resistance indicated negative. [ABSTRACT FROM AUTHOR]

In this paper, we present a charge-based compact model for transition metal dichalcogenide (TMD)-based thin-channel field-effect transistor. In model development, first, charge densities at the source and drain terminals are calculated in terms of the applied gate and drain voltages. Calculated charge densities are then used to develop a charge-based drain-current model. Effects of interface traps, ambipolar current behavior, and negative capacitance are then included in the developed drain-current model in terms of charge densities. Predictions of the proposed model are verified by the simulation and experimental data of the TMD channel material-based n-type and p-type MOSFETs. [ABSTRACT FROM AUTHOR]

Recently, sub-10-nm-diameter InGaAs vertical nanowire (VNW) MOSFETs have been demonstrated. The key to this achievement was the use of Ni for the top ohmic contact. In this paper, we present a detailed study of the impact of Ni and Mo contacts on the electrical characteristics of highly scaled InGaAs VNW MOSFETs. Sequential annealing experiments are presented that reveal the optimum temperature for each type of contact. A negative temperature dependence of the ON-resistance of 7-nm-diameter Ni-contacted devices suggests the existence of an energy barrier. We also observe an unexpected transconductance and drain-induced barrier loweirng (DIBL) dependence on transistor diameter in Ni-contacted devices as well as abnormal DIBL asymmetry to swapping source and drain. All these results can be explained by Ni diffusing down the nanowire during the contact annealing process, reducing the effective channel length, and creating a Schottky-barrier drain. [ABSTRACT FROM AUTHOR]

Thermal conductance in multifinger silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is usually modeled at room temperature with a linear dependence on the total gate width, which is valid only when thermal coupling saturates. This paper presents a physically based model for calculating the thermal resistance of SOI-MOSFETs that accounts for progressive thermal coupling as the number of fingers increases and the substrate temperature. The model, extracted from a variety of gate geometries using the ac conductance method, correctly predicts the temperature rise in the device channel up to a substrate temperature of 150 °C. Finally, this simple thermal resistance model, which is applicable to nanometer-scale transistors, can easily be added to circuit simulators. [ABSTRACT FROM AUTHOR]

This paper reports on the suppression of single-transistor latch, an extreme condition of impact ionization (I.I.), in n-type double-gate germanium (Ge) junctionless (JL) transistors. It is shown that JL transistors can be latched to the on-state due to an increase in the I.I. generated power per unit volume with an increase in drain bias, film thickness, oxide thickness, and doping. Latch, being detrimental to switching, can be effectively suppressed by applying an appropriate negative (positive) back-gate bias for n-type (p-type) JL MOSFET. The independent gate operation with appropriate back bias allows the device to overcome latching and regain switching action with a subthreshold swing (${S}$ -swing) <10 mV/decade at room temperature. The work showcases the limit imposed on back bias due to an increase in off-state current due to band-to-band tunneling along with the utility of sidewall spacer to effectively suppress the same. We also show the tunability of hysteresis using back-gate bias. The work highlights a systematic methodology to eliminate single-transistor latch while preserving sub-60 mV/decade switching in Ge JL MOSFETs. [ABSTRACT FROM AUTHOR]

This paper shows the effect of performing consecutive measurement prior to negative bias stress instability (NBSI) on diamond metal–oxide–semiconductor capacitor (MOSCAP). For the first time, time-dependent stress tests have been carried out in order to investigate the stability of the flatband voltage (${V}_{\text {FB}}$) of MOSCAPs through capacitance–voltage (CV) measurements. Two tests have been performed. In the first test, consecutive CV measurements with the device biased from deep depletion to the accumulation regime were performed to monitor the recovery of the ${V}_{\text {FB}}$. In the second test, NBSI technique has been applied. ${V}_{\text {FB}}$ stability has been measured by means of a time-dependent bias stress in which the device was polarized at a fixed negative voltage for a specific time interval prior to performing the next CV measurement. As ${V}_{\text {FB}}$ is directly connected to the effective oxide charge (${N}_{\text {eff}}$), the two different tests allowed the extraction of total amount of ${N}_{\text {eff}}$ that interfered during the measurements. The result observed shows that the postoxidation annealing process induces a strong enhancement of the MOSCAP stability together with a decrease of ${N}_{\text {eff}}$ [ABSTRACT FROM AUTHOR]

Recent advances in the fabrication technology have yielded nanometer-scale InGaAs quantum-well (QW) MOSFETs with extremely low and reproducible external contact and access region resistances. This allows, for the first time, a detailed analysis of the role of ballistic transport in the operation of these devices. This paper presents a systematic analysis of external resistance, ballistic resistance, and channel mobility in InGaAs QW-MOSFETs under near-equilibrium conditions, i.e., under very low drain-source bias. This is an important regime for device characterization. Devices with a wide range of channel lengths, from 70 to 650 nm, are investigated. Our analysis includes the consideration of the impact of carrier degeneracy in the QW channel. We show that unless the ballistic behavior in the intrinsic channel is accounted for, the standard extraction technique for external resistance grossly exaggerates its value as it incorporates the so-called ballistic resistance. By separating out the ballistic resistance, the external resistance in our devices is shown to be extremely low, $74~\Omega $ - \mu \text{m} , including both source and drain sides. This is thanks to our contact-first self-aligned Mo-contact technology. Furthermore, taking the advantage of the wide range of ballisticity of the devices studied in this paper, we demonstrate a methodology to self-consistently extract scattering-dependent effective mobility, mean-free-path length, and ballistic mobility. [ABSTRACT FROM AUTHOR]

In this paper, an optimized structure of 4H-SiC U-shaped trench gate MOSFET (UMOSFET) with low resistance is proposed. The optimized structure adds an n-type region, wrapping the p+ shielding region incorporated at the bottom of the trench gate. The depletion region formed by the p+ shielding region reduces greatly for the high dopant concentration of the added region. This added region also conducts electrons downward and expands the electrons to the bottom of the p+ shielding region. We discussed the influence of dopant concentration and the width of the added region on the breakdown voltage (BV) and the ON-resistance in this paper. A reasonable size and an optimized concentration were chosen for the added region in our simulation. The channel inversion layer mobility was set to 50 cm ^2 /Vs, and the specific ON-resistance and the BV were 1.64 \textm\Omega \cdot cm^2 ( V\mathrm {GS}= 15 V, V\mathrm {DS}= 1 V, and no substrate resistance was included) and 891 V, respectively, using the numerical simulation. [ABSTRACT FROM AUTHOR]

In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 nm FinFET CMOS technology is used to illustrate the sensitivity to process-induced fin shape variation and to motivate this paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out to evaluate the transistor performance ahead of silicon. Draft-diffusion simulations calibrated to the ensemble Monte Carlo simulation results are used to explore the process and the statistical variability space. This has been enabled by the automation of the tool flow and the dataset handling. The interplay between the process and the statistical variability has been examined in details. A two-stage compact model strategy is used to capture the interplay between process and statistical variability. To close the DTCO loop, the static noise margin and write noise margin sensitivity to cell design parameters and variability in FinFET-based SRAM designs are studied in details. [ABSTRACT FROM AUTHOR]