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Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau–Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies. [ABSTRACT FROM AUTHOR]

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier charge density within few discrete subbands. Combining a parabolic approximation of the Poisson equation, the first-order perturbation theory for the Schrödinger subband energy eigen-values and the Fermi–Dirac statistics for the confined carrier density lead to an explicit solution of the dc characteristic in ultrathin JL devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirm its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on JL nanowire devices. [ABSTRACT FROM AUTHOR]

A physics-based threshold voltage model of junction-less (JL) double gate (DG) FETs with vertical structural and doping asymmetry is being proposed in this paper. The numerical implementation of vertical asymmetric doping in the FET devices modeling has been studied extensively. A linear approximation, as suggested in the post-annealed implantation technique, is introduced to account for asymmetric-doped profile falling within the channel thickness. Furthermore, Bhaskar’s approximation of sinusoidal has been implemented in the solution to impart due accuracy in the modeling overextended range of device parameters. Overall, appropriate implementation of these mathematical techniques has reduced the complexity of the full evanescent mode analysis immensely and has together retained the accuracy in the solution. The simplicity of the model has provided flexibility to study structural and doping asymmetry together for JL DG FET. Synopsys Sentaurus Device simulation tool has been used for verification of the model results. [ABSTRACT FROM AUTHOR]

In this paper, we systematically examined the impact of fin height ( H\mathrm{ Fin} ) and fin angle ( \theta \mathrm{ Fin} ) on the ac performance parameters including total gate capacitance ( C\mathrm{ gg} ), RC delay ( C_{\mathrm{ gg}}V_{\mathrm{ DD}}/I_{\mathrm{\scriptscriptstyle ON}} ), cutoff frequency ( f_{T} ), energy ( E ), total power ( P_{\mathrm{ Total}} ), and leakage power ( P_{\mathrm{ Leakage}} ) of hybrid FinFETs at the supply voltage, V\mathrm{ DD} with on-current I\mathrm{\scriptscriptstyle ON} . The RC delay, energy, and total power consumption are the primary factors limiting the operating frequency of the high-performance devices. Therefore, these electrical parameters are needed to be addressed in the architectural level of the fin based devices. In this paper, a calibrated numerical device simulation tool is used to achieve the best device performances of 14-nm hybrid FinFETs. From the simulated current–voltage ( I – V ) and capacitance–voltage ( C – C\mathrm{ gg}V\mathrm{ DD}/I\mathrm{\scriptscriptstyle ON} , fT , CV2, P\mathrm{ Total} , and P\mathrm{ Leakage} are extracted to analyze the effect of H\mathrm{ Fin} and \theta \mathrm{ Fin} on the performance matrices of these devices. In addition, this paper proposes an optimum structural configuration for 14-nm hybrid FinFET architecture for digital application perspective. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

In this paper, we develop an accurate analytical electrostatic potential model for both the n-type and p-type double-gate heterostructure tunnel field-effect transistors (H-TFETs). We solve the Poisson’s equation in four distinct regions inside the device, the depletion regions of the source, channel, and drain, and the drift-diffusion region of the channel, where the mobile charge carriers should be taken into account. It is shown that the model predicts the electrostatic potential profile of the various heterostructure devices with different material systems in all regions of the device operation accurately. The potential model is used for developing a model for the tunneling distance at the given energy level. Due to the physical nature of the models, the influence of the transistor parameters on the electrostatic characteristics of H-TFETs with desired heterojunction materials may be easily pursued. We show that the model results accurately predict the numerical simulation results for different device parameters. [ABSTRACT FROM AUTHOR]

Hexagonal boron nitride encapsulation significantly improves carrier transport in graphene. This paper investigates the benefit of implementing the encapsulation technique in graphene field-effect transistors (GFETs) in terms of their intrinsic radio frequency (RF) performance, adding the effect of the series resistances at the terminals. For such a purpose, a drift-diffusion self-consistent simulator is prepared to get the GFET electrical characteristics. Both the mobility and saturation velocity are obtained by an ensemble Monte Carlo simulator upon considering the relevant scattering mechanisms that affect carrier transport. RF figures of merit are simulated using an accurate small-signal model. Results reveal that the cutoff frequency could scale up to the physical limit given by the inverse of the transit time. Projected maximum oscillation frequencies, in the order of few terahertz, are expected to exceed the values demonstrated by InP and Si-based RF transistors. The existing tradeoff between power gain and stability and the role played by the gate resistance are also studied. High power gain and stability are feasible even if the device is operated far away from current saturation. Finally, the benefits of device unilateralization and the exploitation of the negative differential resistance region to get negative-resistance gain are discussed. [ABSTRACT FROM AUTHOR]

Conventional transistor models are unable to capture the electrical behavior of transistors at cryogenic temperatures. In this paper, a methodology has been developed to calibrate temperature dependence parameters of Berkeley Short-Channel Insulated Gate Field Effect Transistor Model (BSIM3). Rather than modifying BSIM3 equations, the algorithm only changes the values of relevant parameters through noniterative, analytic operations; therefore, it can be implemented in typical circuit simulation tools. Proposed methodology allows to estimate ${I}_{D}$ – ${V}_{\textsf {GS}}$ and ${I}_{D}$ – ${V}_{\textsf {DS}}$ curves of the transistors having different channel lengths and widths even under various operating voltages, including the body bias. The parameter extraction algorithm runs with a reasonable computation cost and can compute parameter sets for transistors at user-defined cryogenic conditions. [ABSTRACT FROM AUTHOR]

Electrolyte-gated field-effect transistor technology is an attractive candidate for printed low-power electronics due to its high field-effect mobility and extremely low-voltage operation. Relying on an additive process, inkjet-printed devices display large process variations due to ink-substrate interactions, sensitivity to environmental conditions, such as temperature and humidity, as well as intrinsic variations of the ink. All of these sources of variations may display themselves in non-Gaussian distributions as suggested by our experiments. In this paper, we therefore propose a generic methodology for variability modeling of printed transistors, based on the Gaussian mixture model, which can be used to model any arbitrary distribution of the transistor model parameters. The proposed methodology was tested on two different data sets and has been used to predict the behavior of a measured printed security circuit as well as transistor dc characteristics. [ABSTRACT FROM AUTHOR]

Ballistic (collision free) and drift-diffusive (collision dominated) transport mechanisms are both present in graphene, and they together contribute in the current conduction in a graphene FET (GFET). In this paper, we propose an analytical drain current model based on ballistic (${n}_{B}$) and drift-diffusive (${n}_{D}$) charge densities, backscattering coefficient (${R}$), and quasi-ballistic mobility ($\mu _{\text {eff}}$). ${n}_{B}$ is calculated using the McKelvey flux theory and ${n}_{D}$ using the surface potential approach. A closed-form analytical expression is derived for the backscattering coefficient, which is valid under both low and high electric field conditions. The effective quasi-ballistic mobility is obtained by considering both scattering-dominated and scattering free mobilities. The proposed model is well aligned with experimental data, in all regions of operation, for single- and double-gate GFETs. [ABSTRACT FROM AUTHOR]

In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated. [ABSTRACT FROM AUTHOR]

The inclusion of quantum effects in the transport direction plays an important role in the extensive research of ultrascaled electronic devices. In this context, it is necessary to study how these phenomena affect different technological architectures in order to conclude which one can be the best candidate to replace standard technology. This paper presents the implementation of direct source-to-drain tunneling effect in a multisubband ensemble Monte Carlo simulator showing its influence in different structures such as fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. The differences in the potential profile and the electron distribution in the subbands for these architectures modify the number of electrons affected by this quantum mechanism and, therefore, their short-channel behavior. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal–ferroelectric–insulator–semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications. [ABSTRACT FROM AUTHOR]

In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts. [ABSTRACT FROM AUTHOR]

This paper presents a generalization of the charge-based model for ultrathin junctionless double-gate (JLDG) field-effect transistors (FETs) by including quantum electron density. The analytical derivation relies on a first-order correction to the infinite quantum well. When restricting the analysis to the first and second quantized states, the free carrier charge distribution and the current in an ultrathin body JLDG FETs are in agreement with numerical TCAD simulations in all the regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. [ABSTRACT FROM AUTHOR]

In this paper, a new model is successfully introduced to describe an ion-sensitive field-effect transistor in a TCAD tool. To model this device accurately, the model should evaluate surface charge density behavior of electrolyte and insulator interface as well as ion concentration according to different pH values. Performance and accuracy of the model have been examined through assessing parameters such as sensitivity and signal-to-noise ratio (SNR). The effect of silicon active layer thickness on the sensitivity and SNR and its maximum condition and relevance to silicon thickness are investigated. Results show that the model can predict the device responses accurately, in accordance with experimental reports. The proposed model reveals that although the top oxide to buried oxide capacitance ratio does not change the SNR; the silicon active layer thickness can affect it efficiently. [ABSTRACT FROM AUTHOR]

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET. [ABSTRACT FROM AUTHOR]

This paper proposes a novel kinetic velocity model (KVM) for the drift-diffusion (DD) transport approach to describe ballistic effects. It also presents a simulation study of the ballistic effect in short-channel InGaAs and silicon FETs. Monte Carlo and subband Boltzmann transport equation results as well as DD simulations using the simple gate length-dependent ballistic mobility proposed in the literature and the KVM model are compared and discussed. Basic concepts, such as the Matthiessen rule and Fermi-Dirac statistics, are analyzed with a view on ballistic transport in devices in the linear and saturation regimes. [ABSTRACT FROM AUTHOR]

In this paper, we report a physics-based compact model for monolayer graphene field-effect transistors (m-GFETs) based on the 2-D Density of States of monolayer graphene and the drift-diffusion equation. Furthermore, the Ward-Dutton charge partitioning scheme has been incorporated to the model extending its capabilities to AC and transient simulations. The model has been validated through comparison with DC and RF measurements from two different long-channel m-GFET technologies. Moreover, values of parasitic elements included in the model are extracted from measurements on dedicated test structures and verified through electromagnetic simulations (EM). Finally, an EM-SPICE co-simulation has been carried out to assess the applicability of the developed m-GFET model for the design of “balun” circuits. [ABSTRACT FROM PUBLISHER]

Spatially resolved precise prediction of local temperature T(\textit x,y,z) is essential to evaluate Arrhenius-activated interconnect (e.g., electromigration) and transistor reliability (e.g., NBTI, HCI, and TDDB). A 3-D finite-element modeling (FEM) do provide excellent results, but the calculation is too time-consuming for a structure that involves eight to ten layers of percolating interconnects, especially for fast turn-around reliability modeling. Here, an analytical model that can quickly/accurately determine \textit T(x,y,z) will reduce the design time of self-heated modern IC. In this paper, we 1) develop a physics-based electrothermal compact model for ICs to predict \textit T(x,y,z) based on the synthesis of effective medium theory, image charge theory, and Rent’s rule; 2) validate our model against 3-D FEM and experimental data; and 3) predict back-end-of-line (BEOL) reliability (i.e., electromigration at each layer) based on the temperature profile. Since our analytical model predicts changes in \textit T(x,y,z) with any given IC’s configuration (e.g., interconnect wire length and number distribution, metal volume fraction in BEOL, heat sinks mechanisms, materials, and type of devices), it suggests new opportunities for optimization of performance and reliability of modern ICs. [ABSTRACT FROM PUBLISHER]

Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer ( T\textsf {FE}) is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of T\textsf {FE} on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing T\textsf {FE} yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as T\textsf {FE} is increased. Depending on the attributes of the underlying transistor, increasing T\textsf {FE} beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of T\textsf {FE} on the circuit energy–delay. Our analysis shows that for high T\textsf {FE} , the delay of the circuit may increase with an increase in supply voltage. However, for voltages <0.25 V, FEFINFETs show an immense promise yielding 25% lower energy at iso-delay. [ABSTRACT FROM PUBLISHER]

This paper presents a compact analytical I – V model for short-channel double-gate transition metal dichalcogenide filed-effect transistors in the subthreshold region. A closed-form expression is proposed for the characteristic length in the scale length approach, which is based on physical device parameters. It is then used to find the channel potential and drain current in the subthreshold region. This model is verified with the numerical results of a nonequilibrium Green’s function (NEGF) simulator. There is good agreement between the results of the proposed model and the numerical NEGF simulations in the subthreshold region, while it captures the effects of the device’s physical parameters. [ABSTRACT FROM PUBLISHER]

With the aid of an analytical and scalable model, this paper explores the design space for negative-capacitance (NC) field-effect transistors (FETs) with a 2D semiconducting transition-metal-dichalcogenide channel. In addition, the impact of back-gate biasing on the design space and the body effect of 2D-NCFETs is also investigated. Our study indicates that, to mitigate the conflict between subthreshold swing and hysteresis and to maximize the design space for the 2D-NCFET, a thin buried oxide and an adequate reverse back-gate bias can be applied to achieve the optimum design. [ABSTRACT FROM PUBLISHER]

A high performance triple-heterojunction (3HJ) design has been previously proposed for tunneling FETs (TFETs). Compared with single HJ TFETs, the 3HJ TFETs have both shorter tunneling distance and two transmission resonances that significantly improve the ON-state current ( I\scriptscriptstyle {\text {ON}} ). Coherent quantum transport simulation predicts that I\scriptscriptstyle {\text {ON}} = 460~\mu \textsf {A}/\mu \textsf {m} can be achieved at gate length \text Lg = 15~\textsf nm , supply voltage V\textsf {DD} = 0.3~\textsf V , and OFF-state current I\scriptscriptstyle {\text {OFF}} = 1~\textsf {nA}/\mu \textsf {m} . However, strong electron–phonon and electron–electron scattering in the heavily doped leads implies that the 3HJ devices operate far from the ideal coherent limit. In this paper, such scattering effects are assessed by a newly developed multiscale transport model, which combines the ballistic nonequilibrium Green’s function method for the channel and the drift-diffusion scattering method for the leads. Simulation results show that the thermalizing scattering in the leads both degrades the 3HJ TFET’s subthreshold swing through scattering-induced leakage and reduces the turn-ON current through the access resistance. Assuming bulk scattering rates and carrier mobilities, the I\scriptscriptstyle {\text {ON}} is dropped from 460~\mu \textsf A/\mu \textsf m down to 254~\mu \textsf A/\mu \textsf m , which is still much larger than the single HJ TFET case. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model for surface potential and drain current in transition metal dichalcogenide (TMD) channel material-based n-type and p-type FETs. The model considers 2-D density of states and Fermi–Dirac statistics along with drift-diffusion transport model and includes velocity saturation and trap state effects. The developed model has been implemented in Verilog-A and is applicable for symmetric double gate as well as top-gated TMD-on-insulator FETs. The presented model is extensively validated with simulation as well as experimental data for different TMD materials-based FETs and shows excellent agreement with both the simulation and the experimental data. We further validate the model at circuit level using experimental data of MoS2 FET-based inverter. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model of drain current in a silicon tunnel FET with a circular gate (CG TFET). The method involves the bifurcation of the complete geometry into a rectangular gate conventional TFET, and the CG TFET itself based on the number of solvable regions of the CG TFET. The 2-D Poisson equation is solved on the regions of focus of each structure, and both the substructures are mathematically connected through conditions of continuity to arrive at the solution for the original geometry. The effect of the circular gate is considered by segregating the circular region into a number of rectangular segments, and solving the Poisson equation on each of them. The model takes into account the effect of drain on channel potential, bandgap narrowing, and quantum correction. The model is validated by comparing the results with outputs from a TCAD simulation tool. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate a graphene nanoribbon FET (GNRFET) with locally embedded Stone–Wales (SW) defects near its drain contact. The simulation procedure is preformed via the self-consistent solution of the full 3-D Schrödinger and Poisson equations. Localized states induced by the SW defects are able to reduce ambipolar conduction and provide higher ON–OFF ratio and attenuated kink effect. Causing outgoing carriers decelerated in the channel, the use of such defected region in the GNRFET yields less vulnerability to hot-carrier degradation than its conventional counterpart. Our proposed structure also enhances the device transconductance, making it more appealing in high-frequency applications. [ABSTRACT FROM AUTHOR]

This paper presents a systematic analytical model development for a sub-45-nm gate length double gate tunnel FET (DG TFET) and assessment of the tunneling current based on classical model under asymmetric circumstances with the ambipolar characteristic. Performance analysis of the tunneling current for a sub-45-nm gate length TFET is performed using Kane’s model by considering high doping in the source and drain regions keeping the channel region low doped. The model explains the variation of tunneling current with the change in oxide thickness under symmetric front and back gate voltages with 5 eV metal work function. The variation in tunnel current is also analyzed for the change in channel thickness under symmetric front and back gate voltages for symmetric oxide thickness. The increase in tunneling current for channel thickness scaling under asymmetric operation of the DG TFET is also efficiently captured by the developed model. The model is compared and verified with Sentaurus TCAD for all bias conditions and good agreement has been achieved. [ABSTRACT FROM PUBLISHER]

In this paper, we have developed a model for the surface potential and the drain current of a dual-material double-gate (DMDG) junctionless FET (JLFET) transistor. A finite-differentiation method has been used to decompose the 2-D Poisson’s equation into two 1-D equations, which allows the modeling of the DMDG structure as two individual single-material double-gate JLFETs. The two 1-D models are then combined using appropriate boundary conditions to provide a simple solution to the complex 2-D Poisson’s equation. The proposed model has been verified for different values of doping concentration ( ND ), oxide thickness ( T\mathrm{ ox} ), and channel thickness ( T\mathrm{ si} ) against the numerical simulations. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical 2-D model for the channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile. The 2-D Poisson equation has been solved by using the evanescent-mode analysis to obtain the potential distribution function in the channel. The position of the conduction path also has been modeled to calculate the potential at different positions of the conduction path. The validity of the proposed 2-D potential and threshold voltage models is shown by comparing the results with the simulation data obtained by a 2-D TCAD ATLAS device simulator. [ABSTRACT FROM AUTHOR]

Switching behavior in electron–hole bilayer tunnel FETs is known to be unaffected by the subthreshold swing limitation of 60 mV/decade imposed by thermal injection, due to the band-to-band tunneling phenomena on which they rely. However, in this paper, we show that, once parasitic lateral tunneling processes are suppressed by means of heterogate configurations, a new physical limitation arises at the onset of tunneling in this type of transistors, resulting from the interplay between field-induced quantum confinement and asymmetric concentrations of electrons and holes inside the channel. We demonstrate that this limitation comes from the fact that, regardless of the band profile sharpness, the tunneling distance at subband alignment cannot be reduced beyond a certain limit, which we find to be dependent on the body thickness and the material properties. [ABSTRACT FROM PUBLISHER]

In this paper, a detailed evaluation of sub-10-nm n-/p-type GaSb–InAs double-gate tunneling FETs (TFETs) is presented. Source underlapping is shown to achieve lower subthreshold swing (SS) in both n- and p-type GaSb–InAs TFETs and is verified with the analytical treatment. The impact of parameter variations on the performance of underlapped TFETs is investigated through atomistic, 2-D ballistic simulations using self-consistently coupled nonequilibrium Green’s function-Poisson approach. Variations in underlap length, underlap doping, fin thickness, and temperature are comprehensively studied. It is shown that the underlap length of 6 nm is optimal for achieving low SS and it is found that the underlapped TFETs can maintain sub-60-mV/decade SS even when 3-nm fin thickness is relaxed by 40%. We also study the potential of TFETs in ultralow-power and high-density dynamic memories. A novel 4T gain cell embedded Dynamic Random Access Memory (e-DRAM) is proposed, which utilizes the low-leakage current of the source-underlapped TFETs to improve the data-retention time to 25 \mu \texts at V\mathrm {DD}=0.35 V, thereby enabling the prospects of e-DRAM at nanoscale gate lengths operating at ultralow supply voltages. [ABSTRACT FROM PUBLISHER]

Symmetric double-gate ferroelectric FETs (SDG-FeFETs) have better short-channel electrical behavior and hold promise in reducing the subthreshold swing below the classical Boltzmann’s limit. Surface potential and drain current models for SDG-FeFETs have already been published in the literature. In this paper, we derive the quasi-static terminal-charge models for these devices, which can be seamlessly integrated into standard circuit simulators using the Verilog-A interface. The terminal-charge models proposed are shown to match very well with exact numerical integration of Ward–Dutton terminal-charge integrals, for all bias conditions. Core compact model for the SDG-FeFET is implemented in a SPICE circuit simulator, and the simulation of different circuits built using SDG-FeFET transistors shows improvement in their switching behavior. [ABSTRACT FROM PUBLISHER]

Polymer FETs generally have a wide subthreshold regime due to a lot of disorder, mainly originated from domain/grain boundaries. Deep state’s charge transport of polymer transistors has not been investigated due to the difficulty in determining the field-effect mobility in the subthreshold region. In this paper, the features of the charge transport in deep and shallow states of polymer transistors will be discussed in detail through an accurate modeling and an analysis of subthreshold behavior in transistors. Charge transport in shallow states can be described by multiple trap and release transport, while hopping transport models, such as variable range hopping or Gaussian disorder-based model, describe well the deeper state’s charge transport. In addition, the transition between the conduction regimes is a function of temperature and carrier density. [ABSTRACT FROM PUBLISHER]

Line-edge roughness induced fin-edge roughness (FER) is the primary source of VT variation in FinFETs. Conventionally, stochastic simulations are performed to predict the device variability due to FER for a technology, which are computationally expensive. An analytical formulation to predict variability due to FER enables understanding of the effect of input parameters as well as provides quantitative results at fractional computational costs. In this paper, we develop and present an analytical model to estimate saturation VT ( $V_{{T\rm {-sat}}}) variability due to FER. The model is capable of capturing the LG and W\mathrm{ fin} ) and variability parameters (correlation length $\Lambda $ and standard deviation $\Delta )$ accurately. The entire $V_{{T\rm {-sat}}}$ distribution obtained by the model is also presented and compared against the $V_{{T\rm {-sat}}} distribution of stochastic simulations to show that the model captures the distribution effectively. We show that not only \sigma VT but even \mu VT is affected by variability parameters. Hence, such modeling is critical to defining nominal FinFET structure ( LG and W\mathrm{ fin} ), which is affected by variability ( $\Lambda $ and $\Delta $ ) especially for scaled FinFETs, where quantum-confinement effects are enhanced. [ABSTRACT FROM PUBLISHER]

A 6T SRAM design at a sub-10-nm node calls for carefully designed transistors so that new leakage mechanisms, such as direct source-to-drain tunneling (DSDT) and short channel effects that lead to I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} degradation, are kept under control. In this paper, we explore asymmetric underlap for mitigating DSDT, thermionic leakage, and for improving I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} of double-gate FinFETs. We demonstrate that for 6T SRAMs, asymmetric underlapped n-FinFETs are superior to symmetric underlap/overlap in improving access time and leakage power. We model the atomistic nature of sub-10-nm FinFET channels, quantum confinement, subband nonparabolicity, and anisotropy latent at such length scales using quantum physics-based simulators instead of the conventional semiclassical, drift-diffusion-based Technology Computer Aided Design tools. Using a device/circuit/system-level codesign approach consisting of NEMO5 quantum mechanical device simulations, HSPICE circuit simulations of a 6T SRAM bit cell, and a system-level analysis of a 8-kB L1 and 4-MB L2 cache, we show that the adoption of optimized asymmetric underlapped n-FinFETs can offer up to 6.5% improvement in L1 cache access times and a 2.3-mW reduction in L2 cache leakage power, while delivering noise margins close to symmetric underlapped n-FinFET-based caches. [ABSTRACT FROM PUBLISHER]

In this paper, an accurate compact model based on physical mechanisms for dual-gate bilayer graphene FETs is presented. This model is developed based on the 2-D density of states of bilayer graphene and is implemented in Verilog-A. Furthermore, physical equations describing the behavior of the source and drain access regions under back-gate bias are proposed. The accuracy of the developed large-signal compact model has been verified by comparison with measurement data from the literature. [ABSTRACT FROM PUBLISHER]

This paper presents a SPICE-like graphene field-effect transistor (GFET) model with an improved carrier mobility analysis. The model considers the mobility difference between the electrons and the holes in graphene, as well as the mobility variation against the carrier density. Closed-form analytical solutions have been derived, and the model has been implemented in Verilog-A language. This was compiled into an advanced design system. The proposed model gives excellent agreement between the simulation results and the measurement data for both the hole and electron conduction simultaneously. The model is suitable for the exploration of GFET-based applications, especially for those using the ambipolar transfer property of GFET. [ABSTRACT FROM PUBLISHER]

In this paper, we present a compact model for graphene resonant channel transistors (G-RCTs) that uses extracted electrical and mechanical parameters to provide an accurate simulation of dc, RF, noise, and frequency-tuning characteristics of the device. The model is validated with measurements on fabricated G-RCTs, which include what we believe to be the first noise measurements conducted on any resonant transistor. The noise model, which considers both electrical and mechanical sources, is used to demonstrate the fundamental differences in the noise behavior of active and passive resonator technologies, and to show how optimization of device parameters can be used to improve the noise performance of RCTs. [ABSTRACT FROM AUTHOR]

This paper presents a simulation study using a novel distributive quasi-ballistic drift diffusion (DD) TCAD model applied to low mobility unstressed and high mobility stressed scaled pMOS devices. The model is implemented in a DD simulator and used to study the gate length dependence of current drives. The new model captures the physically correct potential distribution and gives the correct drive current limit in ballistic devices for both linear current response and current saturation source–drain bias conditions. The diffusive and ballistic transport is connected using a ballistic probability, which relates to the fundamental time scale in the problem—the mean energy relaxation time. The model captures the ballistic velocity degradation from the diffusive limit at linear source–drain biases. It is shown that the DD simulation with the distributive quasi-ballistic model describes the stress ballistic drive gains at high driving field, which are missed by the existing ballistic models. [ABSTRACT FROM AUTHOR]

In this paper, we present a theoretical study of mercury cadmium telluride (HgCdTe)-based unipolar n-type/barrier/n-type (nBn) infrared (IR) detector structures for midwave IR and longwave IR spectral bands. To achieve the ultimate performance of nBn detectors, a bandgap engineering method is proposed to remove the undesirable valence band discontinuity that is currently limiting the performance of conventional HgCdTe nBn detectors. Our proposed band engineering method relies on simultaneous grading of the barrier composition and doping density profiles, leading to efficient elimination of the valence band discontinuity. This allows the detector to operate at | V\mathrm {bias}| <50 mV, rendering all tunneling-related dark current components insignificant and allowing the detector to achieve the maximum possible diffusion current limited performance. [ABSTRACT FROM PUBLISHER]

This paper aims to model asymmetric operation in double-gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concept. In addition to the benefits in terms of compactness and coherence, such equivalence is used to develop a complete charge-based model for independent double-gate junctionless architectures, including mismatch in gate capacitance and material work functions. [ABSTRACT FROM AUTHOR]

This paper presents a model for graphene electrolyte-gated field-effect transistors (EGFETs) that incorporates the effects of the graphene-electrolyte interface and quantum capacitance of graphene. The model is validated using experimental data collected from fabricated graphene EGFETs and is employed to extract device parameters such as mobility, minimum carrier concentration, interface capacitance, contact resistance, and effective charged impurity concentration. The proposed graphene EGFET model accurately determines a number of properties necessary for circuit design, such as current-voltage characteristics, transconductance, output resistance, and intrinsic gain. The model can also be used to optimize the design of EGFETs. For example, simulated and experimental results show that avoiding the practice of partial channel passivation enhances the transconductance of graphene EGFETs. [ABSTRACT FROM AUTHOR]

In this paper, we have worked out a pseudo-2-D-analytical model for surface potential and drain current of a long channel p-type dual material gate gate all-around nanowire tunneling field-effect transistor. The model incorporates the effect of drain voltage, gate metal work functions, thickness of oxide, and silicon nanowire radius. The model does not assume a fully depleted channel. With the help of this model, we have demonstrated the accumulation of charge at the interface of the two gates. The accuracy of the model is tested using the 3-D device simulator Silvaco Atlas. [ABSTRACT FROM AUTHOR]

In this paper, a novel concept is introduced to improve the radio-frequency (RF) linearity of partially depleted (PD) silicon-on-insulator (SOI) MOSFET circuits. The transition due to the nonzero body resistance (R \(_{\rm Body}\) ) in output conductance of PD SOI devices leads to linearity degradation. A relation for R \(_{\rm Body}\) is defined to eliminate the transition and a method to obtain transition-free (TF) circuit is shown. 3-D numerical analysis of body-contacted devices is carried out to extract the TF body resistances. To identify the output conductance TF concept and its application to RF circuits, a 2.4-GHz low-noise amplifier (LNA) is further analyzed. Mixed-mode device-circuit analysis is carried out to simultaneously solve device carrier transport equations and circuit SPICE models. Fast Fourier transform calculations on the output signal are performed to compute harmonic distortion figures. Comparing the conventional body-contacted (CBC) and TF SOI LNAs, third harmonic distortion and total harmonic distortion (THD) are improved by 16% and 24%, respectively. Two-tone test is used to analyze third-order intermodulation distortions. Third-order output intercept point is improved in TF SOI LNA by 17% comparing with that of the CBC SOI LNA. The results demonstrate superior advantage in application of TF design concept to SOI MOSFET circuits. [ABSTRACT FROM AUTHOR]

Analytical models for the tunnel FETs are very vital to understand the underlined physics and to optimize various device structures in reasonable times. One of the most interesting models, published by Wu et al., is a pure analytical model that includes the dual-modulation effects. This analytical model gives accurate results compared with TCAD simulations. Therefore, the equations provided in this model were considered a base for a lot of other published models. However, three expressions are erroneous in the mentioned paper and should be revised for the exact replication of the model equations and scientific correctness of the simulation results. In this comment, the expressions presented on page 2693 of Section III-B and Section III-C regarding the surface potential in the inversion regime and the total channel surface potential, respectively, are corrected. The symbols used in this comment are the same as utilized in the reference journal. [ABSTRACT FROM AUTHOR]