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Magnetic tunnel junctions (MTJs) with low switching current, high thermal stability, and small device size are strongly preferred for low-power, high-reliability, and high-density spintronic memory and logic applications. The research of MTJs from shape in-plane magnetic anisotropy to interfacial perpendicular magnetic anisotropy (i-PMA) has successfully paved the way down to 20-nm scale, below which, however, the i-PMA approach reaches a physical limit in sustaining sufficient thermal stability while achieving low-power spin transfer torque switching. Recently, studies have been reported a new approach to pave the way toward sub-10-nm MTJs satisfying the requirements by revisiting shape perpendicular magnetic anisotropy (s-PMA). In this paper, we present a compact model of the sub-10-nm s-PMA MTJ device, which captures both the static and dynamic physical behaviors. This model is SPICE-compatible for hybrid MTJ/CMOS circuit designs. This paper is expected to push forward the development of sub-10-nm-scale MTJ-based spintronic memory and logic circuits. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

In this paper, we present an effective switching current model ( I\textsf {eff} ) for inverter followed by a transmission gate structure (Inv-Tx) based on its switching trajectory. Unlike an inverter or NAND/NOR gates, where I\textsf {eff} depends only on nMOSFET (pMOSFET) current for a falling (rising) transition, it is a function of both nMOSFET and pMOSFET currents for an Inv-Tx cell. The proposed model is verified against HSPICE simulations for a wide range of supply voltages and fan-outs at different technology nodes (e.g., 180, 130, and 65 nm). The model predicts the transition delay values with an average (maximum) error of 7% (11%) compared with HSPICE simulations. Synopsys TCAD Sentaurus simulations at 32-nm technology node are also used to validate the basic model assumptions. To demonstrate the utility of our model, design of some representative circuits while incorporating layout-dependent effects and inverse-narrow-width effect is presented. Finally, we show that a 256X1 multiplexer and a static D-flip-flop, with their transistor sizes and layout, optimized using the proposed model improves the performance of these circuits significantly over the conventional design methodologies. [ABSTRACT FROM PUBLISHER]

3-D integrations are unavoidable task for new emerging memories, including resistive switching random-access memory (RRAM), in order to overcome the market-leading nand flash. However, an RRAM crossbar array (CBA) suffers severe read margin degradation due to the sneak current, which becomes even more critical as the memory density increases with the 3-D integration. In this paper, we extend the two-port readout scheme for a 2-D CBA, proposed in our previous work, to the 3-D vertical structure. A closed-form expression of the operating principle is derived, and HSPICE simulation using a $32\times 32\times8$ vertical RRAM CBA considering practical circuit parameters verifies feasibility of the two-port scheme to the 3-D CBA. [ABSTRACT FROM AUTHOR]

Although spin transfer torque (STT)-based magnetic tunneling junction (MTJ) owns advantages of nonvolatility, nonlimited endurance, and fast write/read, its demand for high current density significantly casts a shadow over its future prospects. Recently, a novel three-terminal MTJ cell that combines voltage-controlled magnetic anisotropy (VCMA) effect and negative capacitance (NC) effect is proposed. Drawing support from the NC amplified VCMA effect and the three-step operation scenario, this novel MTJ cell can dramatically lower the energy consumption to fJ as well as keep high operation speed within nanoseconds. The feasibility of the proposed NC enhanced VCMA spintronics device for memory and logic application is proved by extensive physical simulation in our previous work. However, a SPICE compatible compact model of the proposed NC enhanced VCMA spintronics device is still demanded for circuit and system level evaluation. In this paper, we provide an accurate and fast compact model of NC enhanced VCMA device for both memory and logic applications. [ABSTRACT FROM AUTHOR]

We present a physics-based compact model that captures the behavior of phase-transition materials. The model includes a self-heating module that captures the change in temperature with device operation and the resulting phase change. This is the first compact model that captures the temperature-dependent multidomain switching and the hysteresis behavior seen in such devices. The model is implemented in Verilog-A and validated with experimental data for various geometries and temperatures. It is further coupled with industry standard BSIM-BULK, ASM-HEMT, and BSIM-CMG models for SPICE simulation and validated for various phase-transition FETs, illustrating the previously proposed steep switching effect and a subthreshold slope below the Boltzmann limit of 60 mV/decade. [ABSTRACT FROM AUTHOR]

We report on measurements and modeling of ferroelectric (FE) HfZrO/SiO2 FE–dielectric FETs, which indicate that many of the phenomena attributed to negative capacitance (NC) can be explained by a delayed response of FE-domain switching—referred to as transient NC (TNC). No traversal of the stabilized NC branch is required. Modeling is used to correlate the hysteretic properties of the FE material to the measured transient and subthreshold slope (SS) behavior. It is found that steep SS can be understood as a transient phenomenon and is present when significant polarization changes occur. The experimental signature of the TNC is investigated, and guidelines for detecting it in measured data are outlined. The technological implications of FE polarization switching are investigated, and it is found that NCFETs relying on it are not suitable for high-performance CMOS logic due to voltage, frequency, and hysteresis limitations. Requirements for experimental evidence of stabilized S-curve behavior are summarized. [ABSTRACT FROM AUTHOR]

The focus of this paper is to understand the impact of the material properties of GaN, exploited using a vertical device, in power switching by estimating switching loss. The study was performed with a cascoded current aperture vertical electron transistor (CAVET). The normally OFF device was simulated and analyzed using a Silvaco ATLAS 2-D drift diffusion model integrated to SPICE-based circuit simulator. Besides evaluating the performance space and, hence, potential application space for GaN CAVETs, this paper presents significant accomplishment in establishing a device to circuit model, thereby, offering a reliable method of evaluating GaN-based power transistors. The accuracy of the model was established through the excellent agreement of simulated data with the data sheet specs of a commercial cascoded GaN high electron mobility transistor. The model was successfully applied to compare SiC MOSFETs with GaN CAVETs. A cascoded GaN CAVET has $2\times $ faster switching time, $3\times $ lower switching loss compared with standard commercial SiC MOSFET, owing to the higher electron mobility in GaN. Operating at frequencies of megahertz with low power loss, a GaN CAVET will, therefore, lead to smaller converter size and higher system efficiency. [ABSTRACT FROM PUBLISHER]

The current-induced perpendicular magnetic anisotropy magnetic tunnel junctions (p-MTJs) offer a number of advantages, such as high density and high speed. As p-MTJs downscale to $\sim 40$ nm, further performance enhancements can be realized thanks to high spin-torque efficiency, i.e., lower critical current density and higher thermal stability. In this paper, we investigate the origin of high spin-torque efficiency and give a phenomenological theory to describe the critical current reduction due to the subvolume activation. Based on various physical theories and structural parameters, a compact model of nanoscale MTJ is developed and demonstrates a satisfactory agreement with experimental results. Dynamic, static, and stochastic switching behaviors have been addressed and validated. Then, we perform mixed simulations for hybrid MTJ/CMOS read/write circuits, magnetic random access memory, and magnetic flip-flop to evaluate their performance. Analyses of energy consumption are given to show the prospect of MTJ technology node miniaturization. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) relies on the voltage-driven formation/disruption of a conductive filament (CF) across a thin insulating layer. Due to the 1-D structure of the CF and discrete nature of defects, the set and reset states of the memory device generally display statistical variability from cycle to cycle. For projecting cell downscaling and designing improved programming operations, the variability as a function of the operation parameters, such as the maximum current in the set process and maximum voltage in the reset process, need to be evaluated and understood. This paper addresses set/reset variability, presenting statistical data for HfOx-based RRAM and introducing a physics-based Monte Carlo model for switching statistics. The model can predict the distribution of the set state as a function of the compliance (maximum) current during set and distribution of the reset state as a function of the stop (maximum) voltage during reset. Numerical modeling results are finally presented to provide additional insight into discrete fluctuation events. [ABSTRACT FROM AUTHOR]

Emerging nonvolatile memories based on resistive switching mechanisms pull intense research and development efforts from both academia and industry. Oxide-based resistive random access memories (OxRAM) gather noteworthy performances, such as fast WRITE/READ speed, low power, high endurance, and large integration density that outperform conventional flash memories. To fully explore new design concepts, such as distributed memory in logic or biomimetic architectures, robust OxRAM compact models must be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we propose a physics-based compact model used in electrical simulator for bipolar OxRAM memories. After uncovering the theoretical background and the set of relevant physical parameters, this model is confronted to experimental electrical data. The excellent agreement with these data suggests that this model can be confidently implemented into circuit simulators for design purpose. [ABSTRACT FROM PUBLISHER]

The aim of this paper is to introduce a compact model for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) implemented in Verilog-A to assure easy integration with electrical circuit simulators. It takes into account the effects of voltage-dependent perpendicular magnetic anisotropy, temperature-dependent parameters, thermal heating/cooling, MTJ process variations, and the spin-torque asymmetry of the Slonczewski spin-polarization function in the switching process. This translates into a comprehensive modeling that was adopted to investigate the writing performance under voltage scaling of a $256\times256$ STT- magnetic random access memory array implemented at three different technology nodes. Obtained results show that scaling from 30- to 20-nm node allows a write energy saving of about 43%, while the supply voltage that assures the minimum-energy write operation increases. [ABSTRACT FROM PUBLISHER]

In spite of the apparent simplicity of the system under study, compact modeling of complementary resistive switching (CRS) devices, i.e., two antiserially connected memristive structures, is by no means straightforward. This requires a deep understanding of the voltage drops occurring across the circuit elements and correct treatment of the so-called snapback (SB) effect typical of the breakdown process of a thin dielectric film in an MIS or a MIM structure. The SB effect fundamentally consists in a sudden reduction of the device resistance caused by the formation of a filamentary path spanning the insulator. Beyond this point, the filament widens keeping the voltage drop across its extremes constant. The consequence of disregarding this effect is clearly distinguishable in the simulated curves: progressive openings of the on-state windows for both positive and negative voltages instead of abrupt ones. In this paper, a modification is introduced in the original memdiode model for memristive devices in order to account for this remarkable feature. Ta2O5-based CRS devices are considered to demonstrate the suitability of our approach. [ABSTRACT FROM AUTHOR]

This paper reports on modeling and analysis of power delivery network (PDN) impedance and switching noise in through silicon via (TSV)-based 3-D integration. PDN is simulated in SPICE with the combination of lumped-element models and distributed-element models, where the elements are extracted from full-wave electromagnetic modeling. PDN impedance explicitly distinguishes the contributions from off-chip PDN and on-chip PDN, and reveals the TSV-induced resonant effect associated with the 3-D chip stack. The simultaneously switching noises in PDN are simulated and analyzed in different frequency regions, in which 3-D integration has distinct impacts on the PDN impedance. [ABSTRACT FROM AUTHOR]

The nonlinear junction capacitances of power devices are critical for the switching transient, which should be fully considered in the modeling and transient analysis, especially for high-frequency applications. The silicon carbide (SiC) MOSFET combined with SiC Schottky Barrier Diode (SBD) is recognized as the proposed choice for high-power and high-frequency converters. However, in the existing SiC MOSFET models only the nonlinearity of gate-drain capacitance is considered meticulously, but the drain–source capacitance, which affects the switching commutation process significantly, is generally regarded as constant. In addition, the nonlinearity of diode junction capacitance is neglected in some simplified analysis. Experiments show that without full consideration of nonlinear junction capacitances, some significant deviations between simulated and measured results will emerge in the switching waveforms. In this paper, the nonlinear characteristics of drain–source capacitance in SiC MOSFET are studied in detail, and the simplified modeling methods for engineering applications are presented. On this basis, the SiC MOSFET model is improved and the simulation results with improved model correspond with the measured results much better than before, which verify the analysis and modeling. [ABSTRACT FROM AUTHOR]

The accurate calculation of switching voltage (${V}_{s}$) is necessary for the reliable and low-power operation of monolithic 3-D (M3D) CMOS-nanoelectromechanical (NEM) hybrid reconfigurable logic circuits because ${V}_{s}$ corresponds to the operating voltage (${V}_{\text {dd}}$) of NEM memory switches. In this paper, based on the Euler–Bernoulli equation, the physics-based analytical model is proposed to determine ${V}_{s}$. The accuracy of the proposed model is verified by both the finite-element analysis and experimental results. Our proposed model shows >3% error compared with experimental data. Also, the design guidelines of NEM memory switches are presented in terms of minimum ${V}_{s}$ (${V}_{s\_{}{m}}$) and device dimensions. [ABSTRACT FROM AUTHOR]

This paper presents a methodology to model GaN power HEMT switching transients. Thus, a compact model to predict devices’ pulse switching characteristics and current collapse reliability issue has been developed. Parasitic RC subcircuits and a standard double-pulse switching tester to model intrinsic parasitic effects and to analyze power dissipation of GaN power HEMT are proposed and presented. Switching transient including gate-lag and drain-lag is predicted for ideal (without trap) and nonideal (with trap) devices. The results are validated by and compared to 2-D finite-element technology computer-aided design simulations. The original aim of this exercise is to develop a fast (near-real-time) model which can predict dynamic behavior of single and multiple power GaN HEMTs used for the switching transients of GaN power devices at circuit level. [ABSTRACT FROM PUBLISHER]

This paper analyzes write errors in spin-torque switching due to thermal fluctuations in a system with perpendicular magnetic anisotropy. Prior analytical and numerical methods are summarized; a physics-based general 2-D Fokker–Planck equation (FPE) is solved numerically. Due to its computational efficiency and broad applicability to all switching regimes and system symmetries, the 2-D FPE has been used to study the relation between write error slope and material parameters as well as some emerging switching schemes. [ABSTRACT FROM PUBLISHER]

Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed, low power, infinite endurance, and easy integration with CMOS circuits. However, a relatively high current flowing through an MTJ is always required by most of the switching mechanisms, which results in a high electric field in the MTJ and a significant self-heating effect. This may lead to the dielectric breakdown of the ultrathin ( $\sim 1$ nm) oxide barrier in the MTJ and cause functional errors of hybrid CMOS/MTJ circuits. This paper analyzes the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier and proposes an SPICE-compact model of the MTJ. The simulation results show great consistency with the experimental measurements. This model can be used to execute a more realistic design according to the constraints obtained from simulation. The users can estimate the lifetime, the operation voltage margin, and the failure probability caused by TDDB in the MTJ-based circuits. [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

We present analysis and modeling of a new innovative nanoelectromechanical switch (NEMS) with virtually zero leakage current, 1–3-V operation voltage, 1–10-ns switching time, and small footprint. In addition to acting as a simple switch, the physical structure of NEMS enables positioning of multiple contacts to realize functional logic gates in a single device. The implementation of basic two (or more) input logic gates using a single device improves reliability and reduces charging delay time. The reduction in the number of devices also improves yield and power while simplifying implementation. To evaluate NEMS design, we present an accurate NEMS SPICE circuit simulation model which enables the measurement of NEMS timing and power requirement. Based on the model and the device fabrication data, we show that NEMS ISCAS-85 circuit shows significant improvement over CMOS technology counterpart (using 65- and 45-nm technology). [ABSTRACT FROM AUTHOR]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

This paper describes the application of electrical circuit simulations in intelligent power module development for hybrid vehicles, electric vehicles, and fuel cell vehicles. The limitations of the conventional design and simulation systems are discussed, and efforts for overcoming these limitations are described. The introduction of a physics-based insulated-gate-bipolar-transistor model with a surface-potential MOSFET core into the design flow is described. Finally, future expectations for necessary simulation technology development are given. [ABSTRACT FROM PUBLISHER]

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design. [ABSTRACT FROM AUTHOR]

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array. [ABSTRACT FROM AUTHOR]

The need for reliable models that take into account the nonlinear kinetics of dopants is nowadays of paramount importance, particularly with the physical dimensions of electron devices shrinking to the deep nanoscale range and the development of emerging nanoionic systems such as the memristor. In this paper, we present a novel nonlinear dopant drift model that resolves the boundary issues existing in previously reported models that can be easily adjusted to match the dynamics of distinct memristive elements. With the aid of this model, we examine switching mechanisms, current–voltage characteristics, and the collective ion transport in two terminal memristive devices, providing new insights on memristive behavior. [ABSTRACT FROM PUBLISHER]

The transient simulation of threshold switching in phase-change memory (PCM) devices is essential for the prediction and optimization of cell behavior depending on the circuit parameters and for the understanding of the ultimate limit of operation speed. This paper presents a simulation study of threshold switching in PCM devices aimed at investigating the role of delay and switching times in cell behavior. The analytical Poole–Frenkel model for conduction and the energy gain model for threshold switching are used to evaluate the transient effects. The current and field transients at the basis of the switching phenomenon are shown and discussed with the aid of the numerical model. The impact of cell parasitics, in particular the parallel capacitance, is finally addressed. [ABSTRACT FROM PUBLISHER]

We propose, demonstrate, and assess a nontunneling-based nMOS voltage-controlled negative differential resistance (V-NDR) concept for overcoming the intrinsic efficiency and reliability shortcomings of magnetic random access memory memories (MRAM). Using nMOS V-NDR circuits in series with MRAM tunnel junctions, we experimentally observe 40 times reduction in current during switching, enabling write termination and read margin amplification. Large scale Monte Carlo simulations also show 5X improvement in write energy savings and demonstrate the robustness of the scheme against device variability. [ABSTRACT FROM PUBLISHER]

Hybrid-phase-transition FETs (Hyper-FETs) are recently proposed steep switching devices that utilize the phase transition materials (PTM) to achieve a boost in the ratio of ON ( I{{\mathrm {ON}}}) and OFF currents ( I{{\mathrm {OFF}}}) . Prototypical demonstrations of the Hyper-FET have shown performance improvement in comparison with conventional transistors, which motivates the evaluation of its device-circuit design space. In part I, we analyze the device aspects establishing the effects of the resistivity and phase transition thresholds of the PTM on the characteristics of Hyper-FETs. Our analysis shows that the ratio of insulating and metallic state resistivity ( \rho \mathrm {INS} and \rho \mathrm {MET,} respectively) of the PTM needs to be higher than the I{{\mathrm {ON}}} /I{{\mathrm {OFF}}} of its host transistor to achieve performance improvement in Hyper-FET. For a host transistor with $I_{{{\mathrm {OFF}}}} = 0.051\mu \text{A}/\mu \text{m} and I{{\mathrm {ON}}} = 191.5\mu \text{A}/\mu \text{m} , \rho \mathrm {MET}< \sim 2 \times 10^{\mathrm { {-3}}} \Omega .cm and \sim 7.5~\Omega .cm < \rho _{\mathrm {INS}}<20\,000 \Omega .cm is required to achieve proper device functionality with a boost in {I}_{{{\mathrm {ON}}}}/{I}_{{{\mathrm {OFF}}}} . Additionally, we establish the ranges of phase transition thresholds that yield proper functionality of the Hyper-FETs considering different I{{\mathrm {OFF}}} targets. The methodology of choosing appropriate PTM geometry to achieve the target device characteristics is also described. We show that with proper design, Hyper-FETs achieve 94% larger I{{\mathrm {ON}}} at iso- I{{\mathrm {OFF}}} compared with a FinFET. We examine the circuit design aspects of Hyper-FET in part II. [ABSTRACT FROM AUTHOR]

The dynamic characteristics of a spin transfer torque magnetoresistive random access memory crossbar array during write operations were investigated. A spin transfer torque magnetic tunnel junction was combined with a two-terminal selector device instead of a three-terminal CMOS transistor in the crossbar array architecture. The characteristics of the crossbar array architecture were investigated under different bias schemes and transient simulations of write operations were performed under various operating conditions. The variance of the switching time and problematic behaviors was investigated. The floating bias scheme was compared with the 1/2 bias scheme, and simulation results revealed that write errors may be induced in the floating bias scheme by abnormal glitches occurring when the parasitic capacitance becomes large. [ABSTRACT FROM PUBLISHER]

We present a physical circuit model of ferroelectric (FE) polarization switching for the analysis and design of hybrid FE-CMOS circuits. Stochastic geometry is applied to domain nucleation, growth, and coalescence under arbitrary voltage and current input signals. The circuit model is first constructed for ideal FE capacitors and then extended to the realistic effects of lateral scaling, anisotropic growth, and disorder in polycrystalline films. Reliability degradation by imprint and fatigue is also incorporated. The interaction of model parameters and circuit design for three different nonvolatile latch topologies is presented in Part II. [ABSTRACT FROM AUTHOR]

We present a detailed analysis of hybrid ferroelectric (FE)-CMOS nonvolatile latches, based on simulations with the unified physical circuit model from Part-I and experimental verification with circuit measurements. Hybrid FE-CMOS latches are categorized into three classes by the circuit topology of the readout operation. The effect of the physical model parameters is studied in all regions of operation by a variational analysis. Design intuition for the signal timing and sensing margin is provided and the strategies for the design optimization are discussed. Signal degradation due to imprint and fatigue in each latch topology is also compared. [ABSTRACT FROM AUTHOR]

A circuit-level model of a magnetic tunnel junction (MTJ) that accurately depicts the spin-transfer torque switching behavior of an MTJ along with its voltage/temperature dependency is presented. The unified switching model that was suggested in our previous work is suitable for the circuit-level model because the model seamlessly covers the entire current pulsewidth region. Based on this switching behavior model, a method of dynamic current monitoring is proposed for an advanced circuit-level model. The voltage/temperature characteristics of an MTJ are also integrated for a more accurate circuit-level simulation. The proposed model corresponds well with the experimental data for switching characteristics at different temperatures. The design margin in the read/write circuits with an MTJ is analyzed to demonstrate the effectiveness of the model. [ABSTRACT FROM AUTHOR]

The switching waveforms and losses of a GaN gate injection transistor (GIT) bidirectional switch, a type of four-terminal device, were analyzed for the first time using an equivalent circuit model. By applying a three-terminal model to the equivalent circuit model of the GIT bidirectional switch and by using the waveforms of the chopper circuit, the parameters were derived with high accuracy. Furthermore, gate resistance dependence was added to the input capacitance component connected to the gate terminal in order to contain the influence of the gate structure of the GIT. It was confirmed that the calculated switching waveforms and losses agree well with those of the experimental values with over 90% accuracy, even in cases where circuit conditions for circuit voltage, load current, and gate resistance were varied. [ABSTRACT FROM PUBLISHER]

A nonlinear III–V field-effect transistor model is proposed for designing microwave antenna switches and related circuits. off-state gate and drain capacitance values of a pseudomorphic high-electron-mobility transistor (HEMT) derived from pulsed S-parameters with a deep off-state quiescent gate voltage are found to be much less voltage dependent than capacitance values measured by a nonpulsed bias owing to trap-induced dispersion effects. Our device model based on pulsed-bias CV characteristics accurately simulates switch nonlinearity. Both gate and drain capacitance values are assumed to be nonlinear, and a charge expression is developed for model implementation. For both capacitance values, a nonpulsed-bias CV curve is also utilized to maintain accurate capacitance at the quiescent voltage and, thus, accurate simulation of off-switch isolation. Additional terms are introduced to an existing drain current model to improve accuracy at high Vgs/\low\ Vds and subthreshold regions. Furthermore, the model is extended to multiple-gate devices. Harmonics generated from both off- and on -state switches, insertion loss, and isolation are accurately predicted for both single- and multiple-gate HEMTs. [ABSTRACT FROM AUTHOR]

The nucleation-limited switching (NLS) model has been shown in the literature to explain successfully the dynamics of polarization switching of polycrystalline ferroelectric films (FE) in various experiments. However, because of its mathematical complexity, the NLS model has yet to be implemented correctly and efficiently in the simulation of actual, experimental circuits with complex driving waveforms. Here, we reformulate NLS as a generalized polarization rate equation that captures correctly the incubation time of nucleation and the intra- and inter-grain switching statistics of kinetics without any restrictions on waveform and switching time scales. This formulation forms the basis for efficient numerical finite-difference computation, which is verified in realistic circuit simulations of a number of experiments. [ABSTRACT FROM AUTHOR]

A phase-change memory (PCM) model for robust and efficient simulations of circuits including neuromorphic ones is reported in this work. The features of a hysteretic dynamic resistance in the voltage domain, and the incubation in the crystallization, are covered in the model. The Landau–Khalatnikov (LK)-type equation for ferroelectric is used to develop the PCM hysteresis module. A voltage-controlled relaxation oscillation is successfully simulated for the Ge2Sb2Te5 (GST) PCM. A technique of direct evaluation (DE) is then developed to reformulate the PCM model without any internal node. A significant enhancement of simulation efficiency is achieved compared with the traditional approach without sacrificing the accuracy. The functional correctness of the PCM device model and the acceleration effect in circuit simulations are verified. [ABSTRACT FROM AUTHOR]

In this article, for the first time, we present the improvement in efficiency in a low-voltage dc–dc boost converter for the energy-harvesting applications using the experimentally demonstrated sub-50-mV nano electro-mechanical switch (NEMS). As per the measurement results, the sub-50-mV NEMS having a small air gap of only 100 nm exhibits very low hysteresis (< 20 mV), low turn-on delay (15 ns), and low sub-threshold swing of 2 mV/decade. In addition to this, the fabricated NEMS is a propitious candidate toward ideal power switch with almost zero leakage current and a maximum ON-state conductance value of 0.1 A/(V ⋅ μm). This study explores a discontinuous-conduction mode (DCM) boost converter with specifications suitable for energy-harvesting applications using the NEMS-based design. The results are compared with the corresponding design using the MOSFET switches in 0.18-μm CMOS technology. This work illustrates that the NEMS-based DCM boost converter design has an improvement in the efficiency of around 30% at a switching frequency of 10 kHz over CMOS for the same ON-state resistance. This is because the proposed fabricated NEMS has extreme low pull-in voltage (50 mV) and low parasitic capacitances (~3.3 fF/μm). [ABSTRACT FROM AUTHOR]

Spin-transfer torque random-access memory (STT-RAM) is gaining momentum as a promising technology for high-density and embedded nonvolatile memory. Owing to random thermal fluctuations, switching transitions generally display statistical variations from cycle to cycle. Stochastic variations are critical to the hindering of memory and computing applications of STT-RAM. To enable the design of STT-RAM circuits for memory and computing, there is a need for accurate compact models capable of predicting the stochastic behavior. Here, we present a detailed model accounting for the anomalous thermal regime of switching deviating from the Néel–Brown thermal model below 200 ns. Anomalous switching is explained by the nonlinear lowering of the energy barrier associated with the perpendicular magnetic anisotropy (PMA). The model is extensively verified against the write-error-rate (WER) data as a function of applied voltage and pulsewidth and experimental switching time-delay distributions. [ABSTRACT FROM AUTHOR]

Due to its infinite OFF resistance, Nano-Electro-Mechanical Switches (NEMS) have been recently proposed to reduce leakage current during the standby mode in large-scale Digital ICs in nano regime area. However, detailed analysis of the conditions at which the NEMS devices will have impact is missing. In this brief, the technique of power gating is analyzed with a NEMS switch using detailed circuit level simulations to obtain the conditions under which one can obtain net energy savings as compared with FinFET-based power gating. Finally, applicability in the energy reduction on a futuristic system-on-chip for mobile platform made using 14 nm gate length FinFET device is evaluated. [ABSTRACT FROM AUTHOR]

A physics-based compact model of metal-oxide-based resistive-switching random access memory (RRAM) cell under dc and ac operation modes is presented. In this model, the conductive filament evolution corresponding to the resistive switching process is modeled by considering the transport behaviors of oxygen vacancies and oxygen ions together with the temperature effect. Both the metallic-like and electron hopping conduction transports are considered to model the conduction of RRAM. The model can reproduce both the typical I-V characteristics of RRAM in high-/low-resistance state (LRS) and the nonlinear characteristics in LRS. Moreover, to accurately model ac operation mode, the effects of parasitic capacitance and resistance are included in our model. The developed compact model is verified and calibrated by measured data in different HfOx-based RRAM devices under dc and ac operation modes. The excellent agreement between the model predictions and experimental results shows a promising prospect of the future implementation of this compact model in large-scale circuit simulation to optimize the design of RRAM. [ABSTRACT FROM PUBLISHER]

A simulation framework that can comprehend the impact of material changes from the device level to the system level design can be of great value, especially to evaluate the impact of emerging devices on various applications. To that effect, we developed a SPICE-based hybrid magnetic tunnel junction (MTJ)/CMOS simulator, which can be used to explore new opportunities in large scale system design. In the proposed simulation framework, MTJ modeling is based on Landau–Lifshitz–Gilbert (LLG) equation incorporating both spin-torque and external magnetic field(s). LLG, along with heat diffusion equation, thermal variations, and electron transport, is implemented using SPICE-inbuilt voltage-dependent current sources and capacitors. The proposed simulation framework is flexible because the physical device parameters such as MgO thickness, ferromagnet material anisotropy (Ku), and device dimensions are user-defined parameters. Furthermore, we benchmarked this model with experiments in terms of switching current density (JC), switching time (TSWITCH), and tunneling magnetoresistance. Finally, we used the simulation framework to study different MTJ structures, such as in-plane magnet anisotropy and perpendicular magnet anisotropy, the impact of parametric process variations and temperature on the yield of spin transfer torque magnetoresistive random access memories, magnetic flip-flops, and spin-torque oscillators. [ABSTRACT FROM AUTHOR]

An accurate power circuit loss estimation method has been developed for designing power converters with hybrid pairs of silicon (Si) insulated-gate bipolar transistor (Si-IGBT) and silicon carbide (SiC) Schottky barrier diode/SiC p-i-n diode. An analytical model of the switching losses of the hybrid pairs is proposed to achieve high accuracy and short calculation time. The nonlinearity of the device parameters and the stray inductance in the circuit are considered in the model. For the accurate power loss calculation, an empirical parameter extraction method is introduced for extracting device parameters. The calculated circuit power losses are compared with measurement results, and good agreements are confirmed. By using the proposed method, the power loss of a power converter utilizing 4.5-kV Si-IGBT/SiC-p-i-n-diode hybrid pairs is estimated to investigate the upper limitation of the switching frequency. [ABSTRACT FROM PUBLISHER]

We propose a behavioral circuit model to precisely predict optical responses of an active-matrix liquid crystal (LC) display (LCD) using a patterned vertical alignment (PVA) mode. To get more accurate simulation results, we propose two LC groups with different time constants for a pixel after observing the LCD pixels by using a high-speed camera. In addition, we include a time-delay concept into our behavioral model for brightening or rising transitions. We describe the behavior of the PVA-LCD by using the analog hardware description language Verilog-A. We simulate the PVA-LCD panel by importing the behavioral circuit model in the circuit simulator SmartSPICE. The simulation results of the transient optical responses show excellent matches with the measurement ones. [ABSTRACT FROM PUBLISHER]

In this brief, we present the experimental and simulated characteristics of a new power semiconductor device called MOS-gated thyristor (MOS-GTO) for high-power applications. The results are presented for a 1.2-kV device and subsequently scaled up to 4.5-kV blocking voltage. The excellent ON-state voltage and switching characteristics make MOS-GTO a very promising device for high-voltage power applications. [ABSTRACT FROM AUTHOR]