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Voltage-controlled three-phase three-leg inverters are widely applied in various occasions. The inverters are generally switched to the current-controlled mode to limit the fault currents when short-circuit faults happen. Under symmetrical fault, the inverter can be controlled as a symmetrical, three-phase current source. However, the voltage limiting will happen under asymmetrical fault. As a result, the fault phase currents will be distorted and cannot be completely controlled. Considering that the voltage limiting is mainly caused by large load impedance of healthy phase under asymmetrical fault, the voltage limiting is avoided by paralleling the virtual impedance with the output filter capacitor in this paper. As a result, the current limiting loop is not broken and the fault phase currents can be effectively controlled. The implementation of virtual impedance in control system and the influence of virtual impedance on the stability of system are also analyzed in detail in this paper. The theoretical results are validated by experiments. [ABSTRACT FROM AUTHOR]

This paper presents a new photovoltaic (PV) power systems laboratory module that was developed to experimentally reinforce students' understanding of design principles, operation, and control of photovoltaic power conversion systems. The laboratory module is project-based and is designed to support a renewable energy course. By using MATLAB real-time software tools in combination with digital signal processor (DSP) hardware tools, the module enables students to: 1) design and build dc–dc and dc–ac power converters; 2) design and implement control algorithms for maximum power point tracking (MPPT) and voltage and current regulation; and 3) design and fabricate a printed circuit board for voltage and current sensing, isolation, and gate driving. In these hands-on experiments, by designing and building their hardware and software integrated systems themselves, students learn by doing and experience the engineering transformative process of building a product out of an idea. This paper is motivated by the dearth of literature on the application of project-based learning methodology to PV systems. The module description, the pedagogical and evaluation methodologies adopted, and reflections on the implementations are discussed. [ABSTRACT FROM PUBLISHER]

DC shipboard power systems have been considered as a promising solution for stricter environmental regulations on ships due to their main benefits in fuel savings with variable speed engines and easy integration of energy storage systems. In order to employ the dc solution in the shipboard power systems, the dc power systems have to be protected from a system fault with protection selectivity to minimize impacts of the fault or to avoid other undesirable situations in the system. For low-voltage dc shipboard power systems, a three-level protection has been proposed: 1) fast action (first)—bus separation by solid-state dc bus-tie switch; 2) medium action (second)—feeder protection by high-speed fuse; and 3) slow action (third)—generator–rectifier fault controls. This paper proposes a new method by means of additional bus capacitance added in main dc buses to help reliable operation of the three-level protection. The principle of the proposed method is introduced and the sizing of the additional bus capacitance is addressed in this paper. With the modeling of the dc shipboard power systems, the analyses of voltage drops for the bus separation failure and fault clearing time for the feeder protection are carried out to verify the proposed method. The results show that the proposed method not only mitigates the voltage drop for the bus separation failure, but also achieves the selectivity and the sensitivity for the feeder protection. [ABSTRACT FROM AUTHOR]

First harmonic analysis (FHA) is arguably the most widely used analytical technique for wireless power transfer (WPT) circuits due to its simplicity. Although FHA can provide closed-form solutions, the existence of rectifier diode forward voltage drop and higher order harmonics, especially the second and third harmonics at variable duty cycle operation, can significantly deteriorate its accuracy. This paper presents an accurate and efficient method called enhanced multiple harmonic analysis (eMHA) for the optimal design and optimal control of WPT systems. The eMHA method considers the nature of nonlinear rectification networks under nonsinusoidal current and reexamines the concept of the equivalent load. As a result, the rectified WPT system is transformed into a series of linear systems with complex load impedances. The steady-state electric quantities can be then explicitly calculated. This enables eMHA to seamlessly work with numerical optimization algorithms to facilitate the automated design and optimization of WPT systems. An example of optimal design and optimal control of a 10 W WPT system is demonstrated. The results obtained by eMHA and FHA are also compared. A prototype of the designed circuit was constructed. The accuracy and effectiveness of eMHA are verified by experimental measurements. This paper is accompanied by a MATLAB-based analytical tool with a graphical user interface demonstrating the effects of circuit variables on electrical quantities and waveforms. [ABSTRACT FROM AUTHOR]

This paper presents a neutral-point deviation and ripple compensating control method applied to a three-level neutral-point-clamped (NPC) converter. The neutral-point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral-point of the dc link. This paper also proposes a control scheme compensating for the neutral-point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the switching functions and ac input currents are employed to accurately explain the behavior of three-level NPC converter. Simulation and experimental results are presented to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a simplified implementation technique for direct torque control (DTC) of asymmetric six-phase induction motor drive. Current harmonics of fifth and seventh order are observed in the phase currents if conventional DTC scheme is extended for the asymmetric six-phase machine. These harmonic components are not responsible for torque production, thus causing losses in the motor winding. Synthetic vectors are generally used for reduction of current harmonics. Average voltage in $xy$ subspace is maintained to zero by synthetic vectors leading to reduction of currents in $xy$ subspace. A simplified method of implementation of synthetic vectors is proposed in this paper, which eliminates the need for designing of switching sequence and requirement of field-programmable gate array. Also, the number of synthetic vectors that can be possibly produced is increased compared with the ones developed by techniques available in the literature. The experimentation is carried out on a laboratory-developed prototype and the experimental results are presented in this paper to verify the proposed scheme. [ABSTRACT FROM PUBLISHER]

Studies have been taken into the breakdown voltage jitter of corona-stabilized switch at high repetition rate up to several kHz. It is thought that the gas recovery affect the jitter of breakdown voltage directly at high repetition rate, because the gas switch will breakdown at a low voltage if the gas cannot fully recover. The breakdown voltage jitter is called voltage jitter in the following paper. However, based on the experimental results, the voltage jitter still exists at low repetition rate, even at single-shot mode. This is not explained by the previous studies. In this paper, voltage jitter below 100 Hz of a corona-stabilized switch is investigated experimentally. A corona-stabilized switch is introduced, using a cylindrical electrode as the cathode and a plane electrode as the anode. The gas used between the electrodes is SF6. A negative pulse with a maximum width of 30~\mu \texts is used to charge this switch. The tested factors include gas pressure, gap space, repetition rate, and switch geometry. Experimental results show that voltage jitter is mainly affected by the gas pressure and switch geometry. It is seen that voltage jitter decreases as gas pressure increases and a suitable cathode geometry presents a low voltage jitter. Critical volume is a region close to the highly stressed electrode, where the presence of an electron will lead to an electron avalanche which attains a critical size and hence leads to a stabilizing corona. Critical volume is introduced to explain the experimental results. It is found that less voltage jitter can be achieved with a smaller and more concentrated critical volume, as well as efficient corona stabilization. The results indicate that voltage jitter may be reduced by optimize the critical volume at low repetition rate. [ABSTRACT FROM PUBLISHER]

This paper focuses on the issue of network connectedness (NC) in security-constrained optimal transmission switching problems, which is complicated by branch contingencies and corrective line switching. Two criteria are firstly proposed with the principle of preserving NC as much as possible within reasonable limits. By extending the electrical flow based NC constraints, a proposition is derived to associate different cases of NC with the optimum of a linear program, yielding the mathematical formulation of the NC criteria. By Karush-Kuhn-Tucker conditions, this formulation is further transformed into a tractable version which can be incorporated with existing SCOTS models without affecting the applicability of original solution approaches. Finally, case studies on various networks and SCOTS models demonstrate the efficacy of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper analyzes the effects of shunt capacitors installed on the low voltage sides of 10/0.4 kV distribution transformers on the operation of these transformers. Using the results of an extensive measurement campaign, this paper compares: real and reactive power losses, secondary-side current, and primary-side apparent power before and after the installation of transformer capacitors. The following four cases of reactive power compensation are considered and discussed: adequate, conditionally adequate, and total compensation, as well as overcompensation. The presented analysis helps to identify transformer substations where the initial compensation should be changed or adjusted, in order to improve transformers’ operational performance. Voltage dependencies of real and reactive power demands of the transformer-supplied loads are taken into account, based on the previously identified load characteristics in the considered networks as well as voltage dependence of reactive power of shunt capacitors. The result with and without including these voltage dependencies in the analysis is compared and discussed. [ABSTRACT FROM AUTHOR]

The planned China fusion engineering test reactor (CFETR) needs one or more negative-ion-based neutral beam injectors (N-NBIs) with a beam energy of 500 or even 1000 keV. In order to prepare for CFETR, a prototype of CFETR N-NBI is being designed. The prototype needs an acceleration grid power supply (AGPS) rated at 200 kV/25 A with a maximum pulselength reaches to 3600 s. The AGPS adopted a single-stage inverter-type high-voltage power supply (HVPS). The output voltage ripple is an important specification of the AGPS, which can affect the efficiency and stability of N-NBI system by influencing the beam divergence. However, the conventional methods cannot be used to limit the output voltage ripple of the inverter-type HVPS used as AGPS of CFETR N-NBI prototype. This paper simplified the AGPS to an insulated three-phase three-level (TPTL) dc–dc converter connected with a dual dc link. The working process of the TPTL dc–dc converter with duty-cycle modulation has been analyzed, and two main continuous conduction modes are described. The influence of key parameters such as duty cycle of inverter, leakage inductance of transformer, and output current on output voltage ripple is analyzed. Based on the analysis results, a so-called combined control strategy was proposed to keep the output voltage ripple at a level. The proposed strategy is suitable for the cases where the object output voltage is below 175 kV. Some simulations were carried out by using MATLAB/Simulink. The results showed that the analysis in this paper is reliable and the proposed control strategy has a good performance. [ABSTRACT FROM AUTHOR]

This paper introduces an averaging control strategy of the phase-unit losses of modular multilevel converters (MMCs). The quantitative analysis of the MMC phase-unit loss distribution under unbalanced ac conditions is carried out by investigating the individual component of the MMC arm currents. It shows that the unbalanced arm currents will result in unbalanced phase-unit losses. To address this issue, this paper proposes a predictive closed-loop-control-based zero-sequence voltage injection method that results in much averaged loss distribution under unbalanced ac conditions. The essence of the new method is that it adjusts the three-phase sinusoidal references so that the unbalanced arm currents are fully utilized to average phase-unit losses. This paper shows the effectiveness of the new approach by electromagnetic transient simulations on PSCAD/EMTDC. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency single-phase T-type boundary conduction mode (BCM) microinverter. The conventional full-bridge BCM microinverter has achieved zero voltage switching (ZVS) and thereby improved the efficiency, but it suffers from high switching losses under light load conditions. The proposed T-type BCM microinverter reserves ZVS and uses a multilevel technique to further decrease the switching losses. The BCM operation with multilevel technique will have too low switching frequency when the grid voltage approaches half of the dc link voltage. To solve this problem, this paper adopts a third operation mode for the T-type switching leg to maintain the switching frequency above a minimum value. The corresponding mode transitions are also detailed to ensure a smooth operation. Because of the turn-offdelay of the freewheeling transistor, the actual lower current boundary deviates from the programmed one, which will distort output current. To address this issue, this paper also proposes a boundary compensation method. A prototype has been built for performance verification, which can test both full-bridge and T-type topology. Compared with the full-bridge BCM microinverter, the proposed T-type BCM microinverter has a higher efficiency over the whole load range. [ABSTRACT FROM AUTHOR]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

On transmission lines where switching surges are not mitigated with closing resistors and/or surge arresters, high-speed reclosing on a line with trapped charge will produce high overvoltages that have been measured above 3 p.u. Careful simulations of these switching events using available electromagnetic transient (EMT) programs consistently produce significantly higher voltages than the measurements. This indicates a phenomenon present on the line that acts to reduce the switching surge magnitudes but is not typically modeled. This paper aims to identify the required simulation practices in reproducing the field measured overvoltages in EMT simulations and investigates the sensitivity of results to modeling approaches and electrical parameters. Field measurements from a switching surge test of a 230-kV line without surge mitigation have been used for model comparisons. Variations in frequency-dependent line modeling, ground resistivity, skin effect, shunt conductance, parallel lines, and source-side detail have been tested in an unsuccessful attempt to decrease the difference between the field measurements and the higher simulation overvoltages. It is demonstrated that even though the pattern of the transient voltage waveforms can be reproduced very well using frequency-dependent line models, the magnitude of the maximum overvoltage is significantly overestimated unless the effect of corona is considered. Two types of corona models are tested, and both demonstrate that corona is the primary factor that allows the simulations to correctly reproduce high peak overvoltage measurements. [ABSTRACT FROM AUTHOR]

This paper presents low-power circuit techniques for comparators and controllers to reduce increasing power loss of an active diode with offset/delay calibration in a 13.56-MHz CMOS active rectifier. Unlike a conventional switched-offset comparator, the proposed voltage-mode switched-offset comparator reuses its bias current to generate continuously adjustable offset voltage, thereby reducing power loss. Offset calibration for accurate switching is adopted to improve power conversion efficiency (PCE) and voltage conversion ratio (VCR). The proposed switch controller for offset calibration uses dynamic logic circuits and reduces power overhead that NOR-based set-reset latches and edge detectors of conventional switch controllers cause. Under 200- ${\Omega }$ loading and 5-V output, the proposed comparator and controller reduce power consumption by up to 73% and 24% in simulations compared with the conventional comparator and controller, respectively. This paper is implemented with 5-V devices of a 0.35- ${\mu }\mathrm {m}$ CMOS process to support high voltage. A peak PCE of 89.0%, a peak VCR of 90.1%, and a maximum output power of 126.7 mW are measured for 200- ${\Omega }$ loading. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

When developing silicon carbide (SiC) devices, the reliability of the internal body diode is an important issue. Stacking faults (SFs) are expanded from basal plane defects by using a body diode. Although it is well known that ON-voltage degradation occurs due to SFs, their effects on dynamic reliability have not been studied well. Furthermore, including the effects of SFs, there are not many reports about the dynamic reliability of SiC-MOSFETs. In this paper, a double-pulse switching test using 3.3-kV SiC-MOSFETs was carried out to clarify the failure mechanism of the switching operation of SiC-MOSFETs and effects of SFs on the safe operation area (SOA). Before the switching test, current stress was applied to the body diode of the devices under test (DUTs) to expand the SFs. The circuit configuration was half-bridge type, and a double-pulse gate signal was applied to the lower arm DUT. The switching voltage was 1.8 kV, and the switching current increased at about 8-A steps to failure. As a result, reverse recovery SOA (RRSOA) reliability decreased depending on the amount of SFs in the SiC-MOSFET. Because RRSOA failure was caused by avalanche due to the hole concentration during reverse recovery and the SFs raised local current density, reverse bias SOA (RBSOA) hardly decreased even if SFs containing SiC-MOSFETs were used. This is because RBSOA failure was caused by degradation of the gate isolation layer due to overheating and the temperature coefficient of the SFs electric resistance indicated negative. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of switching performances between the in-situ oxide, gallium nitride (GaN) interlayer FET (OG-FET) and the conventional GaN metal–oxide–semiconductor FET (MOSFET), and explores the influence of the channel electron mobility on the device switching performance. GaN OG-FET is a novel structure with a pristine GaN layer grown between the gate oxide and the p-GaN enhancing the channel mobility up to 185 cm2/ $\text {V}\cdot \text {s}$ , which is over $3{\times}$ larger than that of the typical reported value (50 cm2/ $\text {V}\cdot \text {s}$) in GaN MOSFET. Owing to the high channel electron mobility, the GaN OG-FET showed a switching loss 30% lower than that of the conventional GaN trench MOSFET. Our results indicate that GaN OG-FET has the potential to attain greater efficiency, particularly at higher frequencies, showing a possible patch toward megahertz range conversions. [ABSTRACT FROM AUTHOR]

This paper investigates the performance of switch-mode power supplies used in desktop PCs (PC-SMPS’) across the entire range of operating powers. Experimental results show that at low to medium operating powers, the input ac current might lose its periodicity with supply voltage frequency, when PCS-MPS’ can be an unexpected source of interharmonics and dc component. In such cases, there is a significant increase of PC-SMPS’ current waveform distortion and a substantial decrease of efficiency and operational power factors, which requires application of appropriate measurement and calculation procedures during the analysis. To correctly assess these power-dependent changes in performance and power quality indicators, this paper introduces a novel testing and evaluation methodology, based on the known or assumed PC-SMPS operating cycle. [ABSTRACT FROM AUTHOR]

This paper discusses dynamic behavior of a dual-active-bridge (DAB) dc–dc converter. Conventional phase-shift control methods for the DAB converter may cause dc offsets in both inductor current and transformer magnetizing current in transient states. The dc offset in the inductor current would introduce an excessive peak current through the switching devices. The dc offset in the magnetizing current may induce magnetic-flux saturation. Conventional methods simultaneously turn on and off the diagonal switches in each H-bridge converter and produce a square-wave voltage with a 50% duty ratio. In contrast, the proposed method in this paper independently controls each switch to modify the duty ratio in transient states. This paper clearly derives the requirements of each switch to eliminate the dc offsets in both currents with a settling time shorter than half the switching period. Experimental results using a 5-kW 20-kHz system verify the validity of the proposed control method, which is effective not only in a single step change, but also in a continuous change in the phase-shift reference. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate the linear conductance-change characteristics of a conductive-bridging RAM (CBRAM) to be employed as an artificial synapse device in neuromorphic systems. The CBRAM with a bilayer electrolyte structure (${\mathrm {Cu/Cu}}_{{2}-{x}}\text{S}$ / $\mathrm {WO}_{{3}-{x}}$ /W) exhibits analog switching behavior during the depression process due to the well-controlled dissolution of the conductive filament. To analyze the origin of this motion, we investigate the effective voltage applied to $\mathrm {Cu}_{{2}-{x}}\text{S}$ and $\mathrm {WO}_{{3}-{x}}$. Our findings reveal that $\mathrm {Cu}_{{2}-{x}}\text{S}$ , acting as a voltage divider, helps in suppressing the large voltage drop in $\mathrm {WO}_{{3}-{x}}$ , where the formation/dissolution of filament occurs. Furthermore, due to the diode-like characteristics of $\mathrm {Cu}_{{2}-{x}}\text{S}$ and the division of voltage drop between $\mathrm {WO}_{{3}-{x}}$ and $\mathrm {Cu}_{{2}-{x}}\text{S}$ , an optimum programming energy is applied to $\mathrm {WO}_{{3}-{x}}$ during the depression process. This leads to linear conductance-change characteristics under identical pulses. However, abrupt conductance-change characteristics are observed during the potentiation process. Thus, we use only the device characteristics of the depression part for the neuromorphic system. An excellent classification accuracy is achieved due to the linear conductance-change characteristics and optimized pulse conditions. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

This paper proposes a 32.7 kHz self-biased wake-up timer using temperature-insensitive resistive current. A dual-loop structure with supply-regulation loop and frequency-locked loop determines the regulated voltages at both ends of a temperature-compensated resistor and cancels out the amplifier offset voltages, thus generating temperature-insensitive resistive current for the switched capacitor. Moreover, a self-biasing scheme in low-power design reduces the power variation across the temperature range and eliminates the necessity of a sub- $\mu \text{A}$ reference current generator. The proposed timer with its start-up circuit generates <12 ms lock time, which is 20 times less than what obtained without a start-up circuit, and exhibits a long-term frequency stability of 10 ppm and a temperature coefficient of 13.2 ppm/°C with an energy efficiency of 1.08 nW/kHz. [ABSTRACT FROM AUTHOR]

In this paper, the conventional I- and T-type three-level neutral-point-clamped (3L-NPC) inverter for low-voltage renewable energy systems is first investigated. Literature research shows that the T-type inverter improves I-type's insulated-gate bipolar transistor (IGBT) $+$ IGBT current paths. However, the IGBT $+$ diode paths are the same. The calculation in this paper further reveals that the IGBT $+$ diode current paths dominate the conduction losses and even the whole semiconductor losses. Based on the aforementioned recognitions, a novel T-type inverter is presented as an alternative to be applied in the low-voltage renewable energy systems. In the proposed 3L-NPC, four CoolMosfets replace the IGBT $+$ diode middle bidirectional switch. In the proposed topology, there is no diode involved in the current path supposing the unity power factor. In this way, the conduction loss is expected to be reduced compared with that from the conventional T-type 3L-NPC, particularly in the low and medium power ranges. [ABSTRACT FROM PUBLISHER]

This paper demonstrates for the first time the use of microplasma to perform AND, OR, and XOR logic operations. The logic circuits are implemented similar to diode-resistor logic. Output voltages are in the range of \(5-40\) V and can be modified by varying the load resistor. The active area of the microplasma device is just \(50~\mu \) m \(\times 5~\mu \) m. The small interelectrode gap kept breakdown voltage to \(\sim 250\) V when operated in He gas at atmospheric pressure. The use of plasma as a source of free carriers is also demonstrated, with free carriers available up to 500- \(\mu \) m away from plasma. [ABSTRACT FROM PUBLISHER]

This paper presents a 16-core voltage-stacked system with adaptive frequency clocking (AFClk) and a fully integrated voltage regulator that demonstrates efficient on-chip power delivery for multicore systems. Voltage stacking alleviates power delivery inefficiencies due to off-chip parasitics but adds complexity to combat internal voltage noise. To address the corresponding issue of internal voltage noise, the system utilizes an AFClk scheme with an efficient switched-capacitor dc–dc converter to mitigate noise on the stack layers and to improve system performance and efficiency. Experimental results demonstrate robust voltage noise mitigation as well as the potential of voltage stacking as a highly efficient power delivery scheme. This paper also illustrates that augmenting the hardware techniques with intelligent workload allocation that exploits the inherent properties of voltage stacking can preemptively reduce the interlayer activity mismatch and improve system efficiency. [ABSTRACT FROM PUBLISHER]

Bipolar junction transistors (BJTs) have been widely studied and used in nanosecond high-voltage pulse generators due to the advantages of fast switching speed and high repetitive frequency. Usually the Marx-type circuit is used to raise the peak value of output pulses. In this paper, a traditional BJT-Marx circuit using charging resistors is analyzed theoretically and experimentally. Based on the results, the structure of a circuit is changed to decrease the isolation voltage across the resistors, and diodes are used to replace charging resistors to block capacitors discharging to resistors. Experimental results showed that the three Marx generators proposed in this paper output pulses with higher voltage amplitude, and the last improved circuit outputs pulses with faster fall times at a higher efficiency. [ABSTRACT FROM AUTHOR]

The increasing adoption of power electronic devices may lead to large disturbance and destabilization of future power systems. However, stability criteria are still an unsolved puzzle, since traditional small-signal stability analysis is not applicable to power electronics-enabled power systems when a large disturbance occurs, such as a fault, a pulse power load, or load switching. To address this issue, this paper presents for the first time the rigorous derivation of the sufficient criteria for large-signal stability in DC microgrids with distributed-controlled DC-DC power converters. A novel type of closed-loop converter controllers is designed and considered. Moreover, this paper is the first to prove that the well-known and frequently cited Brayton-Moser’s mixed potential theory (published in 1964) is incomplete. Case studies are carried out to illustrate the defects of Brayton-Moser’s mixed potential theory and verify the effectiveness of the proposed novel stability criteria. [ABSTRACT FROM AUTHOR]

This paper proposes a novel polygonal voltage space vector structure (SVS) having 30 sides, for a star-connected induction motor drive. The SVS eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. Topology consists of a dc-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is canceled by the secondary inverter which acts as a switched capacitive filter. Detailed description of the SVS generation and timing calculations are provided in this paper. Effectiveness of the proposed scheme is validated using experimental results, inverter loss calculations, and harmonic analysis. [ABSTRACT FROM AUTHOR]

This paper proposes a fifth-order resonant immittance network based dual-active-bridge (DAB) converter and an optimal modulation method that will ensure high-efficiency operation of the converter under wide-range variations in voltage ratio and output power level. The proposed modulation method is based on the concept of total power loss minimization, where a loss model is developed and an optimization algorithm is formulated to compute the optimal set of internal and external phase shift parameters that will lead to the maximum efficiency for a given set of operating parameters including voltage ratio and output power level. It is found that to maintain high-efficiency operation under wide-range variations in voltage ratio and output power level, the DAB converter is required to switch between different operation modes and neither soft-switching operation nor unity-power-factor operation is able to achieve wide-range high efficiency performance when used alone. The importance of $reconfigurability$ of operation mode for achieving wide-range high efficiency performance is clearly illustrated in this paper. [ABSTRACT FROM AUTHOR]

This paper characterizes the sampling effect in digital sinusoidal pulse width modulation (SPWM) of voltage source inverter (VSI). The time-domain analysis presented in this paper establishes the relation between the fundamental frequency, carrier frequency, and the sampling frequency at different modulation indices of the SPWM. The analysis investigates the effect of sampling frequency of the digital controller on the output of the VSI. It is shown that the low-frequency harmonic components appear in the frequency spectrum of the VSI output voltage due to sampling. As a result, the output current of digitally controlled VSI is stepped in nature. The double Fourier integral solution of the switched waveform for inner and outer integral limits has been used to derive the expression. The integral solution is obtained using Jacobi-Anger expansions. The generalized results developed in this paper are useful to investigate the sampling effect in high switching frequency DSPWM. The proposed sampling effect has been analyzed for SPWM of single-phase H-bridge inverter. The analytical results are verified using simulation and experimental results. The experimental results have been obtained with the use of field-programmable gate array (FPGA) as a digital controller. [ABSTRACT FROM PUBLISHER]

This paper presents a new multilevel cascaded-type dynamic voltage restorer (MCDVR) with a fault current-limiting function. This topology can operate in two operational modes: 1) a compensation mode for voltage fluctuations and unbalances and 2) short-circuit current-limiting mode. The current-limiting function of the MCDVR is performed by activating antiparallel thyristors during the short-circuit fault, and deactivating them during normal operation. The mathematical model of the MCDVR system is also established in this paper. The control scheme design and optimal parameter selection are outlined based on the detailed theoretical analysis of the converter. The transient states of the MCDVR in the compensation mode and current-limiting mode are also analyzed. Simulation results based on the PSCAD/EMTDC software, and experimental results on a laboratory setup help to validate the proposed topology and the theoretical analysis. [ABSTRACT FROM AUTHOR]

A comprehensive study on the dielectric modulated (DM) drift region for power devices is presented in this paper. The performance of this drift region structure is theoretically analyzed and compared with other two structures: conventional and superjunction. In this paper, a study is focused on switching performance. The C – V relationships during switching are analytically derived, and the depletion widths predicted by the proposed analytical model agree well with simulation in a wide reverse bias region. The switching energy loss is evaluated based on the analytical model and its accuracy is verified by 2-D simulations. An effective depletion charge QD is defined as E\mathrm {loss} / breakdown voltage (BV), from which a figure of merit (FOM) of R\mathrm{\scriptscriptstyle ON,\mathrm {sp}}{}^\ast QD is proposed to compare the performances of these different drift region structures, considering both the conduction and switching losses. The discussions in part I on Si and silicon carbide device structures are extended in part II to include FOMs. It is found that the DM drift region structures show better R\mathrm{\scriptscriptstyle ON,\mathrm {sp}} -BV tradeoffs compared with the conventional structures, but slighter inferior FOMs. However, DM structures are still attractive for applications, where switching loss is less critical than the conduction loss, such as low frequency or soft switching. [ABSTRACT FROM PUBLISHER]

A space vector modulation (SVM) technique of a dual-inverter system for an open-end winding motor drive is described in this paper, where one inverter has a battery power source and the other has an only capacitor across the dc bus. The SVM must be achieved to operate the motor with field-oriented control and simultaneously to control the capacitor voltage at a constant value by using redundant switching states of the dual-inverter system. The control of the capacitor voltage is carried out by selecting a charging or a discharging mode in each redundant switching state, taking the instantaneous motor power factor into account. In addition, it is also required to reduce the error voltage pulses, which are generated in output multilevel voltage waveforms during the dead time. The compensation method of the existing dead-time scheme and the improved SVM sequence to reduce the error voltage vectors are proposed in this paper. The proposed methods are examined through several experimental tests and are confirmed to generate superior output voltage waveforms from the viewpoint of the measured total harmonic distortion and dv/dt. [ABSTRACT FROM AUTHOR]

The operating principle of the clamp circuits like clamping diodes and flying capacitor in three-level LLC converter is different from other three-level converters, because the mean value of the resonant tank current is always zero and pulse-frequency modulation control is generally used instead of pulsewidth modulation control. And the converter with only the clamping diodes or flying capacitor is difficult to realize voltage balance. In this paper, the characteristics of the three-level LLC converter with single clamp circuit are first analyzed. Then, the operation principle of the hybrid-clamped circuit under the unbalanced voltages on input capacitors is described with the mode analysis, based on which the mechanism for voltage autobalance is elaborated and the effects of two clamp circuits are derived. Then, the design of the clamping diodes and the flying capacitor is also involved. Finally, a three-level LLC converter prototype is built and the experimental results verify the validity of the theoretical analysis and design. [ABSTRACT FROM AUTHOR]

This paper investigates a Vienna rectifier as a charger for series-connected battery packs. Focusing on carrier-based pulsewidth modulation (CBPWM), the ripple current flowing through the neutral point (NP) results in the voltage oscillation if the loads are resistive. To reduce the ripple of average NP current with mitigated distortion under balanced and unbalanced dc-link voltages conditions, a novel CBPWM with segmented component injection scheme (SCIS) is proposed in this paper. After dc component injection, continuous intervals for optimized component injection and clamping intervals for compensation component injection are identified. Optimized components are calculated originally based on unbalanced factor to make the average NP current zero-size in one switching period. Moreover, unique compensation components generate suitable NP current to shape the sinusoidal input currents according to the circuit analysis. In consequence, the SCIS not only keeps the input current with low-harmonic distortion, but also minimizes the oscillation of dc-link voltage under balanced and unbalanced conditions. In addition, the value of the NP current during the clamping intervals is analyzed under various operating conditions. The effectiveness and the performance of the proposed SCIS are verified by simulation and experiments. [ABSTRACT FROM AUTHOR]

In low-power applications of photovoltaic (PV) systems, the transformerless grid-connected inverters have been preferred to increase the efficiency and reduce the cost, size, and power losses when they are compared to the ones with the transformer. A transformerless single-phase inverter topology with a single dc-link capacitor for the grid-connected PV systems is proposed in this paper. The proposed inverter has been simulated by using a cooperation process of the MATLAB and SPICE package programs and it has been implemented for experimental verification. The proposed inverter reduces the high-frequency common-mode leakage current caused by parasitic capacitances of PV panels, whereas it is controlled with the unipolar sinusoidal pulsewidth modulation. Also, the results show that the common-mode voltage remains constant. The efficiency of the proposed inverter has been compared to that of the most common topologies having the dc-link decoupling during the zero voltage states. This paper is accompanied by a video file demonstrating the power loss distribution in the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a single-inductor dual-output (SIDO) dc–dc converter is proposed. The significant feature of the proposed converter is feeding a constant power load in low-voltage side (LVS) port, where even feeding a variable load at LVS does not have any cross regulation to high-voltage side port with the desired approximation. Magnificently, both merits are obtained in open-loop manner, which is an outstanding characteristic in comparison with that of the existed converters. In this paper, soft commutation and soft switching of switches and diodes are investigated along with the aforementioned main novelty. Moreover, detailed theoretical analyses of the proposed SIDO dc–dc converter in continuous conduction mode are presented besides the comparisons with some other structures. Finally, theoretical analyses are verified through a 1500 W experimental prototype results. [ABSTRACT FROM AUTHOR]

In this paper, a series-capacitor-based interleaving buck power factor correction (PFC) converter is proposed, the intermediate energy storage capacitance of which is operated at discontinuous capacitor voltage mode (DCVM), and automatic power factor (PF) correction for this converter is obtained. Moreover, the voltage across the series capacitor of the proposed PFC converter is clamped at the input voltage, and thus peak voltage stress existed in the traditional DCVM buck PFC could be relieved. By effectively regulating the charge/discharge time for the series capacitor, ultrahigh step-down conversion ratio of the proposed converter is achieved, the conversion ratio of which is independent of the duty cycle and only related to the switching frequency and circuit parameters. Therefore, high PF can be obtained due to very narrow deadtime of the input current. Meanwhile, the proposed PFC converter can realize the soft turn-on of part power switch and soft turn-off of part power diodes. In addition, comparing with the traditional discontinuous inductor current mode PFC, the input current of the proposed PFC converter is continuous so that the peak value and root-mean-square value of input current can be reduced. The operational principle, performance analysis, and parameter design principle are given in this paper. The analysis results show that the PF and total harmonic distortion are also independent of the duty cycle. Finally, a 220-Vac input, 60 W/15 V output experimental prototype is built to verify the validity of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper describes a dc-link voltage control method of a single-phase back-to-back cascaded H-bridge inverter (SBCI) for a medium-voltage motor drive system. The main advantage of the SBCI topology over the conventional regenerative cascaded H-bridge topology with a three-phase active front-end (AFE) is a simple system structure, which is composed of an input transformer, a power cell, a current sensor, etc. However, the challenging points of the SBCI are larger voltage ripple in the dc-link capacitor and imbalance of dc-link voltages of each phase. The asymmetric dc-link voltage of each power cells could cause unstable operation such as over-modulation due to the lack of the dc-link voltage of a particular phase and result in over-voltage or under-voltage faults. In this paper, the control strategy of the dc-link voltage for the SBCI that uses the negative-sequence voltage of the converter is described. The proposed control method is verified with a computer simulation whose target is a 6.6-kV–1.25-MW medium-voltage drive system. Also, through the experimental setup with the prototype SBCI whose power rating is 16.2 kVA, the dc-link voltage of each AFE has been controlled within a 0.5% error of its reference value at the full load. [ABSTRACT FROM AUTHOR]

The neutral-point voltage-balancing control is a critical issue of a neutral-point-clamped converter. The conventional control strategy is to inject the specific zero-sequence voltage to regulate the redundant vector, but it is unacceptable to the three-phase four-wire system. This paper provides a neutral-point voltage-balancing control by the dipolar modulation, and the control freedom of the zero-sequence voltage is flexible. Therefore, the proposed method is suitable for both three-phase three-wire and three-phase four-wire systems. Besides, the proposed method improves the control dynamic in a reactive power system. The proposed neutral-point voltage-balancing control is verified by the mathematical analysis and experimental results. The control dynamic, power loss estimation, and the output current performance are analyzed in this paper. [ABSTRACT FROM PUBLISHER]

The aim of this paper is to study the dynamics of a permanent magnet direct current (PMDC) brushed motor while two crucial space-domain effects, namely, slotting effect and commutation phenomenon are taken into account. Semi-analytical dynamic time-domain PMDC brushed motor model inclusive of these space-domain effects is used to analyze and investigate the dynamics. Pulse width modulation operated discontinuous current PMDC brushed motor drive with steady duty cycle is employed to acquire the bifurcation patterns. The chaotic nature due to slotting effect and commutation is identified from the bifurcation patterns and reported. It also has to be admired that such nonlinear dynamical behavior with the same set of parameters at similar operating condition has not been observed when a conventional PMDC brushed motor dynamic model is considered. These space-domain effects, namely, slotting effect and commutation also have a prominent impact to make some time-domain states of a PMDC brushed motor drive chaotic. The role of slotting effect and commutation phenomenon to analyze the chaos over time-domain state variables of the PMDC brushed motor drive is investigated and validated experimentally in this paper. [ABSTRACT FROM PUBLISHER]

Transport properties of realistic phosphorene nanoribbons (PNRs) with edge defects are studied by using statistical atomistic quantum transport simulations. Regarding the impact of nanoribbon width downscaling and increasing of edge defect percentage, we show that PNRs exhibit qualitatively similar behavior of the ON- and OFF-state conductance, and of the ON–OFF conductance ratio as graphene nanoribbons (GNRs). However, we demonstrate that PNRs are superior to GNRs in terms of the absolute values of the conductance parameters, and that PNRs are much more immune to edge defects than their graphene counterparts. This paper identifies PNRs as a more promising channel material than GNRs for the extremely scaled postsilicon transistor technology. [ABSTRACT FROM PUBLISHER]

This paper describes a low-power 1-GHz 4-bit time-domain arithmetic logic unit (ALU) targeting hardware accelerator. This ALU relies on the time-domain computation based on digital-to-time converter, digitally controlled oscillator, time-to-digital converter, and successive approximation register analog-to-digital converter. The interconnect bandwidth limitation addressed by the time-domain and voltage-domain encoding to improve the spectrum efficiency by $8\times $ . Encoder and decoders are part of the computation, and that results in 1-GHz operational speed in 65-nm CMOS consuming 17.75 mW only. Compared to the conventional approach, the proposed time-domain computation achieves significantly lower power and latency for similar area and resolution. [ABSTRACT FROM AUTHOR]

This paper presents Space Vector Modulation (SVM) sequences that reduce Common Mode Voltage (CMV) in Dual Three-phase Asymmetrical Induction Motor (DTAIM). At first, two existing SVM techniques such as Reference SVM (RSVM) and CMV1 are studied. Additionally, three new switching sequences are developed as CMV2, CMV3 and DCMV3, which reduce peak magnitude of CMV by 66.8% in comparison with RSVM technique. In SVM techniques, to obtain least CMV, zero vectors are usually replaced by two opposite large Active voltage Vectors (AV) with equal time duration. In such topologies like CMV1, total six AVs are utilized to synthesize the reference vector. The proposed SVM technique CMV2 utilizes only five large AVs to synthesize the reference vector and reduces CMV. Selection of five neighbouring AVs is reflected in reduction of harmonic flux trajectories and stator current ripple in proposed techniques. Additionally, two more switching sequences (CMV3 and DCMV3) are developed related to utilization of specific zero voltage vectors in all sectors (7 and 56) that produce zero CMV. These two switching sequences also provide easy implementation feature during the development of c-code program. In this study, CMV and stator current ripple are considered as performance parameters for different SVM techniques. All SVM techniques are analysed by analytical results, computer simulations, and using prototype test setup of DTAIM fed by Dual Three-phase Voltage Source Inverters (DTVSIs). [ABSTRACT FROM AUTHOR]

Multilevel converters are a proven solution for medium-voltage and high-power applications, including renewable energy conversion. Developing 6.6-kV converters is a key goal for the wind turbines industry. Considering the voltage rating of commercially available semiconductors, five-level converters are necessary to reach 6.6 kV. The five-level active neutral-point-clamped converter (5L-ANPC) is one of the most advantageous topologies among five-level multilevel converters. This paper presents a new 5L-ANPC topology that overcomes the features of the previously employed 5L-ANPC topology. Along this paper, the properties and working principle of this new 5L-ANPC are explained. Finally, the validity of the new converter is validated via simulation and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel Verilog-A based memristor model for effective simulation and application. Our proposed model captures desired nonlinear characteristics using voltage-based state control. This model is flexible and accurate, it can exhibit all the behaviors of HP memristive device and a general class memristive device resistive random access memory which is important in logic and memory design. Furthermore, we can antiserially connect two proposed models to capture the ideal I – V characteristics of complementary resistive switch (CRS). We demonstrate that our proposed CRS model-based crossbar arrays can significantly reduce sneak path currents with high noise margin compared to traditional memristor-based architectures. [ABSTRACT FROM AUTHOR]

This paper was written to share the experience acquired in the specification of surge suppressors (snubbers) for protection against switching transients’ overvoltage resulting primarily in dry-type transformers failures in some plants in Brazil and North America. This paper will also explain about the snubber ratings (damping resistor, surge capacitor, and surge arrester), the assembly special cares, system modeling, and simulations using the software Alternative Transient Program. [ABSTRACT FROM PUBLISHER]

This paper proposes a visible light communication (VLC) system consisting of a single-stage buck–boost power factor correction converter operating in the discontinuous conduction mode with dimming capability. Additionally, this paper proposes the on–off M-frequency shift keying modulation for the VLC system. This modulation allows for the transmission of more than a single bit for each switching period without affecting the dimming characteristics of the light-emitting diode luminaire. The design of the whole system is discussed in detail, including both transmitter and receiver modules. A 20-W laboratory prototype was built in order to verify the proposed modulation scheme. The experimental evaluation showed a good performance of the transmitter, which was able to perform simultaneously the desired functions, namely power factor correction, dimming, and data transmission. The receiver also achieved the desired performance with a low bit error rate (BER). The results showed that the proposed system was able to transfer data between emitter and receiver with a bit rate of 1.11 Mb/s at a frequency of up to 375 kHz over a distance of 10 m, and with a BER lower than $10^{-3}$ under the influence of external lighting sources with illuminance levels up to 500 lx. [ABSTRACT FROM AUTHOR]