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In this work, we study oxide defects in various III-V/high-k metal-oxide-semiconductor (MOS) stacks. We show that the choice of a given starting measurement voltage with respect to the MOS flat-band voltage affects the observed capacitance-voltage hysteresis. We discuss how this behavior can be used to study the distribution of oxide defect levels. With the help of comprehensive experimental data, we show that Al2O3 and HfO2 have different hysteresis characteristics related to different oxide defect distributions. In case of an Al2O3/HfO2 bilayer stack with Al2O3 on the channel side (interfacial layer, IL), as the IL thickness reduces from 3 nm to 0 nm, the hysteresis behavior switches from the typical Al2O3 behavior to the one corresponding to HfO2. We link the characteristic behavior of two dielectrics to the defect level distributions inside their respective band-gaps through a simple energy-driven charging model. Based on the experimental data and simulation results, we show that Al2O3, despite having a lower peak defect density as compared to HfO2, shows a very wide, almost continuous distribution of defect levels across and around the InGaAs channel energy band gap. These results explain the often reported poor reliability of III-V devices with Al2O3-based gate stacks. [ABSTRACT FROM AUTHOR]

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high- ${k}$ /metal gate (HKMG) stacks at a reduced thermal budget (<525 °C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of “defect decoupling” layers–LaSiOx for nMOS and Al2O3 for pMOS–at the interface between SiO2 and HfO2 as a promising approach to engineer the high- ${k}$ band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiOx and Al2O3 insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigation on the effects of LaSiOx and Al2O3 insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al2O3) or even improved carrier mobility (LaSiOx) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al2O3 layer (for hole trap decoupling) is deposited in the nMOS gate-stack, even if on top of the beneficial LaSiOx (for electron trap decoupling). In contrast, the pMOS gate-stack is found to be more tolerant to the presence of a residual LaSiOx layer on top of the beneficial Al2O3 layer, suggesting a viable strategy for the simplified dual gate-stack integration. Finally, the reliability improvement is validated also on a FinFET test vehicle. [ABSTRACT FROM AUTHOR]

A comprehensive investigation on the hot-carrier-induced interface state generation and its impact on carrier mobility in nMOSFET is performed. I – V compact modeling and charge pumping (CP) characterization are used as independent ways to evaluate the interface state density as a function of hot-carrier-induced aging. From the two techniques, similar power-law time exponents of the interface state density kinetics are obtained. Assisted by the quasi-spectroscopic (temperature-resolved) CP measurement, the extracted interface state density is further correlated with the I – V modeling results: an universal mobility degradation normalization parameter Nit,ref = ~ 4.1 × 1011/cm2 is reported, irrespective of the effective oxide thickness (EOT), stress temperature, or the relative degradation of the device under test (DUT). Supported by the fundamental principles deployed in the derivation and the broad range of experimental conditions considered for its validation, the reported normalization parameter could serve as a modeling constant in the commonly used I – V compact models to correlate the mobility degradation with the interface state density induced by hot carrier stress. [ABSTRACT FROM AUTHOR]

We report measurements of multiple hot-carrier (HC) stress and high-temperature anneal cycles repeated on the same nFETs fabricated in a commercial 40-nm bulk CMOS technology. We model this cycled HC degradation anneal assuming Si–H bond breakage during stress and bond passivation during anneal, with the bond dissociation and passivation energies following a bivariate Gaussian distribution. Our model can describe multiple stress and anneal time scenarios well using a single parameter set and provides insights into the recovery behavior of HC-induced defects. We find no correlation between bond dissociation and passivation energies and observe that the repeated HC stress and anneal cycles suppress the low energies from the distribution of bond passivation energies, changing its shape from the Gaussian to a non-Gaussian form. [ABSTRACT FROM AUTHOR]

Low thermal budget junction-less transistors with back-gate are fabricated as top-tier devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and bias temperature instability (BTI) reliability is investigated. The back-gate bias is shown to modulate the carrier mobility: specifically, mobility is increased under forward back-gate bias (FBB), which is ascribed to the carrier redistribution from the front-gate interface toward back-gate interface. Regarding BTI reliability, if a back-gate bias (VBG) is applied only during ON-state and a constant front-gate stress VG is used, BTI reliability is not influenced by the applied VBG (due to its negligible impact on the front-gate oxide field, Eox). Therefore, supplying an FBB during ON-state can be used to adjust device performance—as VBG modulates the channel current through Vth and mobility—without reliability penalty. On the other hand, if the back-gate bias is applied during both ON- and OFF-states, while a constant stress Vov is maintained by adjusting the front-gate VG [i.e., VG – Vth (VBG) is kept constant under different VBG’s], the BTI reliability can be improved under FBB (due to a reduced Eox in the front-gate) without performance loss. The latter property can be used to improve the device reliability under circuit operation. [ABSTRACT FROM AUTHOR]

Junction-less FETs are used as top-tier devices in a 3-D sequential integration. Due to the low thermal budget allowed in the 3-D integration, conventional inversion mode FETs show extremely poor BTI reliability. In contrast, a junction-less FET shows improved BTI reliability, which is attributed to the reduced oxide electric field of operation. We observe that the reliability of junction-less FETs can be further improved by increasing the channel doping and/or the channel thickness. Correspondingly, a tradeoff exists between performance (subthreshold slope, carrier mobility), reliability, and variability. This tradeoff is verified in both planar/FinFET structures and can serve as a device optimization matrix. Furthermore, we use the non-radiative multi-phonon (NMP) theory, as implemented in the imec/T.U. Vienna BTI simulation framework “Comphy,” to investigate the degradation kinetics and show that the stress/recovery traces measured in inversion mode and junction-less nFETs can be reproduced with the same set of oxide defect parameters. This observation confirms that the reliability improvement in junction-less devices is inherent to their specific operation mode and not related to the different fabrication flows compared to standard inversion mode devices. Based on the calibrated Comphy model, we perform BTI lifetime projections, exposing for junction-less devices a substantial deviation from the commonly used power-law voltage acceleration. [ABSTRACT FROM AUTHOR]

Operating temperature has a significant imp-act on the reliability of metal–oxide–semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects ($\Delta {N}_{\text {eff}}$) at operating condition typically shows an Arrhenius temperature dependence with ${E}_{\text {A}}$ ~ 0.1 eV. In contrast, apparent non-Arrhenius temperature dependence is reported here for InGaAs devices subjected to BTI stress in a wide range of temperature (77–373 K). This apparent non-Arrhenius temperature dependence is explained here by the presence of three distinct populations of electron traps. Capture–emission-time maps are derived from the experimental data, and are modeled by three bivariate distributions of energy barriers for the capture and emission processes. The total $\Delta {V}_{\text {th}}$ measured in bias-temperature-instability experiments reflects different contributions from the three defect populations, depending on the chosen temperature range, and on the measurement timing. We show that a correct description of the three defect distributions is crucial to properly assess their impact on the device performance. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process. [ABSTRACT FROM PUBLISHER]

To predict the negative bias temperature instability (NBTI) toward the end of pMOSFETs’ ten years lifetime, power-law-based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. n reported by early work spreads in a wide range and varies with measurement conditions, which can lead to unacceptable errors when extrapolated to ten years. The objective of this paper is to find how to make n extraction independent of measurement conditions. After removing the contribution from as-grown hole traps, a new method is proposed to capture the generated defects (GDs) in their entirety. n extracted by this method is around 0.2 and insensitive to measurement conditions for the four fabrication processes we tested. The model based on this method is verified by comparing its prediction with measurements. Under ac operation, the model predicts that the GD can contribute to ~90% of NBTI at ten years. [ABSTRACT FROM PUBLISHER]

This letter proposes a metric to assess the quality of high-k dielectrics on III–V substrates and a benchmarking methodology for the gate stack qualification in the region of MOS device operation above threshold voltage, Vt . The metric is based on a capacitive equivalent thickness (CET) - normalized frequency dispersion ( \textD\mathrm {eff} ) evaluated in the accumulation region of capacitance–voltage (C–V) measurements of III–V MOS devices. D \mathrm {eff} is found to be CET independent, which allows for a preliminary assessment of the dielectric quality by using relatively thick layers. Several gate stacks, single layer or bi-layer, including those with Al2O3, and the recently reported ASM-imec interfacial layer (IL) with HfO2 are evaluated and compared against Si MOS devices. Using the proposed technique, a clear difference between the various deposition processes is observed. The results indicate that the quality of a single layer Al2O3 or a bi-layer stack of Al2O3/HfO2 on InGaAs is significantly lower compared with Si gate stacks while the ASM-imec IL yields a gate-stack with good performance on the proposed quality metric. In addition, these results correlate well with the reliability performance of the studied gate stacks. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the single defect discharge events in Ge-source n-type vertical nanowire tunnel field effect transistors, by monitoring the relaxation phase which follows bias temperature instability (BTI) stress. Threshold voltage shift induced by single discharge events follows a bimodal Weibull distribution, with the location parameter of the second mode being significantly higher than the first one. Both modes are temperature independent. Based on TCAD simulations, we propose that the second mode is associated with defects located at the source/channel junction close to the channel/oxide interface, while the first mode is ascribed to oxide traps far from the source/channel junction. Although present in smaller numbers, such traps with a larger average impact on the device characteristics are expected to dominate the BTI-induced variability in a large population of nanoscale devices for realistic applications. [ABSTRACT FROM PUBLISHER]

We extend our previously suggested drift-diffusion (DD)-based hot-carrier degradation model to the case of decananometer transistors. Special attention is paid to the effect of electron–electron scattering, which populates the high energy tail of the carrier distribution function, by using a rate balance equation. We compare the results of the DD-based model with the results obtained from a spherical harmonics expansion of the Boltzmann transport equation as well as experimental data. We also study the accuracy and limits of the applicability of the DD-based model and conclude that this model is able to capture hot-carrier degradation in nMOSFETs over a range of gate lengths from 65 to 300 nm with excellent accuracy. [ABSTRACT FROM PUBLISHER]

We study the positive bias temperature instability (PBTI) of InGaAs tunnel-FETs (TFETs) with two different indium fractions (53% and 70%) and compare with reference MOSFETs, using the same gate stack. While identical threshold voltage instability is found irrespective of the device type, the subthreshold swing (SS) of the TFETs is found to be more robust against PBTI as compared with MOSFETs. With the aid of comprehensive TCAD simulations, we show that the SS of a TFET is intrinsically less sensitive to interface/oxide border traps, thanks to the narrow energy range swept by the channel Fermi level during the OFF-to-ON transition of the device operation. Moreover, only traps located within $\sim 20$ nm from the tunnel junction can affect the SS. [ABSTRACT FROM PUBLISHER]

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al2O3 gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxation. Hence, a defect band model with different distributions of defect levels inside the gate dielectric is proposed, which can excellently reproduce the experimental data and provide insightful information about the origin of PBTI in GaN MISFETs. The results indicate that the serious PBTI in the device with PEALD SiN is mainly due to a wide distribution of defect levels ( \sigma \sim 0.67 eV), centered below the conduction band of GaN ( E_{C} -0.05 eV), and can be easily accessed by the channel carriers already at a low-gate voltage. On the other hand, ALD Al2O3 gate dielectric shows a narrower distribution of defects ( \sigma \sim 0.42$ eV), which are far from the conduction band of GaN ( E_{C} +1.15 eV). This observations explain the improved PBTI reliability observed in devices with ALD Al2O3. [ABSTRACT FROM AUTHOR]

Using our physics-based model for hot-carrier degradation (HCD), we analyze the temperature behavior of HCD in nMOSFETs with a channel length of 44 nm. It was observed that, contrary to most previous findings, the linear drain current change ( \Delta I\mathrm {d,lin} ) measured during hot-carrier stress in these devices appears to be lower at higher temperatures. However, the difference between the \Delta I\mathrm {d,lin} values obtained at different temperatures decreases as the stress voltage increases. This trend is attributed to the single-carrier process of Si–H bond rupture, which is enhanced by the electron–electron scattering. We also consider another important modeling aspect, namely, the vibrational life-time of the Si–H bond, which also depends on the temperature. We finally show that our HCD model can successfully capture the temperature behavior of HCD with physically reasonable parameters. [ABSTRACT FROM PUBLISHER]

In this work, we discuss how the position of the flat band voltage with respect to the starting voltage of the C-V measurement sweep can influence the estimation of the hysteresis in high-k/InGaAs MOS devices. We show that, with the support of experimental data and conceptual oxide defect band calculations, the interpretation and subsequent parameter extraction from flat-band voltage shifts observed in III-V MOS devices is more complex as compared to Si gate stacks. It is demonstrated that such complication arises due to the wider distribution of defect levels in the dielectric band gap in the case of InGaAs/high-k stack as compared to standard Si/SiO2/HfO2MOS. In particular, for Al2O3 deposited on InGaAs, two wide, partially overlapping oxide defect bands are identified, centered ~1.5 eV and ~0.5 eV above and below the channel conduction band, respectively. Such defect levels are expected to affect the device operation and reliability. [ABSTRACT FROM AUTHOR]

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection. [ABSTRACT FROM AUTHOR]

We investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The measured activation energies for interface-trap charge buildup during negative-bias temperature stress are lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce the strength of nearby Si–H bonds and that Ge–H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2. [ABSTRACT FROM PUBLISHER]

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-gm), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si3N4, Rapid Thermal Chemical Vapor Deposition Si3N4, and Atomic Layer Deposition (ALD) Al2O3) for AlGaN/GaN Metal-Insulator- Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (Dit), the amount of border traps, and the threshold voltage (VTH) shift during a positive gate bias stress can be obtained. The results show that the VTH shift during a positive gate bias stress is highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the VTH shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract Dit needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the gm dispersion commonly attributed to border traps might be influenced by interface states. [ABSTRACT FROM AUTHOR]

This paper presents an extensive study of the interplay between as-fabricated (time-zero) variability and gate oxide reliability (time-dependent variability) in contemporary pMOSFETs. We compare physical simulation results using the atomistic simulator GARAND with experimental measurements. The TCAD simulations are accurately calibrated to reproduce the average transistor behavior. When random discrete dopants, line edge roughness, and gate polysilicon granularity are considered, the simulations accurately reproduce time-zero (as-fabricated) statistical variability, as well as time-dependent variability data, represented by threshold voltage shift distributions. The calibrated simulations are then used to predict the reliability behavior at different bias conditions and for different device dimensions. [ABSTRACT FROM PUBLISHER]