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Novel designs of paper-based bandstop frequency-selective surfaces (FSSs) are presented in this article. The characteristics of the paper-based honeycomb structure are investigated first. One folded dipole resonator with first-order bandstop response is analyzed and further printed on the sidewalls of the honeycomb structure accordingly. A second-order response with two cascade FSSs is proposed with controllable bandwidth by the coupling coefficient of the resonators with the aid of the equivalent circuit model. Two paper-based FSS samples were fabricated and measured to demonstrate the validity of the proposed design strategies. Benefiting from the merits of lightweight and strong mechanical properties, the proposed paper-based FSS is a potential candidate for application in radar systems and aircraft. [ABSTRACT FROM AUTHOR]

Due to the increasing size of integrated circuits (ICs), their design and optimization phases (i.e., computer-aided design, CAD) grow increasingly complex. At design time, a large design space needs to be explored to find an implementation that fulfills all specifications and then optimizes metrics like energy, area, delay, reliability, etc. At run time, a large configuration space needs to be searched to find the best set of parameters (e.g., voltage/frequency) to further optimize the system. Both spaces are infeasible for exhaustive search typically leading to heuristic optimization algorithms that find some tradeoff between design quality and computational overhead. Machine learning (ML) can build powerful models that have successfully been employed in related domains. In this survey, we categorize how ML may be used and is used for design-time and run-time optimization and exploration strategies of ICs. A metastudy of published techniques unveils areas in CAD that are well explored and underexplored with ML, as well as trends in the employed ML algorithms. We present a comprehensive categorization and summary of the state of the art on ML for CAD. Finally, we summarize the remaining challenges and promising open research directions. [ABSTRACT FROM AUTHOR]

This letter describes a single-transistor oscillator implemented on a paper substrate at the operating frequency of 24 GHz, based on a design procedure that makes it possible to overcome the limitations caused by thin high-loss substrates and package parasitics of commercial components. The commercial transistor adopted in the oscillator is led to instability by exploiting its parasitic gate inductance. The drain network compensates for the parasitic inductance of the transistor package and connects the oscillator circuit to a 50- $\Omega $ load resistance. Finally, an external inductor at the source terminal is used to resonate out the capacitive contribution of the circuit at the oscillation frequency. Overall, the active device appears in a quasi-common-drain stage. Experimental results on prototype show that the oscillator exhibits an output power of +6.2 dBm at 24 GHz, with a dc power consumption of 72.5 mW. [ABSTRACT FROM AUTHOR]

The paper presents new diagnostic method applied to assess aging degree for paper-oil insulation used in professional electrical power device, primarily including medium and high power transformers. The described method is based on modified diagnostics using the recovery voltage effect occurring in dielectrics (RVM ? Recovery Voltage Methods). Modification of the RVM method applied so far, which is now used only to assess moistening degree for paper-oil insulation in power transformers, consists in a new parametric analysis of recovery voltage time characteristics. Simulation and experimental tests carried out in laboratory conditions for adequately prepared insulation samples have proven that the time-constant of recovery voltage decay (?R_MIN) is the most susceptible parameter as regards quantitative change in the function of aging of the examined insulation. This conclusion is also confirmed by statistical studies, in which a multi-parameter variance analysis method has been applied. An original equivalent circuit diagram of the insulation has been used to simulate aging degree of paper-oil insulation samples in numerical tests. The diagram is based on the Cole-Cole type dielectric response model. [ABSTRACT FROM AUTHOR]

This paper provides an industry perspective on the present state of compact models for MOS transistors. It highlights the complexity of layout-dependent effects in modern transistors, reviews some common misunderstandings of MOS transistor capacitances, and introduces a new, structurally symmetric, “gate-as-input” equivalent network for these capacitances. Areas of focus for the future model developments are also proposed. [ABSTRACT FROM AUTHOR]

Chemical mechanical planarization (CMP) is vital for ensuring chip fabrication uniformity at nanometer scales. The emergence of a series of phenomenological CMP process models (Stine et al., 1997; Gbondo-Tugbawa, 2002; Xie, 2007; Vasilev, 2011) suggests that the existing model upgrade approach is largely based on a change in phenomenological model assumptions, demanding deep insights into complex process mechanisms and protracted period for accuracy improvements. To tackle this issue, this paper proposes a decoupling regression strategy for model upgrades. This strategy employs a data-driven approach to enhance the coupling relationships within the model, facilitating continuous improvement of simulation accuracy based on the existing model. It is capable of achieving improvements in model accuracy even in scenarios where modelers lack insight into complex process mechanisms. We validate our method by upgrading the Density Step Height (DSH) model to the Extend-DSH model to address poor erosion predictions at the 28nm node. Comparing model predictions with silicon data reveals that the Extend-DSH model aligns better with the measured data, reducing the root mean square error from 159.31Å to 6.89Å and increasing the coefficient of determination from -0.83561 to 0.6058, showcasing the effectiveness of the proposed chip-level CMP model upgrade method grounded in the decoupling regression strategy. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the editor discusses various articles within the issue on topics including research and development in compact models, metal oxide semiconductor field-effect transistors (MOSFET) modeling and RF Compact Model for Bulk MOSFET.

The simulation of electric field transients in HVDC cables can be a fundamental tool to support insulation system design when operation dynamics, which includes voltage polarity inversions and load variation, becomes significant during the expected cable life. The field behavior during voltage and temperature transients is associated with intrinsic and extrinsic ageing processes that can affect the cable design life. Traditional models employed for electric field simulations consider only the non–linear, steady–state dependence of conductivity on temperature and field magnitude, but they neglect the transient behavior of permittivity and conductivity, that is, polarization and charge trapping phenomena. These processes impact on the duration of the field transient and thus ageing. This paper discusses the numerical implementation of an electro–quasistatic model that can be used to perform transient simulations of electric fields in HVDC cables insulation. With respect to the model traditionally employed, the presented one is extended with Debye's equations for dielectric polarization processes. The model is implemented numerically using finite differences, or the Occhini equivalent circuit: this paper demonstrates that the two approaches are equivalent. Numerical simulations show that, during transients, polarization processes slow down the electric field dynamics and reduce its maximum intensity. [ABSTRACT FROM AUTHOR]

Fault diagnosis and fault tolerant (FT) control of electric drive systems have been extensively studied by many researchers. Naturally, one would like to use fault diagnosis information to improve FT control to achieve good post-fault performance while it is safe to do so. In this paper, a novel FT control method is proposed for permanent magnet synchronous motor with inter-turn short circuit fault. Given fault severity, the proposed FT control can reduce torque ripple while keeping reasonable torque output. The theoretical derivation, simulation, and experimental validation are presented in this paper. [ABSTRACT FROM AUTHOR]

Motivated by the fact that living cells use molecular circuits (i.e., a set of chemical reactions) for information processing, this paper investigates the problem of designing molecular circuits for demodulation. In our earlier work, we use a Markovian approach to derive a demodulator for diffusion-based molecular communication. The demodulation filters take the form of an ordinary differential equation, which computes the log-posteriori probability of a transmission symbol being sent. This paper considers the realization of these demodulation filters using molecular circuits assuming the transmission symbols are rectangular pulses of the same duration but different amplitudes, i.e., concentration modulation. This paper makes a number of contributions. First, we use time-scale separation and renewal theory to analytically derive an approximation of the demodulation filter from our earlier work. Second, we present a method to turn this approximation into a molecular circuit. By using simulations, we show that the output of the derived molecular circuit is approximately equal to the log-posteriori probability calculated by the exact demodulation filter if the log-posteriori probability is positive. Third, we demonstrate that a biochemical circuit in yeast behaves similarly to the derived molecular demodulation filter and is therefore a candidate for implementing the derived filter. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

The impedance expansion method (IEM), which has been previously proposed by the authors of this paper, is a circuit modeling technique for electrically very small devices. This paper describes a circuit modeling procedure that utilizes the IEM and eigenmode analysis for a wireless power transfer system. First, a multimode circuit model that can represent the higher order resonances in a broadband frequency range is presented. Subsequently, a single-mode circuit model—consisting only of passive elements—that can represent both the radiated and conduction loss powers at approximately its operating frequency band is presented. [ABSTRACT FROM AUTHOR]

Reinforcement, extinction, generalization and differentiation are all basic principles of Pavlov associative memory. Most memristive neural networks that simulate associative memory only consider reinforcement and extinction, while ignoring differentiation and generalization. In this paper, a memristive circuit of associative memory with generalization and differentiation is proposed to solve the above problem. It implements the functions of learning, forgetting, long-term memory, generalization and differentiation. Learning and forgetting correspond to reinforcement and extinction in associative memory respectively. Spontaneous recovery, in which forgotten reflexes can reappear in the absence of an unconditional stimulus, is also discussed here. Besides, a special differentiation method that takes into account the time delay is designed and demonstrated. The proposed memristive circuit of associative memory provides a reference for the theoretical research and application of artificial neural networks. [ABSTRACT FROM AUTHOR]

Direct-drive wave energy converter (WEC) and buoy control algorithms have shown great potential for renewable wave energy extraction in ideal conditions. However the actual power take-off (PTO) impacts are barely considered in the WEC design. This paper highlights the demands of designing the WEC wave-to-wire control from a global point of view by studying the actual PTO impacts. A permanent magnet linear electrical machine (LEM) PTO unit is simulated and controlled to fulfill the WEC buoy control requirements. Several state of the art control algorithms, which include singular-arc (SA) control, shape-based (SB) control, model predictive control (MPC), and proportional-derivative (PD) control, are applied to maximize the wave energy production (mechanical energy). Multiple types of electrical PTOs, including ideal PTO, unlimited PTO and limited PTO, are all implemented to evaluate WEC wave-to-wire performances. Further, the PTO copper loss model and the PTO actual efficiency maps are introduced and studied to improve the electrical PTO operation efficiency. To further assess the control schemes in various wave conditions, one-year PacWave ground-truth data is applied as well. Numerical simulations are conducted using MATLAB/Simulink and the Simscape toolbox. The electrical PTO unit is composed of a LEM, an ideal inverter, and an ideal energy storage system. The results show that the actual PTO will impact the constrained controls (MPC and SB) less comapring to unconstrained controls (SA and PD). Although SB can produce the maximum energy with the limited PTOs, it is not robust for all wave conditions. At the end of the paper, the possible solutions for improving the WEC wave-to-wire performances are also provided. [ABSTRACT FROM AUTHOR]

An increasing need for fast and reliable models has led to a continuous development of Fourier-based (FB) analytical modeling. This paper presents an overview of the techniques that are currently available in FB modeling for electric machines. By coupling that overview to the most relevant literature related to the subject, an interesting starting point is provided for anyone who wants to use or improve FB models. The following seven aspects of FB models are discussed in detail: 1) the magnetic potential (scalar or vector potential); 2) the coordinate system and the solution of the partial-differential equations for each magnetic potential and for each coordinate system; 3) the way in which time dependence is accounted for; 4) the implementation of the source terms; 5) the possibilities to account for slotted structures; 6) the modeling of eccentricity; and 7) the post-processing computation of physical quantities, such as flux density, electromotive force, torque, losses, and eddy currents in conductive objects. Furthermore, this paper gives the closed form solution of the Laplace, Poisson, and Helmholtz equations in each coordinate system. In addition, this paper tackles other important features of FB models such as computational time reduction and coupling the machine model to an electric circuit. [ABSTRACT FROM AUTHOR]

The Potential Transformer (PT) plays an important role in the measurement and monitoring of the power system. The accurate modeling of the PT is very important but not yet perfect. The stray capacitance will have a non-negligible effect on the performance of a PT. However, the influence of stray capacitance is rarely considered in existing models, which makes the broadband simulation performance weak and provides limited references in engineering. In this paper, a calculation method of PT stray capacitance is proposed to analyze the performance of the PT at different frequencies and extract the capacitive current of the PT port. This paper used a non-destructive method to obtain the test data of a PT, calculated the value of the stray capacitance, and drew the hysteresis loops of the iron core. A corresponding simulation model was established to predict the PT performance at different frequencies. The simulation results are in good agreement with the experimental data, which proves the accuracy of the modeling parameters. The data processing logic is clear and is easy to be simplified by programming, which makes it promising in engineering. [ABSTRACT FROM AUTHOR]

In this paper we present economical interdigitated flexible sensor on the paper substrate for bacteria detection. The impedance measurement was performed in the frequency range of 12.6 kHz–100 kHz for the suspensions with cell density of $1.5\cdot 10^{8}$ CFU/mL, $1.5\cdot 10^{5}$ CFU/mL and $1.5\cdot 10^{2}$ CFU/mL of Pseudomonas aeruginosa and Staphylococcus aureus bacteria, as well as for a sterile saline. Using the measured impedance data, we observed that sensor impedance magnitude increases when bacteria concentration increases. Moreover, impedance spectroscopic analysis was carried out to identify an equivalent electrical circuit for the sensor modelling. Through statistical analysis it was found that all model parameters changes according to the bacteria type and concentration. Additionally, obtained results showed that all fittings results in root mean square errors lower than $0.072~\Omega $ for impedance magnitude, and 0.157° for impedance phase angle. [ABSTRACT FROM AUTHOR]

A logic diagnosis procedure provides information about the defects that are present in a faulty unit as a set of candidate faults. To obtain smaller, and more accurate, sets of candidate faults, a diagnostic test generation procedure produces a test set that distinguishes fault pairs. This paper observes that large sets of candidate faults are obtained when multiple defects are present in a faulty unit, even if a diagnostic test set is used for logic diagnosis. This points to the possibility that fault pairs do not provide a complete set of targets for diagnostic test generation. This paper analyzes the conditions that cause a large set of candidate faults to be formed under a particular logic diagnosis procedure and suggests new targets for diagnostic test generation. The experimental results for benchmark circuits demonstrate that a diagnostic test set can be improved by adding diagnostic tests for the new targets. [ABSTRACT FROM AUTHOR]

After a transformer failed following a double-phase fault, there was an interest in understanding how the fault mechanism led to the failure. This paper investigates this fault condition in detail and demonstrates the underlying challenges in correcting the failure. The electrical and thermal system models were developed and simulated to analyze the transformer response under double-phase fault conditions. Experimental measurements validated the simulation results on a real three-phase distribution transformer. This paper presents the results from simulated and experimental analysis from double-phase fault on a Yg–Yg distribution transformer. [ABSTRACT FROM AUTHOR]

Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley–Reed–Hall-based trap model, yielding a comprehensive FET model for GaN HEMTs which can accurately model GaN devices exhibiting trapping-related dispersion effects. Measurement results of the dc and pulsed output and transfer characteristics of a commercially available GaN HEMT are presented, trapping in the device is modeled, and excellent fit to the measured data is shown. This paper presents an accurate model of trapping which is validated for eight different quiescent bias points of pulse measurements, with quiescent drain voltage ranging from 5 to 20 V and quiescent gate voltage ranging from −2.8 to −3.8 V, and a large range of gate and drain voltages to which the device was pulsed in the pulse measurements and at which the device was measured in the dc measurements, with gate voltage ranging from −4 to 0.4 V and drain voltage ranging from 0 to 40 V. This paper also presents high-frequency (10 GHz) large-signal RF validation of the model for optimal complex load condition. [ABSTRACT FROM AUTHOR]

Multiarm slotline stubs have been used to increase the bandwidth of slotline open circuits in transitions between microstrip and slotline and between coplanar waveguide and slotline. The model used in prior papers is a series connection of the short-circuit terminated stubs, resulting in an increase in the input impedance by a factor of $N$ , where $N$ is the number of stubs. In this paper, it is shown that this model cannot be applied for slotline with finite width metal planes or coplanar stripline (CPS), because it does not account for higher order modes that are necessarily excited on the multiarm structure. This paper presents a physical explanation and model that accounts for the higher order modes on the structure and explains how the multiarm finite width slotline/CPS stub structure increases the bandwidth of the transitions between slotline and other transmission lines. With the correct model presented in this paper, it is expected that improved slotline or CPS circuits can be developed. [ABSTRACT FROM AUTHOR]

In this paper, the performance drift of digital closed-loop quartz flexible accelerometer (QFA) in start-up period is attributed to the heating of the feedback circuit and coil. Compared to the drift compensation by temperature model which is built by statical rule, the gain stabilization of closed-loop channel is an essential and direct method to restrain the drift. In this paper, a high accurate current detection circuit is designed to evaluate the parameters drift and to stabilize the gain of the feedback channel. A stability experiment is conducted to prove the efficiency of the proposed stabilization strategy. The result shows that the stability of output in start-up period improves by 37.6% at most. Therefore, the proposed stabilization strategy can effectively improve the start- up performance of QFA, which could be promoted to other sensors whose performance suffer from the drift of the channel. [ABSTRACT FROM AUTHOR]

The state-dependent Gaussian interference channel (IC) and Z-IC are investigated, in which two receivers are corrupted by the same but differently scaled states. The state sequence is noncausally known at both transmitters, but not known at either receiver. Three interference regimes are studied, i.e., the very strong, strong, and weak regimes. In the very strong regime, the capacity region is characterized under certain channel parameters by designing a cooperative dirty paper coding between the two transmitters to fully cancel the state. In the strong regime, points on the capacity region boundary are characterized under certain channel parameters by designing an achievable scheme based on rate splitting, layered dirty paper coding, and successive state cancellation. In the weak regime, the sum capacity is obtained by independent dirty paper coding at two transmitters. For all the above regimes, the capacity achieves that of the IC/Z-IC without state. Comparison between the state-dependent regular IC and the Z-IC suggests that even with one interference-free link, the Z-IC does not necessarily perform better, because dirty paper coded interference in the regular IC facilitates to cancel the state through the cooperative dirty paper coding between the transmitters. [ABSTRACT FROM AUTHOR]

Cycle time, which is of order of ten weeks for most products in semiconductor wafer fabrication facilities (wafer fabs), must be explicitly considered in production planning models. Cycle times depend nonlinearly on the resource workload in a wafer fab. Different data-driven (DD) production planning formulations are studied in this paper. Such formulations are based on a set of system states representing the congestion behavior of a wafer fab with work in process (WIP) and resulting output levels. Different WIP-output relations in the DD formulations are investigated. In addition, different methods are proposed to gather representative sets of system states. The DD formulations are compared with the Allocated Clearing Function (ACF) formulation with respect to profit and cost values using simulation models of a scaled-down and a large-sized multi-product wafer fab, respectively. The simulation results show that some DD variants are able to outperform the ACF formulation under several experimental conditions. [ABSTRACT FROM AUTHOR]

This paper proposes a resonant switching cell model to analyze and design the single-ended resonant dc–dc converters. The single-ended zero-voltage switching (ZVS) converters such as the Class E converter are efficient for megahertz switching because they feature low turn-on and turn-off switching losses. Also, they use only a ground-referenced switch, allowing a simple gate drive circuit. In this paper, we investigate the single-ended resonant converter with the small input inductance, whereas the conventional Class E converter has a large input inductance. The main contribution of this paper is to propose the resonant switching cell as an analytic model that simplifies the analysis and the design of the resonant dc–dc converters. Furthermore, this paper presents the design method of the resonant switching cell model for minimizing the resonant current magnitude and conduction loss while the converter maintains ZVS property. The experimental results from a 10-MHz GaN-based prototype demonstrate the feasibility and effectiveness of the analysis and design based on the proposed resonant switching cell model. [ABSTRACT FROM AUTHOR]

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]

This paper deals with stabilization of an ideal transformer model (ITM) circuit, used as an interfacing algorithm for hardware-in-the-loop simulations. The ITM allows for the distribution of simulation model computations over multiple processors or can be used in power hardware-in-the-loop simulations. When specific impedance conditions of the partitioned circuit are not met, this interfacing algorithm becomes unstable. This paper first presents a new theoretical approach for representing the ITM interfacing algorithm that is based on delay differential equations. With a stability analysis of the obtained time-delay system, a stabilization method is proposed, which increases the stability boundaries of the ITM algorithm. Simulation examples, including the scenario of a two-level inverter system, are provided. [ABSTRACT FROM AUTHOR]

This paper presents an empirically grounded model, which links organizational learning to pattern-specific fixed costs in integrated device manufacturing. The approach described in this paper helps fab managers make fundamental strategic decisions concerning product design and product mix by engaging in scenario planning. Four critical aspects of managing pattern-specific fixed cost are analyzed in detail—sensitivity to time, design cost, and production volume; platform designs; process postponement solutions; and design penalties. The model suggests that designers and fabrication facilities must collaborate extensively on the design and realizations of product platforms for state-of-the-art integrated circuit products to remain economically viable. [ABSTRACT FROM AUTHOR]

The latest developments in dc transformer technology are enabling larger and more complex dc power distribution systems. However, the literature is scarce regarding the investigation and quantification of its impact on the dc grid. Therefore, this paper analyses the impact of the dc transformer location on the system’s characteristics to provide enough information to predict the system performances for future dc grids. To determine the critical resonant frequencies of the system, the power converters outer control loop dynamic are included to provide a better representation in frequency domain, and enable its evaluation for the addition of new equipment to the power distribution network. The proposed solution has an expansible methodology, allowing its application in large systems and easy impedance response assessment. Moreover, the proposed solution is independent of the ac grid backup solutions, allowing the dc power distribution network planning to deal only with the dc variables. Finally, theoretical developments are validated using simulations, and the steady-state and impedance identification process is described in detail. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

Over the last 11 years, the field of Memristive Sensors abruptly emerged in literature. The present review paper has the aim to acknowledge such an exciting new field of research as well as to critically review its most significant outcomes. As usual in science and technology, only the concept of a new sensor has been drawn and simulated in some cases, while real demonstrators have been designed, fabricated, and demonstrated in several other cases. Moreover, several new sensing methods have been proposed, all based on memristive conductivity. Again, the new sensing principle has been shown just once in some cases, while several different sensors have been demonstrated by applying a single consolidated method in other cases. Therefore, ultimate aim of this paper is to deeply and exhaustive review the most important steps in such a new field by entering the significant details about the several kinds of sensor, while critically commenting on the key aspects of the proposed ideas and applications. The most important milestones are outlined as appeared along the course of the last decade, by also showing the temporal perspective of this totally new recently emerged field. [ABSTRACT FROM AUTHOR]

When lightning strikes a transmission line tower or shield wires, electromagnetic waves propagate through the tower back and forth, increasing the voltage across insulator strings. This can eventually lead to a back-flashover (BF), which may cause damage to equipment or costly power outages. To calculate the over-voltages and predict the probability of a BF, an accurate model of the tower and its grounding system is needed in electromagnetic transient (EMT) type simulators. There are a number of theoretical models for the equivalent circuit of a transmission tower. However, they either are not accurate enough or they are derived for a certain type of transmission tower, which limits their applicability. Numerical electromagnetic analyses have less simplifications compared to the theoretical solutions and are by far less expensive than field measurements. They also have the flexibility to analyse any type of tower. In this paper, the direct method for the measurement of tower impedance is implemented by NEC4 and applied to a 400-kV double circuit tower with all its details. The process of obtaining the wire network of the tower used in this paper is completely automated and it can be applied to any other type of transmission tower. The results of the numerical simulations are compared to those obtained with existing tower models. The developed model in this paper is capable of considering all the details of the tower and including the finite resistance of the ground and grounding electrodes. [ABSTRACT FROM AUTHOR]

The growth process of silicon single crystal (SSC) is a typical batch production process, which has the characteristics of batch size, variety, complex process, and intensive technology. In order to accurately control the diameter and thermal field temperature of the Czochralski (Cz) SSC batch production process to ensure that the actual production requirements of electronic-grade SSC are met, this paper proposes an iterative learning-based batch process predictive control strategy Model Predictive Control - Iterative Learning Control - Extended State Observer (MPC-ILC-ESO). The control strategy consists of two parts. The time axis is a dual Model Predictive Control (MPC) controller, which is mainly used to deal with disturbance suppression and constraints in the production process of a single batch of SSC. The iterative axis is the Extended State Observer (ESO) based Iterative Learning Control (ILC) control algorithm to deal with uncertainty and disturbance estimation and compensation in the multi-batch production process. The control effects of the time axis and the batch axis are superimposed as the final controlled object input to ensure the crystal diameter and stable thermal field temperature. Finally, the effectiveness of the proposed control strategy is verified based on the data analysis of the semiconductor industry production process. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive investigation of several important error sources for the successive-approximation register (SAR) analog-to-digital converters (ADCs). The error sources that we discuss in this paper include the dynamic comparator offset, the dynamic gain error of digital-to-analog converter (DAC), the capacitor mismatch of capacitive DAC, the incomplete settling of DAC, the undershoot of reference voltage, and the input signal coupling. The integral/differential nonlinearities (INL/DNL) of SAR ADCs that are resulted from these error sources are analyzed and addressed. A diagnostic procedure is presented to identify the possible error sources based on the INL/DNL plots. In addition, design suggestions for overcoming these problems are also offered and recommended in this paper. [ABSTRACT FROM AUTHOR]

The effects of a temporally modulated, distributed cathode in a linear format crossed-field amplifier (CFA) are simulated in VSim and analyzed. A linear format, 150 MHz, low power (100 W), moderate gain (7 dB), meander line CFA is used as the basis for the simulation model. This paper describes simulations with different time-varying distributed cathodes in which electron injection is modulated at the RF both in-phase and out-of-phase with the RF input. At low RF input power, the modulated electron injection dominates the operation. Injecting in-phase with the RF input shows gain increases from 23 dB at 150 mA to 32 dB at 1 A for low cathode modulation power (<0.1 W). The CFA efficiency increased from 2%–4% to 20%–24% using the electron modulation. The simulation shows distinct cylindrically shaped electron bunches as opposed to spokes because of the synchronous injection. These results suggest that for high power magnetrons electron modulation could improve gain. [ABSTRACT FROM AUTHOR]

This paper presents the development of a wake-up receiver (WuRX) at nanowatt power levels for event-driven applications. This paper improves the state of the art, obtaining higher sensitivity than previous work in the 151.8- and 433-bands, low-power operation, and robustness to interference due to an integrated offset compensation algorithm operating without any external calibration. Simultaneous low-power operation and high sensitivity are achieved through a passive detector design based upon a terminal impedance boundary condition-based optimization of the detector dictated by the terminal impedances of the detector. This paper is implemented in a 130-nm CMOS process and obtains −76 dBm at the 151.8-MHz multi-use radio service (MURS) band and −71 dBm at the 433-MHz Industrial, Scientific and Medical (ISM) band with a total dc power draw of just 7.6 nW from 1.0- and 0.6-V supplies. [ABSTRACT FROM AUTHOR]

The quantitative analysis of the iron loss taking magnetic hysteresis behavior into account is essential for the development of high-efficiency electric machines. In a previous paper, a novel magnetic circuit model incorporating a play model, which is one of the phenomenological models of magnetic hysteresis, was proposed. It was clear that the proposed model can calculate the hysteresis loop of a ring core with high speed and high accuracy. However, this method was applied only for the objects with simple shapes. Thus, it is necessary to extend the applicable range for the objects with more complicated shapes. This paper presents a novel reluctance network analysis (RNA) model incorporating the play model and indicates the validity of the proposed RNA model by using a three-phase-laminated-core variable inductor as an object of discussion. [ABSTRACT FROM AUTHOR]

By triggering the switches in sequence and controlling the brick charging voltage independently, a pulsed power system can generate flexible current waveform in the load, which could allow high-accurate magnetic pressure in experimental materials in the study of EOS data and dynamic response of material characterization. Currently, a 1.5-MA driver with 20 independent bricks has been developed, and a programmable 256-brick parallel discharge driver which is able to generate shaped current greater than 6.5 MA is under construction in the China Academy of Engineering Physics. In this paper, for these two multibrick parallel discharge drivers, the method of optimizing the output current waveform of the driver is studied by using the genetic algorithm and the corresponding optimization results of different target current waveforms are obtained. An experimental platform is set up for studying the gas switch breakdown characteristics. The self-breakdown and triggering breakdown experiments of the switch are conducted, and its breakdown characteristics are researched. Meanwhile, the effect of breakdown delay and jitter on the output current waveform is studied by simulation. This paper is of great significance to the actual operation of the multibrick parallel discharge drivers. [ABSTRACT FROM AUTHOR]

In this paper, system properties of a physics-based model of a supercapacitor are computed using a local Lyapunov analysis and the solution of linear matrix inequalities. By considering the model as a Lurie system, bounds are computed for the resistance, capacitance, stored and dissipated energies for a charging profile, model stability, maximum reachable set with an input current impulse and the maximum voltage such that the potential difference across the double layer never exceeds the electrolyte overpotential. The bounds computed in this paper will aid the designers of supercapacitors, as the effect on the system properties caused by changes to the physical parameters can now be estimated. The theoretical results predicted by the analysis are compared against experimental data. [ABSTRACT FROM AUTHOR]

The performance of a communication link can be improved by maximizing the mutual information between the input and output signals. This paper considers this maximization problem in a molecular communication link where both the transmitter and the receiver are molecular circuit. This general optimization is hard to solve. We simplify the problem by limiting to reactions with linear reaction rates and molecular circuits with a limited number of species. We derive an expression of mutual information and use it for numerical maximization. We show that our parameterized transmitter circuit is able to give mutual information that is close to upper bound obtained in our earlier work. [ABSTRACT FROM AUTHOR]

Recent research in the field of 3-D system integration has looked to the use of inductive-coupling links (ICLs) to provide vertical connectivity without incurring the inflated fabrication and testing costs associated with through-silicon vias. For power-efficient ICL design, optimization of the utilized physical inductor geometries is essential, but currently must be performed manually in a process that can take several hours. As a result, the generation of optimized inductor designs poses a significant challenge. In this paper, we address this challenge in three main contributions: 1) a novel, nonuniform planar inductor layout that exhibits enhanced performance when compared with conventional uniform inductors; 2) a rapid solver for evaluating inductor layouts; and 3) a high-speed optimization algorithm for determining best performing coil pairs. These three contributions are combined as a CAD tool for optimization of ICLs for 3-D-ICs (COIL-3-D). Results demonstrate that COIL-3-D achieves an average accuracy within 7.8% of finite-element tools consuming a small fraction of the time ($1.5\times 10^{-3}$ %), significantly ameliorating the design of ICL-based 3-D-ICs. We also demonstrate that using COIL-3-D to optimize ICL inductor layouts can yield significant performance (up to 41.5% bandwidth improvement) and power (up to 8.1% power improvement) benefits, when compared with layouts used in prior ICL implementations. For these reasons, this paper unlocks new potential for low-cost, power-efficient 3-D integration using ICLs. [ABSTRACT FROM AUTHOR]

This paper presents a new approach for compact modeling of aging and radiation effects for MOS transistors including process variation and environmental influences. This approach can be used in common design flows for analog integrated circuits. Moreover, the aging behavior of whole circuits can be analyzed without the need for abstractions or extrapolation. Only one common physically motivated transistor parameter is used in order to model radiation and degradation mechanisms. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) with low switching current, high thermal stability, and small device size are strongly preferred for low-power, high-reliability, and high-density spintronic memory and logic applications. The research of MTJs from shape in-plane magnetic anisotropy to interfacial perpendicular magnetic anisotropy (i-PMA) has successfully paved the way down to 20-nm scale, below which, however, the i-PMA approach reaches a physical limit in sustaining sufficient thermal stability while achieving low-power spin transfer torque switching. Recently, studies have been reported a new approach to pave the way toward sub-10-nm MTJs satisfying the requirements by revisiting shape perpendicular magnetic anisotropy (s-PMA). In this paper, we present a compact model of the sub-10-nm s-PMA MTJ device, which captures both the static and dynamic physical behaviors. This model is SPICE-compatible for hybrid MTJ/CMOS circuit designs. This paper is expected to push forward the development of sub-10-nm-scale MTJ-based spintronic memory and logic circuits. [ABSTRACT FROM AUTHOR]

In this paper, surrogate modeling techniques are applied for passive component modeling. These techniques are exploited to develop and compare two alternative strategies for automated radio-frequency circuit design. The first one is a traditional approach where passive components are designed during the optimization stage. The second one, inspired on bottom-up circuit design methodologies, builds passive component Pareto-optimal fronts (POFs) prior to any circuit optimization. Afterward, these POFs are used as an optimized library from where the passive components are selected. This paper exploits the advantages of evolutionary computation algorithms in order to efficiently explore the circuit design space, and the accuracy and efficiency of surrogate models to model passive components. [ABSTRACT FROM AUTHOR]

Stacks of 2-D materials, known as van der Waals (vdW) heterostructures, have gained vast attention due to their interesting electrical and optoelectronic properties. This paper presents an intuitive circuit model for the out-of-plane electrostatics of a vdW heterostructure composed of an arbitrary number of layers of 2-D semiconductors, graphene, or metal. We explain the mapping between the out-of-plane energy band diagram and the elements of the equivalent circuit. Although the direct solution of the circuit model for an n-layer structure is not possible due to the variable, nonlinear quantum capacitance of each layer, this paper uses the intuition gained from the energy band picture to provide an efficient solution in terms of a single variable. Our method employs Fermi–Dirac statistics while properly modeling the finite density of states (DOS) of 2-D semiconductors and graphene. The approach circumvents difficulties that arise in commercial TCAD tools, such as the proper handling of the 2-D DOS and the simulation boundary conditions when the structure terminates with a nonmetallic material. Based on this methodology, we have developed 2dmatstacks, an open-source tool freely available on nanohub.org. Overall, this paper equips researchers to analyze, understand, and predict experimental results in complicated vdW stacks. [ABSTRACT FROM AUTHOR]

Electromagnetic pulse forming (EMPF) is an attractive manufacturing method using pulse power techniques. Temperature rise of the work piece is usually neglected in previous studies because the forming process is regarded as a cold process. Nevertheless, the temperature rise (if not high) also has influence on the forming process. It is important to study the temperature rise for exploring the related law in the process of EMPF. In this paper, the thermal effect in the process of EMPF, caused by the joule heating generated by the high current and the plastic work produced by the plastic deformation of the work piece in the forming process, is discussed though simulations and experiments. A finite-element simulation coupled with the electromagnetic field, plastic mechanics, deformed geometry, heat transfer, and thermal expansion based on COMSOL multiphysics is established to show the detailed thermal effect in this process. The relationship between parameters of work piece and the thermal effect has been analyzed by comparing different materials and thicknesses of work pieces. The simulation results show that the temperature of work piece has changed because of the thermal effect. A high-current pulse generator has been developed for the experiment of EMPF to verify the results of simulations. This paper describes the forming experiments of different materials and thicknesses. And the experimental results verify that the materials and thickness of work piece affect thermal effect during the process of EMPF. Compared with the Joule heating, the plastic work is the main cause of the thermal effect. Moreover, the thermal expansion caused by temperature rise could affect the forming results and material property. [ABSTRACT FROM AUTHOR]

Isentropic compression experiments (ICEs) are an important method to study the dynamic characteristics of materials at pressures, temperatures, and stress or strain rate not attainable in conventional shock experiments. Yet it makes high demands toward the precise current pulse tailoring capability of the source. The China Academy of Engineering Physics is now developing a 20-brick parallel discharge driver and a 256-brick parallel discharge driver (CQ-7) to improve the performance and flexibility of compact magnetic compression devices. The load current of ICEs is tailored by optimizing the switch trigger sequence and the brick charging voltage. This paper establishes the equivalent circuit model of the 20-brick parallel discharge driver, taking the distributed inductance, resistance, and capacitance of transmission plates into account based on the partial-element equivalent circuit method. Besides, the equivalent circuit model of discharge brick based on the switch arc resistance model is also established to study the influence of key structural parameters on the output current. Furthermore, by comparing the simulation and experimental results of simultaneous discharge of 20-brick driver, the accuracy of simulation model is confirmed. This paper is of great significance to the design and optimization of multibrick parallel discharge drivers. [ABSTRACT FROM AUTHOR]

This paper deals with the test of a reconfigurable hardware system (RHS). The latter is a hardware device that allows to change the hardware resources at runtime in order to modify the system functions and therefore to dynamically adapt the system to its environment. The increasing functional complexity of embedded systems and the transition to the RHS make the hardware testing a challenging task, especially under the confine of providing a high quality with a low cost. Considering the fact that the hardware test represents a key cost factor in a production process, an optimal test strategy can be advantageous in the competitive industrial market. Accordingly, this paper introduces a new methodology for an efficient hardware test of RHS. For an RHS, the number of stuck-at faults can be very large, which leads to a significant slowdown in the testing process. Because of the redundancy of faults between the different circuits composing an RHS, the proposed methodology aims at minimizing the number of faults using the inter-circuits relationships and consequently at providing an optimal fault set that can be effectively used for testing. Efficient techniques for test generation and test set validation are proposed to provide the test patterns for faults reduced by inter-circuits fault collapsing. The application of the generated test patterns is typically sufficient to provide an overall fault coverage. The proposed methodology is implemented in a new visual environment named TnTest. An experimental study confirms and validates the expected findings. Note to Practitioners—This paper addresses possible challenges for future generations of adaptive embedded systems. It proposes an original methodology for an efficient reconfigurable hardware system (RHS) hardware test. The main objective is to significantly reduce time and cost needed for the testing process. For an RHS, the number of stuck-at faults can be very large, which can cause a major slowdown in the hardware test. Based on the inter-circuits relations existing between the different circuits composing an RHS, the proposed methodology decreases considerably not only the number of the faults but also the test patterns needed for testing. The application of the generated test patterns is typically sufficient to provide an overall fault coverage. The proposed methodology is implemented in a new visual software environment named TnTest, which is capable of providing the smallest fault set as well as the efficient test set that can be effectively used for testing. This environment can be applied to test any embedded device that can be deployed in any new application based on flexible technologies. It can also be useful in manufacturing industries for a required improvement of the production process in relation to time and cost. [ABSTRACT FROM AUTHOR]