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In this paper, we report the characterization and modeling of multi-finger gate all around (GAA) nanowire (NW) FETs (NWFETs) from dc to 14 GHz. The self-heating effect (SHE) in NWFETs is investigated experimentally using the small-signal output conductance (${g}_{{\text {ds}}}$) technique. The frequency-dependent complex thermal impedance, ${Z}_{{\text {th}}}({f})$ , is extracted by fitting an ${n}$ th-order thermal network with the experimental data. We show that the temperature rise $\Delta {T}$ (=85 °C) due to SHE is significant in short-channel silicon on insulator (SOI) NWFETs. Finally, we have evaluated the RF figure of merit (FOM) for these NWFETs as ${f}_{T}$ (=70 GHz) and ${f}_{\text {max}}$ (=80 GHz). We also report the RF performance metric sensitivity on temperature, $\partial {f}_{\text {max}}/\partial {T}_{{\text {amb}}}$ ($\approx -0.104$ GHz/K). The reported BSIM-CMG compact model shows a good correlation with the measurement data. [ABSTRACT FROM AUTHOR]

In this paper, an array wire-to-wire surface dielectric barrier discharge (DBD) structure is used to generate large-scale plasma by bipolar nanosecond pulse power in atmospheric air. The quantity of electrodes can be adjusted from 1 to 10 for varying discharge area. The applied voltage and discharge current are measured, the discharge images are captured, and optical emission spectra (OES) are collected. The discharge power, discharge area, and OES intensity for a single group of/and whole structure are calculated. The vibrational and rotational temperatures are simulated by the OES of N2 (C-B, $\Delta \nu =-2$), and the effects of the quantity of electrodes on discharge current, discharge power, discharge area, OES intensity, and vibrational and rotational temperatures are investigated. The results show that the discharge current has two main peaks during single applied pulse voltage, and decays in a fluctuant type. As the quantity of electrodes increases, the peak value of discharge current increases and the decaying time from peak value to zero around becomes longer. The discharge power, discharge area, and OES intensity have increasing tendencies, and those of the single group of wires decrease. In addition, when the quantity of electrodes increases, the vibrational temperature increases first and then decreases, and the rotational temperature varies in a fluctuant type. [ABSTRACT FROM AUTHOR]

This paper presents a sensor front end for air pressure sensor, relative humidity (RH) sensor, and accelerometer in a standard CMOS process, equipped with a wide input range high-resolution capacitance-to-digital converter (CDC). For air pressure and RH, interdigitated top metals in air and polyimide are exploited, respectively, which exhibit the change in dielectric constant. For acceleration, separation among three bondwires is exploited. These sensing transducers induce capacitance change that is quantized by a CDC based on a dual-quantization architecture that employs a single-bit first-order $\Delta \Sigma $ modulator and a 7-bit SAR analog-to-digital converter (ADC). Implemented in 0.18- $\mu \text{m}$ CMOS, the air pressure sensor, RH sensor, and accelerometer achieve a noise floor of 0.14 psi/ $\sqrt {\textrm {Hz}}$ , 0.001 %RH/ $\sqrt {\textrm {Hz}}$ , and 4.6 mg/ $\sqrt {\textrm {Hz}}$ , respectively. The CDC achieves a resolution of 864 aF (minimum resolution of 116 aF) when the sensing capacitance is 10 pF and consumes $3~\mu \text{W}$ from 1.1-V supply. [ABSTRACT FROM AUTHOR]

In previous work, the performance of a compact and cost-effective point-of-care (PoC) device based on the increase relative optical power (IROP) methodology is reported and it is determined the enhancement in comparison with standard high-resolution spectrometry in terms of limit of detection. This paper describes a new label-free IROP-based biomedical device capable of working with low concentration of reagents and low sample volume per measurement in order to be used for screening different steps necessary in immunoassay optimization. This new approach significantly improves the sensing performance in terms of read-out signal ($\Delta $ IROP) per nanometer of biofilm in comparison with our previous work. This improvement is achieved due to the implementation of a laser as light source of the optical read-out system and the redesign of Fabry–Perot transducers by optimizing their reflectivity response and reducing their sensing area. For demonstrating the screening capability of this new PoC device in several immunoassays steps and methodologies, a C-reactive protein detection assay was carried out as a potential application and assay model. It is remarkable that only $10~\mu \text{L}$ of sample was used per measurement. This label-free IROP-based device complies an easy-to-use and cost-effective tool for immunoassays optimization in terms of performance, reagents cost, and measuring time. [ABSTRACT FROM AUTHOR]

For decades, power system stabilizers paired with high initial response automatic voltage regulators have served as an effective means of meeting sometimes conflicting system stability requirements. Driven primarily by increases in power electronically-coupled generation and load, the dynamics of large-scale power systems are rapidly changing. Electric grids are losing inertia and traditional sources of voltage support and oscillation damping. The system load is becoming stiffer with respect to changes in voltage. In parallel, advancements in wide-area measurement technology have made it possible to implement control strategies that act on information transmitted over long distances in nearly real time. In this paper, we present a power system stabilizer architecture that can be viewed as a generalization of the standard $\Delta \omega$ -type stabilizer. The control strategy utilizes a real-time estimate of the center-of-inertia speed derived from wide-area measurements. This approach creates a flexible set of trade-offs between transient and small-signal response, making synchronous generators better able to adapt to changes in system dynamics. The phenomena of interest are examined using a two-area test case and a reduced-order model of the North American Western Interconnection. To validate the key findings under realistic conditions, we employ a state-of-the-art co-simulation platform to combine high-fidelity power system and communication network models. The benefits of the proposed control strategy are retained even under pessimistic assumptions of communication network performance. [ABSTRACT FROM AUTHOR]

Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel mechanism for the Vth shift of amorphous-indium gallium zinc oxide (a-IGZO) thin film transistors under negative bias illumination stress (NBIS). Three kinds of IGZO TFTs with different gate dielectrics and valence band offsets (VBO) were used in this experiment. Gate dielectric materials used were Al2O3, HfO2 and SiO2. Initial parameters, VBO, and state density (DOS) for each TFT were extracted. After NBIS, the Vth shift was greatest at −3.82 V using a TFT with an HfO2 gate dielectric. VBO was the lowest at 0.38 eV using a TFT with an HfO2 gate dielectric. The smaller the VBO, the larger the generated Vth shift. DOS measurements confirmed the interfacial properties between the gate dielectric and IGZO, and the highest DOS resulted from the interface between Al2O3 and IGZO. Through the experimental results, the correlation between VBO and Δ Vth after NBIS was investigated. We found that the main cause of Vth shift in NBIS is injection of photoinduced hole carriers that cross the VBO by tunneling from IGZO channel to gate oxide. [ABSTRACT FROM AUTHOR]

This paper analyzes the effect of high current under illumination stress (HCIS) in self-aligned amorphous indium gallium zinc oxide transistors with Al2O3 as high- $\kappa $ gate dielectric. A negative parallel threshold voltage $({V}_{T}$) shift with the appearance of hysteresis $(\Delta {V}_{{hys}})$ is observed after HCIS. In contrast to the double ionized oxygen vacancy ($\text{V}_{\text O}^{\text 2+}$) theory, a peroxide donor theory based on ${ab~ initio}$ calculations is proposed to explain the degradation. Several methods are carried out to support the mechanism, including $\Delta {V}_{{hys}}$ generation, stress recovery behavior and capacitance-voltage ${(C-V)}$ measurements. A linear dependence between initial ${V}_{T}$ and negative ${V}_{T}$ shift is observed that further supports the peroxide theory. This work highlights the importance of evaluating the HCIS for oxide base semiconductor devices. [ABSTRACT FROM AUTHOR]

In this paper, the impingement cooling performance on pin-fin heat sinks is experimentally and numerically investigated with different outlet arrangements and pin-fin layouts. Compared with one-way opening arrangement, results show that the two-way opening arrangement can offer a much lower pressure loss ($\Delta p$) due to shorter flow distance of airflow from outer jets. Meanwhile, it is surprising that the two-way opening arrangement still offers appreciable improvements on effective heat transfer coefficient ($h_{\mathrm {eff}}$). This is because the fountain may shift toward the outer jets more rapidly with one-way opening arrangement. Yet the implementation of staggered pin-fin layout has minor improvement on $h_{\mathrm {eff}}$. However, $\Delta p$ can be obviously reduced by 11.1% due to the more effective spreading of impinging airflow in radial direction. The $h_{\mathrm {eff}}$ value can be further increased by 8.8% when a smaller jet-to-target distance is applied. With priority consideration of hot spots in electronic cooling, the nonuniformity of local Nusselt number (${S}$) is further studied through the computational fluid dynamics (CFD) method. ${S}$ approaches 18.5% when the airflow directly impinges on a flat surface with optimized jet array. Implementing pin-fin heat sinks can reduce the nonuniformity of Nusselt number distribution to fall below 8.0%. The nonuniformity of local Nusselt number can be further reduced to 1.8% by applying four-way opening arrangement and larger central jet at the same time. [ABSTRACT FROM AUTHOR]

In this paper, we report measurements in Colorado and Utah of the disturbed very-low-frequency (VLF) signals from the NML Navy transmitter in North Dakota during the 2017 solar eclipse. Using an occultation mask of solar fluxes together with detailed chemistry and VLF propagation simulations, we quantify the D-region response to the eclipse, in terms of electron density variation, as well as the expected signatures of VLF transmitter signals. The VLF measurements, including an anomalous amplitude enhancement recorded in UT, can be quantitatively explained using the Wait and Spies ionospheric profile with a sharpness parameter of $\beta = 0.3$ km−1 above ~55 km and an increase in the D-region ionosphere height of $\Delta h' \simeq 8$ km. This sharpness parameter is consistent with previously reported rocket measurements and first-principles calculations. The best-fit results suggest a reduction of D-region electron density by ~90% during the eclipse in the D-region, implying an occultation of Lyman- $\alpha $ by nearly 99%. This finding agrees with detailed calculations of time-dependent obscuration factors utilizing the He 30.4-nm images from Solar Dynamics Observatory as a proxy for the distribution of Lyman- $\alpha $ across the solar disk and limb. Moreover, the present results show that subionospheric VLF propagation is sensitive to the sharpness parameter of the electron density profile in the D-region. Previously reported first-principles simulations have shown that the sharpness parameter is mostly controlled by the background concentration of minor neutral species. Thus, the VLF technique can be likely used to remotely sense these neutral species at and below the effective reflection altitudes of VLF waves. [ABSTRACT FROM AUTHOR]

In this brief, a 300-mV, auto shutdown comparator based on a novel clock gating network is proposed. The proposed auto shutdown comparator is further employed to realize a compact, ultralow power continuous-time $\Delta \Sigma $ modulator (CTDSM) with a 300-mV supply voltage for multichannel sensing and biomedical applications. The design was fabricated in standard mixed-mode 180-nm CMOS process. Measurement results show that the CTDSM achieves a peak SNDR of 54.81 dB and DR of 57.4 dB while consuming a core power of $1.76~\mu \text{W}$ at 300-mV supply voltage without the clock-gated comparator. With the clock-gated auto shutdown comparator, the CTDSM consumes a core power of only 220 nW thereby providing an eight times power saving. Moreover, the fabricated CTDSM occupies an extremely small area of 0.0464 mm2 with an energy efficiency of 24.5 fJ/conv making it the most compact and energy-efficient CTDSM reported till date among the moderate resolution CTDSMs. Furthermore, by increasing the supply voltage to 400 mV, the CTDSM features a peak SNDR of 58.56 dB and DR of 64.1 dB while consuming a core power of 410 nW and 29.61 fJ/conv. [ABSTRACT FROM AUTHOR]

This article describes a new digital transmitter architecture that automatically corrects static and dynamic nonlinearities with no need for digital predistortion or adaptation. We draw upon the Newton–Raphson method of solving equations and show that it leads to $\Delta \Sigma $ modulation as a special case and to a compact, efficient transmitter in the general case. A complete transmitter realized in 28-nm CMOS technology achieves an overall efficiency of 50% while delivering +24 dBm with an adjacent channel power ratio of −35.4 dB and a receive-band noise of −150 dBc/Hz. [ABSTRACT FROM AUTHOR]

A spread-spectrum clock generator is proposed based on an in-band phase modulation. In a charge-pump phase-locked loop configuration, the input phase modulation signal is applied to the proposed charge-based discrete-time loop filter. The phase difference between the input phase modulation signal and the output clock feedback phase is sampled and applied to the control voltage of an oscillator. The loop gain of the clock generator pushes the output clock phase to accurately trace the input phase modulation signal. This article achieves 3.2% spread-spectrum modulation range and 26.51-dB spread-spectrum attenuation at 352-MHz output frequency using a 2-MHz reference frequency. The in-band modulation improves a design sensitivity, and a 298-ppm modulation range error is measured with over 140% $K_{\mathrm{ VCO}}$ perturbations. This spread-spectrum clock generator is implemented in a 0.18- $\mu \text{m}$ CMOS, and achieves 951-fsrms period jitter while consuming 9.98 mW from a 1.8-V power supply. [ABSTRACT FROM AUTHOR]

A dual-loop eight-channel electrocardiogram (ECG) recording system with the fast settling mode is proposed for wireless real-time 12-lead ECG applications. It employs the frequency division multiplexing (FDM) technique to achieve multi-channel IA (MCIA). The FDM technique allows using smaller input capacitor and sharing of programmable gain amplifier (PGA), buffer, and ADC to achieve smaller area. To suppress the dc offset of bio-signal with faster settling, dual dc servo loops are proposed. The main loop employs the least-mean-square (LMS) algorithm in the digital domain to extract the dc offsets in different frequency channels. An auxiliary fast settling loop (FSL) in the analog domain can be enabled to shorten the settling time from 14 s down to only 0.6 s. A 16-bit $\Sigma \Delta $ ADC, including the decimation filter, is adopted to achieve high resolution and avoid using high Q anti-aliasing filter in the analog domain. The MCIA achieves 112.5-dB common mode rejection ratio (CMRR), 113.0-dB power supply rejection ratio (PSRR), and 1.44- $\mu ~V_{\mathbf {rms}}$ noise performance. The MCIA occupies only 0.3 mm2 and consumes 60 $\mu \text{W}$ for eight channels. The whole ECG recording system was implemented in 130-nm CMOS technology. [ABSTRACT FROM AUTHOR]

We investigated the total ionizing dose (TID) influence on the single-event multiple-cell upsets (MCUs) in 65-nm 6-T static random-access memory and found that MCU sensitivity of the device is enhanced by TID. MCU caused by particle strike in pMOSFET (p-hits) or nMOSFET (n-hits) is distinguished by the MCU pattern. Analysis of MCU pattern shows that both p-hits MCU and n-hits MCU are enhanced by TID, and they have different mechanisms. Enhancement of n-hits MCU is due to the positive threshold voltage shift ($\Delta V$ th) of the pull-up pMOSFET, while p-hits MCU is strengthened by the increase in the equivalent resistance of p-well contacts caused by oxide-trapped charges (Not) trapped in the shallow trench isolation. [ABSTRACT FROM AUTHOR]

Wireless power transfer (WPT) is an enabling technology for electric vehicles (EV), as it eliminates driver intervention during charging. Major challenges to the adoption of WPT systems include coil misalignment and large air-gap WPT, both of which degrade the transfer efficiency. To address these issues, this article presents a compact WPT charger for the rear of an EV, capable of correcting lateral misalignment $\Delta$ x using two integrated electromagnetic coils. The air-gap $\Delta$ y is reduced due to the rear placement of the charging pads. The variation in $\Delta$ y, however, increases due to vehicle parking accuracy, which impacts the operation of the electromagnetic coils. This article proposes a closed-loop three-stage position-correcting control algorithm capable of detecting the impedance and resonant frequency of the system, which, in conjunction with the electromagnetic coils, results in improved vehicle alignment. The experimental prototype achieves a peak dc–dc efficiency of 90.1% at 5 kW WPT. With $\Delta$ y = 50 mm, the electromagnetic coils laterally align the pads within 1.75 s and correct $\Delta$ x as large as 240 mm. The position-correcting control was successfully demonstrated in four parking scenarios with the charging pads being corrected to within a 10-mm radius of perfect alignment. [ABSTRACT FROM AUTHOR]

The additional microwave radiation from underground rock mass (lithosphere) that is caused by tectonic activity and alternating crustal stress has been shown to be a detectable electromagnetic signal via satellite remote sensing. However, the emission of microwave radiation produced inside the lithosphere will be affected by its overburden matter, such as sand, soil, water, and vegetation, and this effect is unknown. In this article, we use a C-band microwave radiometer to detect the variations in the microwave brightness temperature ($T_{B}$) of rock samples in the process of axial loading. For the rock samples, the surface was bare and covered with dry sand or humid sand. The experimental detection illustrates that the dry sand unexpectedly allows more stress-associated additional radiation ($\Delta T_{B}$) to be received by the radiometer, while humid sand shows significant extinction of $\Delta T_{B}$. Both the radiative transfer theory and the stress-activated positive hole hypothesis are applied to interpret the mechanisms of the effect of dry and humid sand layers on $\Delta T_{B}$. The outflow of stress-activated positive holes is from inside the loaded rock, and hence their accumulation beneath the surface of the sand layer is expected to reduce the local dielectric permittivity of sand, thereby making the detected $\Delta T_{B}$ by the microwave radiometer to be larger than that extrapolated theoretically in accordance with radiative transfer theory. This article is valuable for understanding the diverse $T_{B}$ anomalies that have been observed prior to tectonic earthquakes, and it facilitates the evaluation of the potential application of $\Delta T_{B}$ to seismic monitoring and earthquake prediction. [ABSTRACT FROM AUTHOR]

The proposed fully integrated digital-intensive system on chip (SoC) allows dual-mode protocols of Bluetooth low energy (BLE) 5.0 and IEEE802.15.4 with extended-range wireless connectivity and ad hoc mesh networks for Internet-of-Things (IoT) systems in wireless sensor networks. The SoC fully integrates a dc–dc converter, LDOs, a digitally controlled crystal oscillator (DCXO), a PHY, a microcontroller (MCU), a security engine, an SRAM, and an eFlash memory. A triple-supply configuration and low-voltage circuit design enable the SoC to be applied for a wide range of battery-powered systems energy-efficiently and to extend battery lifetime. The TRX employs a low insertion-loss on-die TRX switch with impedance matching circuits, a pseudodifferential current-mode class-D PA with HD2 calibration, a low-IF RX architecture with fast AGC algorithm and complex CT- $\Delta \Sigma $ ADCs, and a low-power all-digital phase-locked loop (ADPLL) with fast settling injection LDOs and an LMS-based two-point direct frequency modulation structure. The TRX implemented in a 28-nm CMOS process achieves an output power of +10 dBm with a calibrated HD2 of −63 dBc while consuming 45 mW and sensitivities of −98 dBm in 2-Mb/s BLE and −102 dBm in 256-kb/s IEEE802.15.4 at ${10}^{-3}$ BER while consuming 6 mW. [ABSTRACT FROM AUTHOR]

A digital low-dropout (DLDO) regulator using p-type MOS (PMOS) and n-type MOS (NMOS) switches is proposed to achieve a sub-fs speed figure-of-merit (FoM) by reducing the total capacitance ($C_{\mathrm {TOT}}$) and accomplishing a comparable output voltage droop ($\Delta V_{\mathrm {OUT}}$) during a load transition. The proposed DLDO uses the segmented PMOS switches to fully turn on the NMOS array, which strengthens the intrinsic NMOS loop and maintains the undershoot and overshoot voltages of 88 and 42 mV, respectively, during an 88.4-mA load transition. In addition, with the aid of the proposed voltage doubler (VD)-based periodically refreshed level shifter (PRLS), the total capacitance of DLDO to drive NMOS array is reduced to 7.2 pF, which is 3.3 $\times $ smaller than that of previous work, extending the input voltage ($V_{\mathrm {IN}}$) and load current ($I_{\mathrm {LOAD}}$) ranges up to 0.9 V and 140 mA, respectively. The proposed DLDO is fabricated using a 28-nm CMOS process and achieves a 0.12-fs speed FoM that is 42.5 $\times $ smaller than the state-of-the-art designs. [ABSTRACT FROM AUTHOR]

Voltage-controlled oscillator (VCO)-based continuous-time $\Delta \Sigma $ modulators (CTDSMs) are deemed attractive for deep-scaled process. However, to realize high-order noise shaping, existing works still employ operational transconductance amplifiers (OTAs), which limits the benefits brought by the VCO. This article presents an OTA-less second-order VCO-based CTDSM featuring a hybrid passive-VCO architecture. It exploits the gain-efficient and scaling-friendly nature of the VCO integrator, enabling the use of a fully passive loop filter to increase the order with minimum power. The proposed architecture is realized in a low-cost, low-noise cascaded-integrator feedback structure that makes use of the parasitic effect of the VCO as an inherent passive stage. Fabricated in 40-nm CMOS, the prototype occupies 0.028 mm2 of active area and consumes 590 $\mu \text{W}$ when sampling at 330 MHz. The CTDSM achieved peak Walden figure of merits of 22 fJ/step with 68.7-dB signal to noise and distortion ratio (SNDR) over 6-MHz bandwidth. [ABSTRACT FROM AUTHOR]

We report the pulse dependent threshold voltage (${V} _{t}$) variation of the Ovonic Threshold Switch (OTS) and its effect on the read window margin (RWM) in Cross-Point Memory (XPM). We found that OTS ${V} _{t}$ varies by the height and width of the write-current pulse. The varied ${V} _{t}$ is persistently maintained even after 2E4 cycling of the write pulse, which means that the phenomenon is not a temporary one, but a type of memory effect in OTS itself. Therefore, it would affect the overall ${V} _{t}$ window ($\Delta {V}_{t}$) of XPM by changing the Set ${V} _{t}$ (${V} _{t\_{}{\text {Set}}}$) and Reset ${V} _{t}$ (${V} _{t\_{}{\text {Reset}}}$) when combined with either phase-change memory (PCM) or resistive memory (RM). High-resolution transmission electron microscopy (HRTEM) and fast Fourier transform (FFT) images have proved that this phenomenon is not caused by the phase change of the OTS. Instead, a sub-threshold analysis extracted from the Poole-Frenkel model suggests that the phenomenon is associated with the variation of the amorphous network either by changes in the atomic bonding configuration or trap density. [ABSTRACT FROM AUTHOR]

This article presents a space–time averaging technique that can realize instantaneous fractional frequency division, and thus, can significantly reduce the quantization error in a fractional- $N$ phase-locked loop (PLL). Spatial averaging can be achieved by using an array of dividers running in parallel. Their different division ratios are generated by using a fractional $\Delta \Sigma $ modulator (DSM) and a dynamic element matching (DEM) block. To reduce the divider power, this article also proposes a way to achieve spatial averaging using only one divider and phase selection. A prototype 2.4-GHz fractional- $N$ PLL is implemented in a 40-nm CMOS process. Measurement results show that the proposed technique reduces the phase noise by 10 and 21 dB at the 1- and 10-MHz offset, respectively, leading to a reduction of the integrated rms jitter from 9.55 to 2.26 ps. [ABSTRACT FROM AUTHOR]

Front and back ends of line (FEOL and BEOL) self-heating and mutual heating are important barriers to a sustained increase in processor speed and density. In this context, the severity of transient Joule heating in scaled interconnects under a variety of operating conditions (e.g., frequency and duty cycle) is not fully understood. Here we introduce the closed-form analytical transient Joule heating model to calculate the time-dependent temperature rise of an interconnect ($\Delta {T}_{\textsf {Int}}({t})$) located at an arbitrary metal level within an integrated circuit (IC). The model is validated by high-fidelity finite element method simulations and specially designed test structures. Remarkably, the model predicts ${I}_{\textsf {Max}}$ (the interconnect-specific current for a certain degree of $\Delta {T}_{\textsf {Int}}$) within 20%–25% for an arbitrary duty cycle. Therefore, our model can be used to accurately predict temperature-accelerated interconnect reliability issues of a modern IC. [ABSTRACT FROM AUTHOR]

Compact polarimetry is a dual-polarization hybrid imaging mode and provides partially backscatter characteristics of scatterers. The compact polarimetric (CP) synthetic aperture radar (SAR) measures the combinations of fully polarimetric (FP) scattering coefficients, which is dependent on the transmit-wave polarization state. The backscattered wave is fully described by a 2-D complex scattering vector, in which the dual-channel polarization ratio represents the vector nature for describing target polarimetric properties. However, due to the dependence of CP measurements on the transmit wave, the complex channel ratio is explained differently for the same scatterers under different observation modes, e.g., the channel ratio ρ = ± j under the left circular mode and ρ = ±1 under the linear π/4 mode for the canonical trihedral and dihedral scatterers. The explanation diversity is inconvenient for the use of CP data, resulting in nonunified target decomposition algorithms. In this study, first, we propose a new formalism method for the general CP SAR mode, such that all CP mode observables are described based on the same standard for target scattering characterization. This provides potential for developing unified CP decomposition algorithms. Then, based on this formalism, a polarization ratio-based scattering characterization method is proposed, which is mathematically equal to the FP ΔαB/αB method but without any scattering assumption. Theoretical analyses and discussions are provided. Experiments show that the proposed method is efficient for compact polarimetric scattering interpretation. [ABSTRACT FROM AUTHOR]