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We show a new Ge channel ion implantation scheme for realization of low-V TH pFET, which enables ∼500mV V TH lowering with no T inv , GIDL and NBTI degradations. We also reveal the physical origin of the large V TH modulation. Based on experimental findings, we propose simplified photo-resist masked dual low-V TH CMOS flow and demonstrate low-V TH pFET/nFET operations.

A new technique to enhance the metal segregation at NiSi/Si interface for reducing contact resistance in source/drain electrodes is proposed. It is demonstrated that metal segregation at the junction of pre-amorphized NiSi/Si using ion-implantation leads to reduction of Schottky barrier height by > 0.2 eV. This modulation width is far beyond the previous metal segregation technique [1] and allows 90% reduction of contact resistance in source/drain junctions.

This paper studies the Schottky barrier height (SBH) modulation effect induced by dipoles, which several types of impurity atoms generate at the nickel silicide (NiSi)/silicon (Si) interface, through both first-principles calculations and experimental methods. Based on these understandings, we discuss their applicability to the DCS junction, leading to a principle for choosing dopants.

We propose a feasible integration scheme for dual FUSI/HfSiON CMOS with low work function metal pile-up to nMOSFET. A newly developed post phase change process to Ni3Si and composition-dependent diffusivity of Al realize simplified integration of 4.3 eV/4.8 eV. Moreover, direct WF lowering of Pt2Si with metal pile-up realizes 4.3 eV/4.9 eV.

It is demonstrated that Schottky barrier height (PhiB) for NiSi/Si junction can be modulated by interfacial segregation of metals. Thin films of rare earth (RE) metals and platinum (Pt) are deposited on NiSi/Si Schottky diodes and annealed. The metals diffuse into NiSi and segregate at NiSi/Si interface, which leads to PhiB modulation by 0.1 eV. Similar technique can be applied to PtSi/Si junction as well for advanced dual silicide process.

The paper demonstrates large effective work function (Phieff) modulation towards Si band-edges based on physical and chemical nature of interfacial impurities at Ni-FUSI/SiON and HfSiON interfaces. The authors clarify the influence of Ni-silicide phase on the Phieff modulation with dopant segregation. Phieff of 4.14 eV is obtained with a combination of phosphorous ion implantation last (IIL) doping and newly developed low temperature NiSi2 formation process. The paper also proposed the realistic Phieff modulation with Al-segregation at Ni-FUSI/HfSiON using IIL-doping process

We propose sub-1Aring-order analysis of gate/insulator interfacial region in scaled-Tinv gate stacks by differentiating their C-V curves. By applying this technique to p+ poly-Si/HfSiON, it is found that gate depletion increases due to both lower poly impurity cone. (Npoly) and huge amount of pinning charge inside the dielectric (Nox). We found ultra-thin SiN cap insertion recovers the degradation in Npoly and Nox, leading to improvement of gate depletion and DeltaVjb. By analyzing FUSI stacks, absence of semiconducting interlayer is verified with sub-1Aring resolution, and it is also found that As segregation outside SiO2 leads to EOT increase as well as work function (WF) modulation in As-doped FUSI/SiO2, whereas As segregation inside HfSiON results in smaller WF change in FUSI/HfSiON

The physical mechanism of work function modulation caused by impurity pileup at Ni-FUSI/SiO(N) interface were investigated. We proposed and verified a new model which can explain the Phim-eff modulation both nMOS (As P and Sb) and pMOS (B). In our model, the position and concentration of impurity at interface determine the direction and the extent of Phim-eff modulation. We have also developed a new method to introduce impurity atoms at the interface after FUSI gate formation, in which the amount of Phim-eff modulation is higher than that for the conventional process

This paper studies the Schottky barrier height (SBH) modulation effect induced by dipoles generation at the nickel silicide (NiSi)/silicon (Si) interface, based on first-principles calculations. Dipole comforting SBH is dramatically reduced to 0.1 eV in 1 nm region around the interface for the case of B atoms substituted for Si atoms. The results suggest that NiSi with appropriate dopant preparation is a plausible electrode material for ultimately small p-MOSFETs

We have investigated the Schottky barrier height of ErSi/sub 1.7/ and suitable formation process to achieve the ideal interface. Atomically flat interface has been achieved by high-temperature (700/spl deg/C) furnace annealing, as well as oxide-block W-cap layer. Under this condition, Schottky barrier height value for electron of lower than 0.4 eV has been obtained. In addition, careful control of silicidation anneal is quite important to achieve ideal ErSi/sub 1.7//Si interface.

A novel approach for achieving high-performance Schottky-source/drain MOSFETs (SBTs: Schottky Barrier Transistors) is proposed. The dopant segregation (DS) technique is employed and significant modulation of Schottky barrier height is demonstrated. The DS-SBT fabricated with the current CoSi/sub 2/ process show competitive drive current and better short-channel-effect immunity compared to the conventional MOSFET. In conclusion the DS-Schottky junction is useful for the source/drain of advanced MOSFETs.

We have investigated the effect of C on Ni silicidation on Si/sub 1-x/C/sub x/ (x=0.004) substrate. The addition of C effectively suppresses the agglomeration of the Ni silicide layers, which results in the low sheet resistance even after annealing at 850/spl deg/C. Pile-up of C at the interface between the Ni silicide layer and the Si/sub 1-x/C/sub x/ film is clearly observed and this is key to improving the silicide morphology and its electrical property as the contact material.