Search

We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 106, a read endurance of $>10^{10}$ read cycles, and a program/erase endurance of 107 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated.

Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon TFTs, fabricated with a spacer technology providing submicron (0.35 mu m) LDD regions, have been analyzed by using two-dimensional numerical simulations. The numerical analysis was used to explain the observed reduced kink effect and short channel effects presented by FSA GOLDD devices, compared to SA devices. The reduction of the kink effect has been attributed to the reduced impact ionization rate, and related to reduced electric fields at the channel/LDD junction. In addition, the role of the LDD dose on the kink effect has been also investigated, clarifying the observed current inflection occurring in the kink effect regime and the LDD dose dependence of the breakdown. Reduced short channel effects were attributed to reduced floating body effects, since drain induced barrier lowering was apparently not affected by the SA GOLDD structure, when compared to SA devices.

By introducing high-K dielectrics and metal gate in our planar self-aligned gate-all-around (GAA) fabrication process, we have successfully fabricated sub-35 nm CMOS devices that exhibit high-performance drive currents (2230/1000 muA/ mum for N/ P at Vd = 1.2 V), low off-state currents (3/5 nA/mum), and excellent subthreshold characteristics. When benchmarked with other published multigate data, the results presented in this paper are proved to be among the best and underline the potential of planar self-aligned GAA devices for the 32 nm technology and below. In particular, it is demonstrated that an optimized supply voltage can bring a significant improvement in circuit time delay and power when using GAA devices.

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO2 as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO2 gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO2/Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO2 /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.

We have developed a self-aligned Lg = 55 nm In0.53Ga0.47As MOSFET incorporating metal-organic chemical vapor deposition regrown n++ In0.53Ga0.47As source and drain regions, which enables a record low on-resistance of 199 Ωμm. The regrowth process includes an InP support layer, which is later removed selectively to the n++ contact layer. This process forms a high-frequency compatible device using a low-complexity fabrication scheme. We report on high-frequency measurements showing fmax of 292 GHz and ft of 244 GHz. These results are accompanied by modeling of the device, which accounts for the frequency response of gate oxide border traps and impact ionization phenomenon found in narrow band gap FETs. The device also shows a high drive current of 2.0 mA/μm and a high extrinsic transconductance of 1.9 mS/μm. These excellent properties are attributed to the use of a gate-last process, which does not include high temperature or dry-etch processes.

We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H/sub 2/ ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of non-lightly doped drain (non-LDD) and lightly-doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation.

We report combining plasma-enhanced atomic layer deposition (PEALD) ZnO thin-film transistors (TFTs) with a gate-self-aligned process to fabricate high-speed circuits. The speed of our previous PEALD circuits (22 ns/stage) was largely limited by the parasitic capacitance between the gate and drain, and a selfaligned-gate process provides higher speed devices and circuits. In this letter, a backside exposure process was used to fabricate gate-self-aligned TFTs with a mobility of 20 cm2/V · s. The seven-stage self-aligned-gate PEALD ZnO TFT ring oscillators had a propagation delay of 9.8 ns/stage at a supply voltage of 18 V. These ring oscillators are similar in performance to the best reported saturated-load oxide-semiconductor circuits but with much longer channel length (> 5× longer).

We propose a large-signal model that can simulate the power-added efficiency of p-pocket self-aligned gate GaAs MESFET's. This model includes a new drain current model and a gate bias-dependent RF output resistance to express the drain conductance and its frequency dispersion at each gate bias. In addition, gate-source and gate-drain capacitances are modeled by functions of two variables of gate and drain biases so as to fit the measured values of ion implanted channels. The simulated power-added efficiency agreed with the measured value with a maximum error of 5%. The intermodulation distortion was also simulated and the maximum difference between the simulated and measured results was reduced to one-fifth of the results simulated by the conventional model. Practical applications were demonstrated by the load-pull simulation and the /spl pi//4 shift QPSK-modulated signal simulation.

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 107 to 1.39 times 107. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFET's, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz /spl pi//4-shift QPSK modulated input.

Characteristics of a 0.2-mum capless InAlAs/InGaAs pseudomorphic high electron mobility transistor (p-HEMT) having a self-aligned gate (SAG) were investigated. The 0.2-mum SAG capless p-HEMT showed a source resistance comparable to that of a conventional recessed p-HEMT having a heavily n-doped In0.53Ga0.47As cap layer primarily due to the SAG and optimized ohmic-metallization processes and excellent characteristics of Gm,max, fT, and fmax of 1.12 S/mm, 185 GHz, and 225 GHz, respectively, even without a heavily doped InGaAs cap layer. The capless device exhibited much better device parameters for digital logic applications including I ON/IOFF and subthreshold slope (1.27times104 and 78 mV/dec) compared with those (5.1times103 and 120 mV/dec) of the conventional recessed device, respectively

We report on 0.1-/spl mu/m gate-length self-aligned Au/WSiN-gate GaAs MESFET technology. The FET we produced using this technology has a planar structure with a selective ion-implanted channel layer and self-aligned n/sup +/- layers. One of the key structural parameters affecting device performance is the offset separating the gate electrode from lightly-doped source and drain n' layers. A 0.1-/spl mu/m gate length is attained by i-line photolithography using an anti-reflection top coat film and SF/sub 6/ gas ECR plasma etching. We demonstrate FET uniformity in a 3-in wafer and excellent high-frequency performance. The standard deviation of the threshold voltages is 0.058 V with an average of about 0 V at a gate length of 0.126 /spl mu/m and the current gain cutoff frequency (f/sub T/) is 168 GHz at a gate length of 0.06 /spl mu/m.

WSiN Schottky diodes on GaAs have been electrically and chemically characterized for atomic silicon and nitrogen; compositions of 0 to 42% and 0 to 28%, respectively. It is found that the main cause for Schottky diode degradation, after high temperature annealing, is the out-diffusion of As from GaAs. For films with atomic nitrogen composition of /spl ges/5%, As outdiffusion is eliminated as long as the atomic Si composition is /spl les/40%. WN films (5% nitrogen) were applied to the fabrication of self-aligned gate lightly doped drain MESFET's with buried P layer. A maximum transconductance, g/sub m/, of 370 mS/mm, f/sub T/ of 33 GHz, and DCFL inverter delay of 29 ps are measured for a 0.5 /spl mu/m gate technology. >

A novel process for fabricating self-aligned gate-overlapped LDD (SAGOLDD) poly-Si thin film transistors (TFTs) was demonstrated. Laser irradiation for dopant activation was performed from the backside of the quartz wafer. The graded LDD structure was naturally formed under the gate edges due to the lateral diffusion of the dopants during the laser activation. In comparison with the conventional laser-processed self-aligned poly-Si TFTs, the SAGOLDD poly-Si TFTs exhibited lower leakage current, suppressed kink effect, and higher reliability. Moreover, the proposed process was simple and very suitable for low-temperature processing.

The design and fabrication of a class of 50-nm self-aligned-gate pseudomorphic AlInAs/GaInAs high electron mobility transistors (HEMTs) with potential for ultra-high-frequency and ultra-low-noise applications are reported. These devices exhibit an extrinsic transconductance of 1740 mS/mm and an extrinsic current-gain cutoff frequency of 340 GHz at room temperature. The small-signal characteristics of a pseudomorphic and a lattice-matched AlInAs/GaInAs HEMT with similar gate length (50 nm) and gate-to-channel separation (17.5 nm) are compared. The former demonstrates a 16% higher transconductance and a 15% higher current-gain cutoff frequency, but exhibits a 38% poorer output conductance. An analysis of the high-field transport properties of ultra-short gate-length AlInAs/GaInAs HEMTs shows that a reduction of gate length from 150 to 50 nm neither enhances nor reduces their average velocity. In contrast, the addition of indium from 53% to 80% improves this parameter by 19%. >

Design and test results are presented for several multiuse GaAs ICs for radar and electronic warfare (EW) applications. The chips described are a redundant switch, a broadband distributed amplifier, a broadband variable-gain amplifier, a 2.5-GHz sample and hold, a 1-GHz analog-to-digital converter, and an L-band buffered prescalar. These ICs, fabricated with the ITT 0.4- mu m-gate MESFET multifunction self-aligned gate (MSAG) process, demonstrate excellent performance. >

A substitutional self-aligned gate MESFET process for the half-micrometer gate GaAs IC that employs techniques of sidewall formation and precise pattern reversal using ECR (electron cyclotron resonance) CVD (chemical vapor deposition) is discussed. A FET with 0.45- mu m gate length showed high performance characteristics, such as a maximum transconductance of 440 mS/mm and a cutoff frequency of 39 GHz. This process has two advantages over conventional substitutional and refractory gate processes. First, it can incorporate an LDD (lightly doped drain) structure. Second, since the photoresist dummy gates are precisely reversed without using reactive ion etching (RIE) at all, the gate length is dependent only on lithography. The process was demonstrated by the preliminary fabrication of a 16 b*16 b multiplier with 50% yield. The process, with high-performance device characteristics, should fine broad applications in both half-micrometer gate level LSIs and analog ICs. >

This article demonstrates full self-aligned inverted-staggered amorphous silicon thin-film transistors (TFT's) fabricated using selective plasma deposition of doped microcrystalline silicon source/drain contacts. Back-side exposure, using the bottom metal gate as the mask, produced the self-aligned contact openings. Selective deposition of the n+ silicon contact layer assures self-aligned ion resistance contacts and eliminates the need for reactive ion etching of the n+ silicon. Complete TFT fabrication requires no critical alignment steps. Transistors have linear mobility between 0.6 and 1.1 cm/sup 2//Vs, threshold voltage of 3.0 V, and sub-threshold slope of 0.35 V/decade. The OFF current is

MBE-grown MESFET wafers were patterned with a novel resistless approach and InAs was selectively grown in the source and drain regions. Photoresist and the associated process steps and chemicals were eliminated by utilizing gallium oxide as the masking material. Metallization for the source, drain and self aligned gate was carried out in one step, also without using any photoresist. Device structures with gate lengths ranging from submicron to 10 /spl mu/m were fabricated.

The authors report on the design and fabrication of a 650-AA self-aligned-gate pseudomorphic Al/sub 0.48/In/sub 0.52/As/Ga/sub 0.2/In/sub 0.8/As high electron mobility transistor (HEMT) with a state-of-the-art current gain cutoff frequency of over 300 GHz. This work clearly demonstrates the potential of sub-0.1- mu m gate-length HEMTs for near-future microwave and millimeter-wave applications. >

The authors report a three-stage pipelined 4500-gate 16*16 complex multiplier with a multiply rate of 500 million products per second, producing a complex product which requires four multiplications and two additions every 8 ns at a power dissipation of 4.0 W. The multiplier uses a modified Booth's algorithm to reduce the number of adders in the multiplier net. The basic building block of the adders and registers is a DCFL NOR gate with a special load structure. The heterostructure active layers were grown by molecular beam epitaxy on 3-in semi-insulating LEC (liquid encapsulated Czochralski) GaAs substrates. The output of bits 1 and 5, operating in the self-test mode, is shown. The circuit was found to perform vector rotations correctly at a clock rate of 560 MHz with a power dissipation of 6.2 W and at 520 MHz with a power dissipation of 4 W. The 520-MHz clock at 4 W corresponds to 96 ps/gate and 0.89 mW/gate because the pipelined stages are limited to 20 gate delays. This performance represents a loaded delay with each gate driving an average fan-out of 2.5 and about 1000 mu m of interconnects at close to minimum spacing. >

A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A 4-b analog-to-digital converter, a 2500-gate 8*8 multiplier/accumulator, and a 4500-gate 16*16 complex multiplier have been demonstrated using enhancement-mode n/sup +/-(Al,Ga)As/MODFETs, superlattice MODFETs, and doped channel heterostructure field-effect transistors (FETs) whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1- mu m gate-length devices, direct-coupled FET logic ring oscillators with realistic circuit structures have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 mu m of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysteresis of less than 1 mV at room temperature. Fully functional 4-b analog-to-digital circuits operating at frequencies up to 2 GHz were obtained. >

The authors fabricated GaAs power FETs and microwave ICs using a novel fully planar, refractory self-aligned gate process. This process uses methods to reduce the gate resistance and output conductance without sacrificing simplicity. Because it is compatible with the use of an optical stepper, the process is suitable for manufacturing use. The C-band RF performance is excellent; the very uniform and reproducible device parameters resulted in a first-iteration 2.5-W C-band power amplifier that met design specifications on the first lot of wafers processed. >

This paper reports fabrication of high-speed GaAs divider IC's implemented using self-aligned gate (SAG) technology. BFL circuits employing SAG D-MESFET's have operated at higher clock speed (4.0 GHz) and have achieved higher yield (> 80 percent) than circuits with comparable threshold voltage and gate-length fabricated using "selective implant" or "recessed gate" technology.

InGaAs junction field-effect transistors (JFETs) are fabricated in metalorganic chemical-vapor-deposition (MOCVD)-grown n-InGaAs and semi-insulating Fe:InP layers on n/sup +/-InP substrate with a P/Be co-implanted p/sup +/ self-aligned gate. The device exhibits a transconductance of 245 mS/mm (intrinsic transconductance of 275 mS/mm) at zero gate bias and good pinch-off behavior for a gate length of 0.5 mu m. The effective electron velocity is deduced to be 2.8*10/sup 7/ cm/s, equal to the theoretical prediction. >

Self-aligned gate (Al,Ga)As/GaAs modulation-doped FET's (MODFET's) have been demonstrated on MBE layers grown on

The low-frequency noise characteristics of GaAs MESFETs operating at very low power and at cryogenic temperatures of 77 and 10 K as well as at room temperature are discussed. A self-aligned gate and a buried p-layer were incorporated to maximize device gain and minimize low-frequency noise. Measurements at 77 K show a noise voltage spectral density of 1.0-2.0 mu V/ square root Hz at 1.0 Hz (referred to the transistor input) with a drain current of 1.0 mu A. >

An asymmetrical lightly doped drain (LDD) (Al, Ga)As/GaAs modulation-doped FET (MODFET) structure with high drain-to-source and drain-to-gate breakdown voltages was fabricated. The LDD structure has a self-aligned lightly doped n/sup -/ region between the channel and a heavily doped n/sup +/ region at the drain, to reduce the electric field and impact ionization. The length of the lightly doped n/sup -/ region on the drain side was varied from 0 to 1 mu m. Drain-to-source breakdown voltage BV/sub ds/ improved from 4.6 to >10 V while the transconductance g/sub m/ remained unchanged. The drain-to-gate reverse breakdown voltage BV/sub dg/ increased from approximately=7 to >20 V. The two breakdown mechanisms are believed to be independent. The LDD MODFET should find widespread application in circuits requiring high breakdown voltage such as high-speed analog-to-digital converters (ADCs) and microwave power amplifiers. >

A very high-performance voltage comparator circuit has been demonstrated using self-aligned gate AlGaAs/GaAs modulation-doped FET's (MODFET's)and laser-trimmable CrSi-based thin-film resistors. The MODFET master/slave comparator circuits demonstrated analog input resolutions of < 1 and 2.5 mV at sampling rates of 0.5 and 1 GHz, respectively, at Nyquist analog input rates at room temperature. The MODFET comparators operated to sampling rates greater than 2.5 GHz at Nyquist analog input rates. Static hysteresis of less than 1 mV was observed for some comparators at room temperature. The self-aligned gate MODFET's demonstrated average threshold-voltage offsets for closely spaced FET pairs of 2.53 ± 1.15 mV, and typical static hysteresis levels of < 1 to 3 mV. These MODFET comparators demonstrated the highest analog input resolution at gigahertz sampling frequencies ever reported, including comparators fabricated using AlGaAs/GaAs heterojunction bipolar transistors (HBT's).

The origin of the subthreshold leakage current in self-aligned gate GaAs MESFET's is investigated using temperature characterization, The leakage current is found to be comprised of two components, each dominant in a different temperature range. At temperatures below 0°C, space-charge-limited injection through the surface of the depleted channel dominates. At room temperature and above, the leakage current measured is the ohmic leakage through the bulk substrate. The space-charge-limited injection current is also found to be sensitive to the GaAs substrate quality.

A 5 × 5-bit parallel multiplier circuit has been demonstrated with self-aligned gate superlattice (Al,Ga)As/n+-GaAs modulation-doped FET's (MODFET's). Multiplication times (gate delays) and corresponding power dissipations of 1.80 ns (73 ps/gate) at 0.43 mW/gate and 1.08 ns (43 ps/gate) at 0.75 mW/gate were measured at room temperature and 77 K, respectively. These are the shortest gate propagation delays ever reported for parallel multiplier circuits at room temperature or 77 K using any semiconductor IC technology.

A self-aligned-gate GaInAs metal-insulator-semiconductor FET (MISFET) fabrication process that minimizes gate overlap capacitance and offers the potential of achieving submicrometer gate lengths is described. GaInAs MISFETs (1-µm gate length) fabricated with this process have given 0.49-W/mm gate width and corresponding power-added efficiencies of 48 and 39 percent at 4 and 8 GHz, respectively, at a drain voltage of 5.5. V. A small-signal gain of 3.2 dB was obtained at 15 GHz. The estimated carrier velocity was 1.7 × 107cm/s. More recent devices have carrier velocities of 2.5 × 107cm/s and are expected to have improved microwave performance.

Reduced short-channel effects were obtained by using a buried AlGaAs layer beneath the channel. A 0.5*10- mu m/sup 2/ MODFET was fabricated that had a peak transconductance of 264 mS/mm with a K-factor of 425 mA/V/sup 2/-mm. The measured output conductance was 2.37 mS/mm, a reduction from 18 mS/mm for a 0.5- mu m device without the buried layer. This combination of high transconductance and low output conductance makes the device ideal for high-speed analog and digital applications. The reduced output conductance gives a maximum gain of 110, compared with a more typical gain of 25 for a standard 0.5- mu m MODFET device. Threshold voltage dependence on gate length decreases from a 60-mV shift for 1.5- to 0.5- mu m gate length to 20 mV over the same range. The structure of the device, which was grown by molecular-beam epitaxy, consists of a five-period AlGaAs/GaAs superlattice and AlGaAs cap and spacer layers. The GaAs conducting channel is located between this charge control layer and a buried AlGaAs channel confinement buffer layer. This double heterostructure forms a quantum well in the channel region to further confine the quasi-two-dimensional electron gas. >

An asymmetrical LDD structure next to the gate was used to improve the breakdown voltages and short-channel characteristics (such as subthreshold currents, threshold voltage uniformity, and output conductance) of self-aligned gate heterostructure FETs (HFETs). This approach decreases impact ionization and increases the breakdown voltage. Previous approaches have created symmetrical lightly doped regions around the gate by using a sidewall spacer, which resulted in high source resistances and transconductance degradation, leading to a tradeoff in transconductance and breakdown voltage. In the LDD HFET, drain-to-source breakdown voltage increased from 4.5 to 12 V and drain-to-gate breakdown voltage improved from 8.8 to 25 V, while the transconductance remained unchanged at 250 mS/mm, as the length of the lightly doped region is varied from 0 to 1 mu m. Experimental data show that the LDD structure eliminates threshold voltage roll off and improves V/sub T/ uniformity across a 3-in. wafer at gate lengths of 0.55 mu m. Further analysis of the subthreshold characteristics and the threshold voltage sensitivity to drain bias shows that the LDD HFET is much less sensitive to drain bias than the conventional HFET. >

A technique is described for automatically aligning the gate contact of a gallium arsenide microwave-frequency Schottky-barrier field-effect transistor between the source and drain contacts. This technique consists of etching part of the epitaxial gallium arsenide layer from beneath the edge of the source and drain contacts and using the resulting overhang as an evaporation mask for the gate contact metal. Microwave measurements were made on a device fabricated in this manner with a 4-µ gate length. Maximum available gain measurements yield 16 dB at 2 GHz falling off at 6 dB/octave to a cutoff frequency of 11 GHz.