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The enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices based on the continuity theorem of electric displacement including interface charges is reported. The newly designed ENDIF as an effective rule for SOI high-voltage (HV) devices could be used to give a theoretical direction for increasing the vertical breakdown voltage (BV).

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are described and the structure is characterized by a compound buried layer (CBL) made of two layers and a polysilicon layer between them. The maximal temperature of CBL SOI is reduced by 25 K because of a window in upper buried oxide (UBO) when compared with the conventional SOI.

The fabrication, design, and characterization of high-quality factor microelectromechanical (MEM) resonators fabricated on thin-film silicon-on-insulators (SOIs) are addressed in this paper. In particular, we investigate laterally vibrating bulk-mode resonators based on connected parallel beams [parallel beam resonators (PBRs)]. The experimental characteristics of PBRs are compared to disk resonators and rectangular plate resonators. All the reported MEM resonators are fabricated on 1.25-[micro]m SOI substrates by a hard mask and deep reactive-ion etching process, resulting in transduction gaps smaller than 200 nm. Additionally, this fabrication process allows the growth of a thermal silicon dioxide layer on the resonators, which is used to compensate the resonance-frequency dependence on temperature. Quality factors Q, ranging from 20 000 at 32 MHz up to 100 000 at 24.6 MHz, are experimentally demonstrated. The motional resistances [R.sub.m] are compared for different designs, and values as low as 55 k[ohm] at 18 V of bias voltage are obtained with the thin SOI substrate. The thermal sensitivity of the resonance frequency is investigated from 200 K to 360 K, showing values of--15 ppm/K for the PBRs, with a possible compensation of 2 ppm/K when using 20 nm of Si[O.sub.2]. [2008-0112] Index Terms--Electrostatic devices, frequency stability, MEM system (MEMS), microelectromechanical (MEM) devices, micromachining, quality factor (Q), resonators.

This paper presents the design, fabrication, and measurement results for a novel non-contact-type radio-frequency (RF) microelectromechanical systems switch for 24-GHz radar applications. The proposed switches are free from unavoidable microwelding and stiction problems in other contact types, which in turn guarantee high reliability and long lifetime. The developed switch is a capacitive shunt type using a variation of the capacitance between the signal line and ground lines. The capacitance is precisely regulated by comb-drive actuators. This concept is simple, but the design requires a large and precise mechanical motion. In addition, for a low-loss switch structure, an air bridge with a large air gap is required. Therefore, the selective silicon-on-insulator process, based on the sacrificial bulk micromachining process, is designed for this switch fabrication. First, large insulating supports are fabricated 60 [micro]m below the wafer surface, and then, the RF switch is fabricated on these insulating supports. The measured actuation voltage is 25 V, and the actuation stroke is 25 [micro]m. The switching times are 8 ms in the OFF to the ON state and 200 [micro]s in the ON to the OFF state. In the RF characteristic measurements, the insertion loss without the long coplanar waveguide line loss is 0.29 dB and the isolation is 30.1 dB at 24 GHz. The bandwidth is relatively narrow, and the isolation is 25 dB or better in the range of 23.5-29 GHz. The reliability test for the switch was performed [10.sup.9] times with 18-mW RF power. We observed no mechanical failure or RF performance degradation. A power handling capacity of 0.9 W with a hot-switch condition was achieved. [2007-0183] Index Terms--Non-contact-type, radio-frequency (RF) micro-electromechanical systems (MEMS) switch, sacrificial bulk micromachining (SBM) process, selective silicon-on-insulator (SSOI) process, variable capacitors.

In this paper, we report on the design, fabrication, and characterization of an in-plane mode-matched tuning-fork gyroscope ([M.sup.2]-TFG). The [M.sup.2]-TFG uses two high-quality-factor (Q) resonant flexural modes of a single crystalline silicon microstructure to detect angular rate about the normal axis. Operating the device under mode-matched condition, i.e., zero-hertz frequency split between drive and sense modes, enables a Q-factor mechanical amplification in the rate sensitivity and also improves the overall noise floor and bias stability of the device. The [M.sup.2]-TFG is fabricated on a silicon-on-insulator substrate using a combination of device and handle-layer silicon etching that precludes the need for any release openings on the proof-mass, thereby maximizing the mass per unit area. Experimental data indicate subdegree-per-hour Brownian noise floor with a measured Allan deviation bias instability of 0.15[degrees]/hr for a 60-[micro]-thick 1.5 mm x 1.7 mm footprint [M.sub.2]-TFG prototype. The gyroscope exhibits an open-loop rate sensitivity of approximately 83 mV/[omicron]/s in vacuum. [2007-0100] Index Terms--Mode-matching, silicon-on-insulator (SOI), tuning fork, vibratory microgyroscope.

This paper is concerned with the design, fabrication, and characterization of novel high-temperature silicon on insulator (SOI) microhotplates employing tungsten resistive heaters. Tungsten has a high operating temperature and good mechanical strength and is used as an interconnect in high temperature SOI-CMOS processes. These devices have been fabricated using a commercial SOI-CMOS process followed by a deep reactive ion etching (DRIE) back-etch step, offering low cost and circuit integration. In this paper, we report on the design of microhotplates with different diameters (560 and 300 [micro]m) together with 3-D electrothermal simulation in ANSYS, electrothermal characterization, and analytical analysis. Results show that these devices can operate at high temperatures (600[degrees]C) well beyond the typical junction temperatures of high temperature SOI ICs (225[degrees]C), have ultralow dc power consumption (12 mW at 600[degrees]C), fast transient time (as low as 2-ms rise time to 600[degrees]C), good thermal stability, and, more importantly, a high reproducibility both within a wafer and from wafer to wafer. We also report initial tests on the long-term stability of the tungsten heaters. We believe that this type of SOI microhotplate could be exploited commercially in fully integrated microcalorimetric or resistive gas sensors. [2007-0275] Index Terms--Gas sensors, microhotplates, silicon on insulator (SOI), tungsten.

We describe electrostatically actuated silicon nanotweezers which are intended for the manipulation and characterization of filamentary molecules. The microelectromechanical system consists of a pair of opposing tips whose distance can be accurately adjusted by means of an integrated differential capacitive sensor. The fabrication process is based on silicon-on-insulator technology and combines KOH wet anisotropic etching and deep reactive ion etching of silicon to form sharp nanotips and high aspect ratio microstructures, respectively. In the designed prototype, the initial gap between the tips was around 20 [micro]m. The device showed a maximum displacement of about 2.5 [micro]m, and we could achieve a resolution better than 0.2 nm (in static mode). We measured a resonant frequency of 2.5 kHz and a quality factor (Q factor) of 50 in air. The instrument was used to perform static and dynamic mechanical manipulations on DNA molecules, and we could distinctly observe the viscoelastic behavior of DNA bundles from these experiments. [2007-0162] Index Terms--Biomechanics, dielectrophoresis (DEP), differential capacitive sensor, DNA tweezers, molecular biophysics, silicon-on-insulator (SOI).

A closed-form surface potential solution is obtained for gate oxide-silicon film interface, silicon-film-buried oxide interface and buried oxide-substrate interface of fully depleted silicon-on-insulator (SOI) MOSFETs by considering the effect of substrate charge. Three different equations are obtained by solving the 1-dimension Poisson equation in vertical direction and they are solved for various regions of operations.

The threshold voltage variation in Schottky-barrier (SB) MOSFETs with different geometric parameters as well as devices with dopant segregation is examined. A multigate structure has suppressed the threshold voltage variation by improving carrier injection by reducing its sensitivity to the SB height inhomogeneity.

The noise mechanisms at high frequencies in MOSFETs are studied and an analytical model is described that is applied to floating body silicon-on-insulator (SOI) MOSFETs. The studies have shown that scaling of the transistor structure will improve transconductance and reduce the noise figure (NF), but at the cost of a reduced operating drain voltage range.

A novel approximation of 2-dimensional (2-D) potential function perpendicular to the channel for the fully depleted (FD) silicon-on-insulator (SOI) MOSFETs on films with vertical Gaussian profile and an analytical threshold voltage model are derived. This model has represented a feasible way to find the threshold voltage and has provided reference points in developing new 2-D models for nonuniform FD-SOI devices.

The actively body-bias controlled (ABC) silicon-on-insulator (SOI) technology is described that has controlled the body biases without an area penalty and increase of the parasitic gate capacitance. The studies have shown the enhancement of the speed performance and the reduction of the variation for the ABC SOI technology.

The NROM-cell concept is introduced as a promising technology for replacing Flash nonvolatile memory devices also in embedded products, owing to its intrinsic 2-b/cell operation and better endurance. This method has allowed profiling hole distribution in devices erased with different bias conditions and also monitoring the evolution of the nitride charge with cycling, correlating it to the degradation of memory reliability after cycling.

The self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology are discussed and the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs is analyzed. The effects of SHE on device performance might result in the degradation of the long-term reliability.

A device design and optimization strategy is provided for low-power and stable static random access memory (SRAM) applications. The analysis has shown that thinner buried oxide (BOX) and cooptimization of body doping and back biasing are efficient in designing low-power and stable ultrathin-body fully depleted silicon-on-insulator (UTB FD/SOI) SRAM cell.

The low-power mobile multimedia (LPMM) technologies are discussed, which are very important drivers of nonclassical materials, devices and innovative circuit and system solutions. The studies have shown that CMOS technologies are expected to remain for long as the leading information technology.

The sensitivity of silicon nanowire biosensors is examined. Findings suggest an increase in the sensitivity of the nanosensor with reduced doping, smaller diameter and shorter length.

The low-frequency-noise characteristics of separation by implantation of oxygen (SIMOX) and bonded silicon-on-insulator (SOI) wafers are examined. Higher buried-oxide (BOX) bulk and interface trap densities result in higher noise on SIMOX.

The corner effects in Pi-gate silicon-on-insulator (SOI) MOSFETs are examined. The inverse dependence of the extension of corner regions on doping concentration is observed.

The device design of 15-nm high-speed source-heterojunction-MOS transistors (SHOTs) on silicon-on-insulator (SOI) substrates with the high-velocity electron injection from the source into the channel regions is examined. Results suggest the achievement of transconductance enhancement of SHOT due to high-velocity electron injection in a whole range of drain bias.

The speed performance of silicon large-scale integrations is enhanced to exhibit a clock rate of more than 50 GHz by introducing the balanced complementary MOS on a silicon (551) surface substrate using 3-D-structured MOS transistors. Silicon MOS transistor performance such as the current drivability and the transconductance are scheduled to be enhanced up to a very high speed.

A general analytical solution is derived for the Poisson equation for generic undoped metal-oxide semiconductor field effect transistors (MOSFETs), including silicon-on-insulator (SOI), symmetric and asymmetric double gate (s-DG, and a-DG). The results have shown that the general iterative solution can be used for formulating or bench-marking unified SOI/DG MOSFETs with an undoped channel for surface-potential-based compact models for terminal currents and charges.

The continuous decrease of the supply voltage to 1 V and below in CMOS makes the design of laser drivers a challenging task. Hence, a detailed comparison of three basic driver architectures, namely, common source (CS), CS with source degeneration, and source follower (SF) is presented using transistor models including short channel effects. Based on this comparison, two power-optimized driver topologies are implemented in a 90-nm silicon-on-insulator CMOS technology. The SF driver features a bandwidth of 18 GHz on a 50-[ohm] load. The required chip area is only 140 [micro]m x 140 [micro]m, which is very beneficial for high-density short-distance optical interconnects. This allows a data rate of 12.5 Gb/s at a bit error ratio of less than [10.sup.-12] to be achieved even with a 10-Gb/s oxide confined vertical-cavity surface-emitting laser (VCSEL). The power consumption is 27 mW. The drivers were optimized for maximal eye opening by applying a fast and accurate VCSEL model. Index Terms--Common source (CS), modeling, optical interconnects, parasitics, source follower (SF), vertical-cavity surface-emitting laser (VCSEL).

A three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between.

The impact of pseudo-MOS technique on threshold and flatband voltages and the reason of their dependence on silicon-on-insulator (SOI) layer thickness are described. The band-offset-induced depletion beneath the source contact obstructs the local formation of the inversion layer of the SOI/buried oxide interface.

The threshold-voltage and the short-channeleffects (SCEs) of strained-SOI n- and p-MOSFETs are quantitatively studied by using device simulation. The control of the work function of the gate electrode and the control of bias gate bias are effective for n-MOSFETs and in p-MOSFETs, thicker strained-Si layers and the higher back gate bias are necessary to suppress the buried channel formation.

The experimental evaluation of the gate architectures influence on the performance of double gate (DG) silicon-on-insulator (SOI) MOSFETs is reported. DG transistors show improved short channel effects control, higher saturation current and improved mobility.

The impact of the back-gate bias on lateral DMOS (LDMOS) transistors on silicon-on-insulator (SOI) substrates is discussed. An analytical model that takes the back-gate bias and the device parameters into account is presented and verified with a 0.8-mu m, 80-V SOI smart power technology.

The alternative device topologies that may greatly increase the energy yield for a given system size by increasing both the generation efficiency and conversion efficiency are examined. An insulated gate bipolar transistors and a MOS-triggered thyristor, both based on previous silicon-on-insulator MOSFET designs are examined for their switching speed and losses using physics-based finite element simulation.

A transport model based on the solution of the Boltzmann Transport Equation for modeling eta-channel silicon-on-insulator MOSFETs and MESFETs is presented. The mobility of the equivalent SOI MESFET device is a factor of three to five times higher than that of the SOI MOSFET in the subthreshold regime.

A study is made of 1/f and generation/recombination (GR) noise in silicon-on-insulator (SOI) silicon-germanium heterojunction bipolar transistors fabricated using selective growth of the Si collector and nonselective growth of the SiGe base and n-type low doped Si emitter. The noise in SOI devices is found to be comparable to that in control bulk devices, indicating that the buried oxide in SOI devices does not degrade the noise.

A novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor is introduced. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base and the self-aligned base and emitter regions greatly reduce the parasitic components.

Self-heating in a 0.25Mum BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization via layer, and the simulation structure width is investigated.

Silicon-on-insulator (SOI) CMOS technology offers low parasitic junction capacitance, and therefore provides speed and power enhancements to digital applications when compared to bulk CMOS. The RF performance of this technology is presented, and the capabilities of CMOS technology that are expanding into the low-power and mmWave regime are shown.

A reliable fabrication technique is developed to make Terahertz-frequency waveguide for NbTiN phonon-cooled hot-electron bolometer (HEB) mixers using 6 mum Silicon-On-Insulator (SOI). It is found that this approach can be extended to several THz and would allow to design more complicated chips for balanced and sideband separating mixers.

We report on the architecture and experimental characterization of a small-footprint optoelectronic receiver for parallel arrays of optical interconnects. The receiver is designed and fabricated in the 0.5-[micro]m silicon on sapphire CMOS technology. The circuit design exploits the properties of MOS transistors with three different threshold voltages and the insulating substrate to achieve a low-power, high-speed and compact circuit. The design attains a 7-pJ energy per bit transduction cost when operated at 1 Gbit/s data rates. Index Terms--Chip-to-chip communication, optical interconnect, optoelectronic receiver, silicon-on-insulators (SOI) CMOS, silicon on sapphire (SOS) CMOS.

Physical mechanisms responsible for the reduction in both electron and hole mobility in strained-silicon-on-insulator (SOI) CMOS devices with thin strained-Si layers are examined. As a result of insight into these mobility lowering mechanisms, a new device design regarding the strained-Si thickness and the Ge content is presented to realize high-speed thin film strained-SOI CMOS devices in 25-nm gate length regimes.

A systematic and quantitative comparison between the analog characteristics of the bulk and silicon-on-insulator (SOI) technology is presented. It is shown that gate-workfunction engineering is essential in fully depleted SOI (FDSOI) devices for improving analog performance.

Computer simulations of various silicon-on-insulator (SOI) MOSFETs with double and triple-gate structures and gate-all-around devices are described. Result recommend Pi-gate device for future nanometer MOSFET applications.

Research into the suppression of the parasitic bipolar effect in MOSFET structures is presented. A design which offers near complete protection against circuit failure, and thus applications in SOI circuits, is proposed.

Research was conducted to examine the suppression of floating body effects in silicon-on-insulator complementary metal oxide semiconductor field effect transistors (MOSFET) using a new type of source engineering. The device supports a symmetric source-drain structure by standard MOS fabrication processes. Moreover, it restores breakdown voltage properties to the similar values as in general bulk devices while suppressing other phenomena that originate from the floating body effects.

A study was conducted to examine a body-contacted silicon-on-insulator (BC-SOI) metal oxide semiconductor field effect transistor structure without the floating-body effect. The threshold voltage of BC-SOI is measured as a function of the well bias to determine the effect of well pick-up distance. The structure significantly increases drain breakdown voltage and enhances hot-carrier degradation features. Moreover, it reduces parasitic effects while incorporating gate-delay time features in dynamic random access memory applications.

The design of a new scheme for a low-voltage 16 M-dynamic random access memory/silicon-on-insulator (DRAM/SOI) wherein the DRAM operation had been obtained below 1 V is described. The memory cell's storage capacity is influenced by the soft-error for the bulk-Si DRAM. Because of the device's low power supply requirements, the read signal level also decreases and becomes sensitive to noise. The SOI-DRAM may possibly be adopted in the next generation of mobile computing system devices.

A new, comprehensive transient-based method is proposed for gauging the effect of floating-body charge on a fully- or partially-depleted silicon-on-insulator (SOI) MOSFET transistor device design space. The shifts in the threshold voltage and off-current design device parameters caused by hysteretic floating-body charge are quantified and may be problematic. These shifts can be reduced by decreasing the effective carrier lifetime of the SOI.

The dependence of substrate resistivity on substrate crosstalk is analyzed using simple equivalent circuit models. Very low resistivity substrates have significantly lower crosstalk for all frequencies, compared to both high resistivity and medium resistivity substrates and the crosstalk is dependent on both the geometry and the load impedance.

The perspective of body-source built-in potential lowering the geometry-dependent floating body effect in state-of-the-art silicon-on-insulator (SOI) MOSFETs can be explained and predicted by the geometry dependence of threshold voltage [V(sub T)]. The correlation between delta V(sub bi) and V(sub T) is underlying mechanism responsible for the coexistence of partially depleted and fully depleted devices in a single SOI chip.

Based on the results of basic studies on the housings and FRP cores of polymer composite insulators, a line post type polymer insulation arm for 154 kV with a truss structure formed by three polymer insulation arm units; i.e., two horizontal units with an open angle between them and one suspension unit, was experimentally manufactured. Samples of the polymer insulation arm were tested to verify the withstand voltage performance under a polluted conditions, the impulse and power-frequency withstand voltage performance, and the mechanical performance by a full scale test against longitudinal loads.