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This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents I on more than double, while the off-state currents I off remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher I on increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design. • Gate Overlap Tunnel FET : On Current more than double & Off current an order of magnitude lower than 45 nm CMOS. • New GOTFET based Comparator Design: PDP is merely 1/3rd of that of conventional comparator. • New GOTFET based Comparator Design: PDP is merely 1/3rd of that of conventional comparator. • Reduced Transistor Count : Requires only 48 transistors compared to 70 required for conventional designs. • Reduction in PDP : GOTFET based ADC shows 99.7% improvement in PDP. [ABSTRACT FROM AUTHOR]

This study presents a high-speed successive-approximation-register analog-to-digital converter (SAR ADC) for low-noise low-power satellite transceiver applications. The proposed system is a (2+1)-bit then 2-bit per cycle SAR ADC with a sampling rate of 1 GS/s, 9-bits resolution designed in a 65-nm standard CMOS process. This system resolves nine bits using a special switching scheme in a total of four cycles per sample. This is achieved by interleaving four capacitive digital to analog converter (C-DACs) with 1-fF unit capacitance. As the interleaving is limited only to the DACs that match well, the design is not affected by the drawbacks of full interleaving. Hence, better power efficiency and performance metrics were obtained in comparison to regular interleaved ADCs. A special timing with an additional first bit comparator is optimized to have appropriate timing margins for every step from a single 4-GHz low-noise clock source that is readily available in the 8-GHz direct conversion frontend. This comparator is reused as the active comparator in both the interleaving phases. The proposed design achieved an effective number of bits value of 8.2 bits at Nyquist rate with a power consumption of 12 mW, resulting in a figure of merit of 38.37 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is presented in this paper. This circuit has an advantage of digital circuit concept and can be easily migrated to lower technologies. Also, the digital circuits are less sensitive to the noise and device mismatches can be synthesized and auto place and route (P&R) using EDA tools. The design of the proposed comparator is based on the standard cells implementation. As the proof of concept this comparator is implemented on Xilinx Basys-3 Artix-7 FPGA kit. The prototype of complete 4-bit Flash ADC is designed in 180 nm CMOS technology with 1.8 V supply voltage. The measured values of ENOB, SNDR, SNR and SFDR are 3.6, 23.43 dB, 25.2 dB and 30.1 dB, respectively at 33.20 MHz input frequency and 200 MHz clock frequency. The total power consumed by the 4-bit flash ADC is 2.14 mW. The calculated value of DNL and INL is < 0. 4 LSB and < 0. 5 LSB respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 µW using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications. [ABSTRACT FROM AUTHOR]

This paper presents a high linear voltage-to-time converter (VTC) with wide input range of over 1.2 V p-p, diff for the high-speed high-linear time-domain (TD) analog-to-digital converters (ADC). Different from the conventional VTC, the proposed VTC samples the input as the initial charge voltage, and apply current source independent of the input for charge process. Thanks to the high-linear sample and hold (S/H) circuit and low-mismatch current source, the input range and linearity of the proposed VTC are greatly improved. Also, a low propagation-delay comparator is designed for high-speed VTC. The VTC is fabricated in 65 nm CMOS process, occupying an area of 0.012 mm2, consuming power of 0.48 mW. The measured results show that conversion gain of the VTC is as high as 1.95 ns/V. DNL/INL is suppressed within −0.32–0.38 LSB and −0.5–0.6 LSB, respectively. In 250 MHz full Nyquist frequency, SFDR is measured over 66 dB. [ABSTRACT FROM AUTHOR]

This paper presents the design of linear ramp generator and digital BIST for an on-chip ADC testing. It replaces the costly and time-consuming traditional mixed signal test methods like DSP-based testing, ATE, etc. The proposed on-chip analog ramp generator uses only a few transistors to generate linear ramp signal. A TIQ comparator based 8-bit flash ADC is taken under test. The output response of the ADC is analyzed in the digital BIST to measure the primary nonidealities affecting the linearity and accuracy of the data conversion. In testing, ADC generates the digital data sequence as a test pattern in response to the ramp input while digital BIST estimates the conversion error. This method does not require DAC and any additional components which increase the area overhead of ADC test. The complete design of ramp generator is integrated with TIQ flash ADC and verified in 0.18 μ m CMOS technology with 1.8 V of the power supply and 100 kHz of the input frequency. Measurement of nonidealities shows that the design of an 8-bit flash ADC has good accuracy in data conversion with the differential nonlinearity of − 0.24/ + 0.17 LSB and integral nonlinearity of − 0.44/ + 0.04 LSB. [ABSTRACT FROM AUTHOR]

Abstract This paper presents an on-chip built-in self-test technique for testing an ADC. The conventional test of a mixed signal element has performed through DSP based tester with the help of an arbitrary waveform and a signal digitizer but it is consuming more time and cost. Hence, the testing strategy has started an on-chip BIST based testing scheme to control the testing issues. An on-chip ramp generator based BIST technique has proposed for testing static characteristics of ADC. The evaluation procedure of this BIST consists of test pattern generation and output response analysis. A novel cascode current mirror based analog linear ramp generator has used to generate the test pattern through fast switching TIQ comparator based ADC. Output response analyzer evaluates switching positions of binary code for computing the static parameters. The proposed ADC BIST has implemented in 0.18 μm technology with the supply voltage of 1.8 V. [ABSTRACT FROM AUTHOR]

Summary: A low‐power technique for high‐resolution comparators is introduced. In this technique, p‐type metal‐oxide‐semiconductor field‐effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter‐based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n‐channel metal‐oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power benefits of the proposed comparator were verified using analytical derivations, PVT corners, and post layout simulations. The results confirm that the introduced technique reduces the power consumption by 60%, also, provides 57% better comparison speed for an input common mode voltage (Vcm) range of 0‐Vdd/2. [ABSTRACT FROM AUTHOR]

A new dynamic comparator with offset elimination circuit is proposed. The offset elimination circuit decreases the influence of the offset voltage effectively and increases the resolution of the comparator. The simulation results show that, if the pre-set offset voltage is 10mV, the offset elimination circuit can decrease to the enough low value, which meets the requirements of the system. The standard deviation of the offset voltage decreases from 7.27mV to 1.15mV with the utilization of the offset elimination circuit in Monte Carlo simulation. [ABSTRACT FROM AUTHOR]

This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) intended for use in wearable biomedical circuits. In order to achieve the nanowatt range power consumption, an energy-efficiency modified V CM -based switching scheme is proposed. In addition, a fully dynamic comparator and a dynamic register are used to eliminate the static power consumption. To improve the signal linearity in such a low supply voltage, a double-boost bootstrapped switch is proposed. A prototype of the proposed SAR ADC was fabricated in 0.18 µm 1P6M CMOS technology within a bio-sensor front-end circuit, which occupies an active area of 370×390 µm 2 . The SAR ADC achieves 57.8 dB SNDR and consumes 68nW at 0.5 V supply voltage and 10 kHz sampling rate, resulting in a figure-of-merits (FOM) of 10.8fJ/conversion-step. [ABSTRACT FROM AUTHOR]

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage , is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing PMOS transistors at the input of the comparator. [ABSTRACT FROM AUTHOR]

The paper presents a low power and high dynamic range 4-bit, 80 MHz Phase ADC that is simulated in Tanner tool using 45 nm technology. Phase ADC can be used in digital signal processing, Bluetooth, cellular and micro sensor wireless networks for wireless communication and in other various communication systems. This ADC is much better than conventional amplitude ADC in case of number of comparators, power dissipation and surface area because this directly quantizes the phase of the received signal instead of using any reference voltage and two separate amplitude ADCs. The Phase ADC presented here includes Operational Transconductance Amplifier (OTA), comparator and a phase quantization network which are also analyzed in 45 nm technology using Tanner tool. Analysis for power dissipation, slew rate, delay and dynamic range at different values of power supply, input signal frequency and bias current is done. [ABSTRACT FROM AUTHOR]

The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise) signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator's circuit. This article presents the results of a CMOS comparator with hysteresis design -- the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to design a prevented glitch circuit (PGC) to avoid the destroyed that is caused to glitch in the paralleling comparator Flash ADC. The advantages of this prevented glitch circuit are high-speed, lower power consumption, and size effective, furthermore, it also reduce the faults. We used the TSPC's D flip-flop to achieve this prevented glitch circuit where reduces and improves the glitches and faults, respectively. The PGC is simulated by the Tanner Pro. 13.0 with Generic0_25µm techniques in 0.25-µm. Summarizing the features of this implemented circuit is lower power of 3.3V at 333.3MHz, higher area density is 89.6%, and lower area size is 1221.16x721.793µm². [ABSTRACT FROM AUTHOR]

We propose a possible application of a high-speed flash type single flux quantum (SFQ) analogue-to-digital converter (ADC) to optical communication systems and their measuring instruments. One of the problems in optical networks is the chromatic dispersion over a standard single mode fiber, which has to be recovered by optical dispersion compensation. Recently, there has been great interest in 100-Gbit/s Ethernet technologies as next generation optical networks in which chromatic dispersion is more severe. Among several types of architectures, digital coherent optical communication system is a promising technology. Correction of the dispersion is performed electrically after digital conversion without any optical compensation, which would ease system construction. Digital storage oscilloscopes with high-speed ADCs are crucial for investigating the architecture and for constructing 100-GbE systems. A flash-type SFQ ADC is attractive for its high-speed sampling clock capability, especially as an instrument for a digital coherent receiver. The maximum operating frequency of the comparator in ADCs was studied by simulation for various critical current densities (Jo). The simulation suggested that using Jc of 20-40 kA/cm2 enables the comparator to operate at a clock frequency of more than 100 GHz. An O/E converter, a uni-traveling-carrier photodiode, operable at low-temperature, has been developed and 40-GHz operation was confirmed at 5 K. We have also designed a 1-bit slice of a superconducting quantum interference device-(SQUID) wheel-type ADC and its test circuit including a doubler circuit and two driver types. [ABSTRACT FROM AUTHOR]

An array of N comparators subject to the same input signal and independent additive noise, with the outputs from each comparator summed, is a useful noise model for a range of systems including flash analog-to-digital converters, Digital Multibeam Steering sonar arrays and parallel neurons. It has previously been shown that for certain threshold configurations the transmitted information through such an array is maximised for non-zero noise. This behaviour has been termed Suprathreshold Stochastic Resonance (SSR) and in this paper we show that SSR occurs for a number of different signal and noise distributions. Also presented is an analysis of the variance of the quantisation error incurred when all thresholds are set equal to the signal mean, for Gaussian and uniform distributions. It is shown that the minimum error variance is given by a non-zero value of noise. [Copyright &y& Elsevier]

• A scheme for power consumption reduction in a conventional comparator is presented. • The proposed scheme turns off the preamplifier, to reduce the power consumption. • The power-delay product is optimized using dynamic inverters. • The input referred offset is compensated using an offset cancellation scheme. Dynamic comparators are an essential part of low-power analog to digital converters (ADCs) and are referred to as one of the most important building blocks in mixed mode circuits. The power consumption and accuracy of dynamic comparators directly affects the overall power consumption and effective number of bits of the ADC. In this paper, an early shutdown approach is proposed to deactivate the first stage preamplifier at the suitable time. Furthermore, a time domain offset cancellation technique is incorporated to reduce offset effects. With the proposed method power consumption can be reduced in low power high precision dynamic comparators. The proposed method has been simulated in a standard 0.18 µm CMOS technology and the results confirm its effectiveness. The proposed circuit has the ability of reducing the power consumption by 21.7% in the worst case, while having little effect on the speed and accuracy in comparison with the conventional methods. The proposed comparator consumes only 47 µW while operating at 500 MHz. Furthermore, Monte Carlo evaluations showed that the standard deviation of the residual input referred offset was 620 µV. [ABSTRACT FROM AUTHOR]

In this paper, an ultra high speed dynamic comparator is presented. The PMOS pass transistors are used in the latch and pre-amplifier stage of the comparator. At the regeneration phase, the latch is activated faster with sufficient preamplification gain and very less power consumption. Meanwhile, a cross-coupled set up of NMOS transistors in latch stage enhances the gain and speed. Unlike the previous reported comparator, the proposed dynamic circuit avoids the extra power consumption as well as delay, and establishes the optimum offset and kickback noise. The benefits in delay and power are verified with the help of analytical expressions, meticulous Monte Carlo simulations and process corner analysis in CADENCE SPECTRE at 90 nm CMOS technology. The simulation results validate that the proposed structure provides the about 2.5 times better speed and minimizes the power consumption by 3 times in comparison to hybrid double tail dynamic comparator with only 0.348 fJ/conv. energy per conversion. Moreover, it provides 2.44 mV offset with optimum kickback noise and area. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid design of flash based successive approximation register (SAR) analog-to-digital converter (ADC) with a resolution of 6 bits, operating at 1 GS/s. The dynamic comparator in traditional architecture is replaced by an inverter based comparator, for an energy efficient comparison. A segmented spilt capacitor array charge redistribution digital-to-analog-converter (CDAC) is used to achieve improved linearity, power, speed and area. Further, a 3 bit per clock cycle approach is adopted to achieve fast conversion time. The hybrid flash-SAR ADC has been designed and simulated in a standard 28 nm CMOS technology with V DD of 0.9 V and 1 GS/s of sampling rate. The designed ADC achieves a peak SNDR of 35.56 dB and an SFDR of 40.81 dB. The design achieves 5.61 effective number of bits (ENOB) with 2.33 mW of power consumption and figure-of-merit (FOM) of 47.7 fJ/conversion. [ABSTRACT FROM AUTHOR]