Search

Conjugated semiconducting polymers are key active materials for printable electronics, sensors and biosensors, organic photovoltaics, organic light emitting devices, and more. The research in the field developed very efficient materials and sound structure property relationships, thus making a case for a transition from laboratory to industrial environment. At this critical juncture, sustainability, and ease of scaling up are at least as important as performances, to the point that efficient materials on a lab scale could become unpractical for the industry. The development of more efficient synthetic protocols and the complete removal of all organic solvents from both the synthesis and the processing of semiconducting polymers can help tremendously to improve sustainability and reduce costs. It is shown that the use of an aqueous dispersion of the food grade surfactant lecithin as the medium, enables the synthesis and processing of the representative semiconducting alternating copolymer poly (9,9-dioctylfluorene-alt-bithiophene) (PF8T2) in high yield and high quality and with transistor performances comparable with those obtained with reference materials synthetized and processed from volatile organic solvents.

The electrothermal behavior of gallium nitride (GaN) HEMTs has been simulated by using a hybrid approach in which the problem is solved by coupling together an effective model (for the electrical part) and a 3-D finite element model (for the thermal part). The effective model relies on the estimation of the channel current at different temperatures in the absence of thermal gradients. This regime occurs in real devices only during the very initial stage of bias pulses, when self-heating effects are not yet developed, for time intervals shorter than 1 ns. Virtual output electrical characteristic, in which self-heating effects are negligible, have been derived from pulsed measurements of the electrical output characteristics and electrothermal transient simulations. The maximum temperature because of self-heating evaluated by using the virtual output characteristic are substantially higher than those obtained using the short time-pulsed measurements directly. The results have been validated by a comparison with temperature measurements obtained using Raman thermography. This approach has proven to be numerically very efficient and fast, allowing the analysis of realistic complex structures and circuits.

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μFE> 1 cm2V−1s−1) and excellent stability under gate bias stress (bias stress Vds = 0V). However, after prolonged bias stress performed at high drain voltage, Vds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high Vds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.

The electrical properties of dinaphtho [2,3-b:2′ ,3′ -f]thieno[3,2-b]thiophene (DNTT) based organic thin film transistors (DNTT-TFTs) were investigated in detail under dark and various light illumination conditions with different channel lengths. We have exploited the experimental curves current–voltage of our TFT to extract electrical parameters such us mobility, threshold voltage, sub-threshold voltage and trapped density in dark and under illumination. By using an analytical model, we are able to reproduce very accurately the output and transfer characteristics with a joint analysis of the L = 100 μm and L = 500 μm electrical characteristics, the dependence of the contact resistance (Rc) upon the illumination conditions has been extracted. The used model gives a good agreement between the measured current–voltage characteristics of the DNTT-TFTs and those modeled in all measurement conditions (in dark and under illumination).

Organic material deposition by gravure printing is a promising pathway for the realization of large area flexible electronic devices. Nevertheless, in order to achieve high performance it is required to improve the electronic ink printability, operating on the fluid dynamic mechanisms involved during the process. In this work, this issue has been faced working on ink characteristics for a conductive and a dielectric material. The suitable ink features have been defined studying the influence on the printability of the different forces that act in the fluid during the printing process, using an experimental approach. Properly defined ink formulations have been printed, considering different shapes and dimensions of the cells on the gravure cliche to fit the ink features. The printing outcomes have been compared and analysed through the evaluation of several significant fluid dynamic parameters and the rheological characterization of the materials. Finally, exploiting the results of this study, high performance fully printed organic thin film transistors have been realized.

We present a compact model for the DC and small signal AC analysis of Organic Thin Film Transistors (OTFTs). The DC part of the model assumes that the electrical current injected in the OTFT is limited by the presence of a metal/organic semiconductor junction that, at source, acts as a reverse biased Schottky junction. By including this junction, modeled as a reverse biased gated diode at source, the DC model is able to reproduce the scaling of the electrical characteristics even for short channel devices. The small signal AC part of the model uses a transmission line approach in order to compute the impedances of the channel and parasitic regions of the device. The overlap capacitances and the presence of non-ideal metal/organic semiconductor junctions are taken in account as well and the model can be easily adapted to different device geometries. The model is particularly well suited for printed devices, often realized with large process tolerances, since it takes into consideration the presence of parasitic regions and their effect on the AC operation. The model has been validated on printed OTFTs using a pentace-derivative as organic semiconductor with a quite peculiar device layout. It has been fully implemented in Verilog-A programming language.

We studied, by 2D numerical simulations, the effects of poor semiconductor morphology near the source and drain contacts of BGBC-OTFTs. The variations of the electrical characteristics and of the path of the injected carriers in the transistor channel have been analyzed considering different defective regions, parameters (mobility, density of states) and contact thicknesses. The results showed that 100 nm wide defective regions can induce high contact resistance, resulting in large variation in the electrical characteristics. However, the typical S-shape in the low-Vds output characteristics is clearly observed only considering a combination of highly defected regions and Schottky barrier at the contacts. Furthermore, the simulations showed that most of the current is injected and extracted, at the source and drain contact, within a few nanometers from the semiconductor- dielectric interface. This explains the small influence of the contact thickness on the simulated electrical characteristics, at least for a contact thickness down to 10 nm.

In this work, staggered top-gate n-type organic thin film transistors (OTFTs) with evaporated PDIF-CN2 semiconducting layers, spin-coated Cytop™ dielectric barriers and channel lengths ranging from 100 to 2 μm were fabricated on polyethylene-naphtalate (PEN) substrates. Hexamethyldisilazane (HMDS) treatment of the PEN surface was successfully tested as an effective strategy to achieve flexible devices with improved electrical response. Following this approach, maximum field-effect mobility (μFE) values exceeding 0.4 cm2/V⋅s were observed in air. Moreover, the self-encapsulating features of the investigated top-gate configuration, employing the highly hydrophobic Cytop™ dielectric films, allowed getting considerable performances in terms of un-sensitivity to hysteresis and bias stress phenomena.

We studied the capacitance characteristics of printed p-type organic thin-film transistors (OTFTs) under vari- ous frequencies and dc bias conditions. The experimental results show that the device capacitance is largely influenced by parasitic capacitances, related to the large gate-active layer overlap areas required by the printing processes. We developed a nonquasi- static small-signal capacitance model that adopts a transmission line approach and considers the specific layout of the OTFTs, taking into account for the parasitic capacitances and, hence, is particularly well suited for printed devices. In addition, the model included parasitic impedance at the metal-organic semiconductor contacts, related to the nonohmic behavior of source-drain contacts. The model has been shown to nicely reproduce the experimental capacitance characteristics in all their features. It should be pointed out that the proposed model allows the reproducing of any device layout and could be implemented in device simulator to analyze small-signal dynamic characteristics.

Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon TFTs, fabricated with a spacer technology providing submicron (0.35 mu m) LDD regions, have been analyzed by using two-dimensional numerical simulations. The numerical analysis was used to explain the observed reduced kink effect and short channel effects presented by FSA GOLDD devices, compared to SA devices. The reduction of the kink effect has been attributed to the reduced impact ionization rate, and related to reduced electric fields at the channel/LDD junction. In addition, the role of the LDD dose on the kink effect has been also investigated, clarifying the observed current inflection occurring in the kink effect regime and the LDD dose dependence of the breakdown. Reduced short channel effects were attributed to reduced floating body effects, since drain induced barrier lowering was apparently not affected by the SA GOLDD structure, when compared to SA devices.

Low-frequency noise (LFN) has been used in order to gain insight into the physical properties of the materials involved in organic thin-film transistors (OTFTs) fabrication, often with contradictory results. Besides the physical origin of noise, contact effects on noise have been a source of concern and discussion. In this paper, we report on accurate LFN measurements in p-type staggered top-gate OTFTs over four decades of channel current, from the subthreshold to the strong accumulation region. The measured spectra follow a clear 1/ $f$ behavior attributed to the trapping/detrapping of channel charge carriers into interface and oxide defects, while the influence of noise sources at contacts is found to be negligible. However, contacts affect the measured noise by a nonnegligible differential resistance. Noise data are interpreted in the context of a multitrap correlated mobility fluctuations (CMFs) model, showing that noise is dominated by acceptor-like traps. Despite the low mobility ( $\mu _{{\mathrm{eff}}}\sim $ 2 cm2/V/s), the large scattering parameter ( $\alpha \sim 10 ^{7}$ Vs/C) produces an increase of the noise at the higher currents due to CMFs. The product $\alpha \mu _{{\mathrm{eff}}} \approx 2\cdot 10^{7}$ cm2/C, which measures the strength of CMFs, is similar to what was reported for a-Si:H and much higher with respect to crystalline silicon MOSFETs revealing a strong correlation between CMFs and the state of disorder of the active layer.

As fabrication and positioning of micro- and nanocrystals grow in importance in a wide range technological applications, there is an increasing requirement for the development of a shared technological platform that is able to process materials from solutions on large areas. Here, the application of lithographically controlled wetting (LCW) for the manipulation and positioning of single crystals directly on devices is reported. In the LCW, a stamp, consisting of a metallic grid, is positioned in contact with a liquid thin film spread on a substrate; under these conditions, the capillary forces pin the solution to the stamp protrusions, thus splitting the continuous film in separated droplets or channels. As the solvent evaporates and the solution reaches the saturation, the solute precipitates onto the substrate within the menisci, giving rise to a structured thin film, in correspondence of the protrusion of the stamp. The possibility to achieve a patterning of crystals of conjugated molecules with a defined shape and with controlled size directly on device is demonstrated and pattern of crystals are investigated using polarized optical microscopy, atomic force microscopy, X-ray diffraction; they are also electrically characterized. The application of lithographically controlled wetting on the manipulation and positioning of single crystals directly on devices. It is demonstrated that it is possible to achieve patterning of crystals of conjugated molecules with a defined shape and with controlled size directly on a device.

Investigation of gate dielectric conduction properties in organic p-type staggered thin-film transistors is reported by means of direct-current, capacitance–voltage, and noise measurements. Results suggest that transport in the CYTOP™ gate dielectric is dominated, at low currents, by Schottky conduction due to the emission at the aluminum gate interface through a barrier $\phi _{B} \approx 1$ eV, while is limited, at higher currents, by space-charge conduction in the trap-limited regime with an effective mobility $\mu \theta $ estimated in the order of $10^{-9}$ cm2/(Vs). Gate current noise follows a 1/ $f$ law and it is found to be proportional to $I_{G}^{2}$ , which is inconsistent with the commonly assumed mobility fluctuation. Traps responsible for gate noise are dielectric-bulk traps, not located at the semiconductor interface, since the gate noise is found to be uncorrelated with drain noise.

We studied environmental stability of top contact pentacene TFTs with active layer evaporated at different growth rates. We measured the transfer characteristics in vacuum and in air and after storing the devices in oxygen for several days. Different pentacene growth rates result in different grain size of active layer. This morphology difference influences the hysteresis of transfer characteristics induced by water absorption. On the contrary, aging effects on the transfer characteristics of pentacene O-TFTs, induced by oxygen diffusion into the active layer, are not related to structural characteristics of pentacene film.

(Polytetrafluoroethylene) PTFE-like films, deposited by using CHF3/Ar gas mixtures in a plasma reactor, have been used as encapsulation layers in pentacene thin film transistors. The PTFE-like encapsulation layers allow to carry out photolithographic processes without damaging pentacene film. However, the PTFE-like encapsulation layers are not effective in reducing hysteresis of electrical characteristics when measured in air. On the contrary, the degradation of the device electrical characteristics, induced by oxygen diffusion into pentacene film after storing the devices in air, is almost completely suppressed by the encapsulation with the PTFE-like films.

The presence of high electric fields at the drain junction in polycrystalline silicon (polysilicon) thin film transistors (TFTs), enhances several undesired effects, such as hot-carrier related instabilities and kink effect. In order to reduce the drain electric field, non-self-aligned (NSA) device architecture can be adopted. In this case, dopant activation and active layer crystallization are achieved at the same time by excimer laser annealing, resulting in a substantial lateral dopant diffusion. The gradual doping profile provides not only a reduction of the drain electric field, but also a channel length shortening. Therefore, an effective channel length (L eff ) has to be determined in such devices, in order to successfully design circuit applications. In this work, L eff and parasitic resistance (Rp) modulation effects have been investigated in both n- and p-channel NSA polysilicon TFTs. Three different parameter extraction methods, originally proposed for the crystalline MOSFETs technology, have been used and compared in order to extract L eff and R p , including: the "channel resistance" method; the "paired V g " method; the "shift and ratio" method. These methods indicate a channel length reduction up to 1 μm and a non negligible parasitic resistance effect. The reliability of the results of the three methods are discussed in terms of applicability of the underlying assumptions in the case of polysilicon TFTs and numerical simulations are used to support the analysis.

We have fabricated bottom contact pentacene TFTs on flexible polyimide substrate and silicon substrate using different passivation layers in order to reduce the electrical instability of pentacene devices, induced by water diffusion in the film, as evidenced by electrical measurements under different environments. Experimental data show that parylene passivation layer does not introduce appreciable degradation of device characteristics and allows standard lithographic process, but it is not an effective barrier for water diffusion. The encapsulation of pentacene TFTs with an additional acryl layer does not reduce the device sensitivity to the water, whereas devices encapsulated by a parylene/acryl/aluminum triple layer do not show increase of transfer characteristics hysteresis when measured in air.

The electrical instabilities in p-channel polysilicon TFTs induced by negative bias temperature stress (NBTS) and self-heating have been investigated. From NBTS experiments performed at different temperatures and gate bias, we derived an empirical relationship that provides the T and electric field dependence of the interface state generation. To explain the device instability related to self-heating we considered a spatially non uniform interface state distribution, as a non uniform transverse electric field is present during bias stress. The interface state distribution can be deduced using the empirical relationship, determined from NBTS experiments, and considering the spatial distribution of the oxide electric field, obtained from numerical simulations. Using the so determined interface state distribution it was possible to perfectly reproduce not only the transfer characteristics but also the asymmetry observed in the output characteristics, when source/drain contacts are reverted after bias stress.

In this work, we investigated self-heating related instability in polysilicon thin film transistors (poly-Si TFTs) fabricated on polyimide (PI) substrates. Indeed, when Joule heating becomes relevant, the temperature of the active layer can substantially rise, since the devices are fabricated on thermally insulating substrates. As a result, electrical instability is triggered and attributed to the generation of interface states, due to the Si–H bond breaking, and charge trapping into the gate insulator. In addition, by using 3-dimensional numerical simulations, coupling the thermodynamic and transport models, we analyzed the temperature distribution of the device under operating conditions and found that self-heating is more severe for devices fabricated on plastic substrates.

In this work we present a study of the electrical stability of self-aligned p-channel TFTs fabricated using excimer laser annealing. The electrical stability was tested performing bias stress experiments and accelerated stability tests and we found that the device characteristics were seriously degraded upon application of large negative gate bias. From extensive analysis of the phenomenon through numerical simulations, we found that the device degradation could be perfectly reproduced by positive charge injection into the gate oxide in narrow (300–400 nm) regions at the edges of the gate, near the source and drain contacts. From the present results we conclude that the observed degradation is closely related to the residual damage, induced by ion implantation, present in the gate oxide near the gate edges.

The optical diagnostic of spectroscopic ellipsometry is shown to be an effective tool to investigate the mechanism of excimer laser crystallization (ELC) of silicon thin films. A detailed spectroscopic ellipsometric investigation of the microstructures of polycrystalline Si films obtained on SiO2/Si wafers by ELC of a-Si:H and nc-Si films deposited, respectively, by SiH4 plasma enhanced chemical vapor deposition (PECVD) and SiF4-PECVD is presented. It is shown that ellipsometric spectra of the pseudodielectric function of polysilicon thin films allows to discern the three different ELC regimes of partial melting, super lateral growth and complete melting. Exploiting ellipsometry and atomic force microscopy, it is shown that ELC of nc-Si has very low energy density threshold of 95 mJ/cm2 for complete melting, and that re-crystallization to large grains of ∼ 2 μm can be achieved by multi-shot irradiation at an energy density as low as 260 mJ/cm2 when using nc-Si when compared to 340 mJ/cm2 for the ELC of a-Si films.

We present, for the first time, the application of the asymmetric fingered thin film transistor (AF-TFT) architecture to self-aligned p-channel TFTs for kink effect suppression. In AF-TFT the transistor channel region is split into two zones with different lengths ( L 1 > L 2 ) separated by a floating p + region. A fourth electrode, contacting the floating p + region, allowed us to measure the individual electrical characteristics of the two sub-TFTs. Output characteristics show that substantial kink effect reduction can be achieved when the sub-TFT placed at the drain end of the device has an L 2 ≪ L 1 . The electrical characteristics were analysed by using numerical simulations in the framework of the two-transistor model and we show that kink effect suppression arises from the operation in saturation regime of the source sub-TFT. The electrical characteristics of the fabricated p-channel AF-TFTs show a complete kink effect suppression, making these devices very attractive for current drivers in organic light emitting displays.

A unified drain current model of complementary (p- and n-type) organic thin film transistors (OTFTs) is presented. The model is physically based and takes into account the detailed properties of the organic semiconductor through the density of states (DOS). The drain current depends on the geometrical and physical parameters of the transistor, on the applied gate, drain and source voltages, and on the surface potential at the source and drain contacts. An analytical expression of the surface potential is derived. The proposed model is validated with the numerical calculations and the measurements of both p- and n-type OTFTs fabricated in a printed complementary technology. The provided analyses show that the model is continuous, accurate, and includes the main physical effects taking place in complementary organic transistors. Thanks to its analytical and symmetric formulation, it is suitable for the design of organic integrated circuits. Moreover, the unified physical picture provided by the model enables the extraction of the OTFTs physical parameters, thus it is a very powerful tool for the technology characterization.

In this work, we studied the effects of different thermal annealing on the electrical characteristics of non-self-aligned low-temperature p-channel polycrystalline silicon (polysilicon) thin film transistors. Different thermal treatments were performed after Al-gate formation at different temperature (200 degrees C, 250 degrees C, 350 degrees C and 450 degrees C) and annealing times. We found that optimal conditions were obtained at 350 degrees C, with transfer characteristics showing a subthreshold slope of 0.5 V/dec, field effect mobility > 100 cm(2)/Vs and threshold voltage around -3.5 V. Hot carrier induced degradation was also analyzed performing bias-stress measurements on devices annealed at 350 degrees C and at different bias stress conditions. The experimental data show that a maximum transconductance degradation is obtained for V,(stress) - V-t = -4 V while bias-stress at V-g = V-t and vertical bar V-g(stress)vertical bar >> vertical bar V-ds(stress)vertical bar did not produce appreciable changes in both transfer and output characteristics.

Integration of excimer laser annealing (ELA) process for power MOSFET devices is currently studied and evaluated within the frame of the IST project FLASH (Fundamentals and applications of laser processing for highly innovative MOS technology), funded by the European Commission. Final goal of the project is to show that ELA can be industrialized in the context of semiconductor device fabrication. In this work, the recent advancements of the FLASH project are described, including the formation of n + /p source junctions in both one and two dimensions. The experimental results are analysed by using a two-dimensional simulation program, specifically developed by the consortium. The simulation tool allowed a deeper insight of the ELA process and has been successfully used to optimise the process parameters. Finally, data on electrical integrity of the test devices are also presented, showing a yield for optimum ELA conditions up to 84%.

Parasitic resistance effects have been investigated in n-channel polycrystalline (polysilicon) silicon thin film transistors (TFTs). We show, both experimentally, and by using two-dimensional numerical simulations, that the transfer characteristics and, in particular, the transconductance are degraded by parasitic resistance effects, which are related to residual implant damage. In particular, we show that residual implant damage gives rise to two types of defected regions across the edges of the gate: the first, not overlapped by the gate, which mainly controls the parasitic resistance. The second, which is gate overlapped, can affect the behavior of the threshold voltage by modifying the classical short channel effect to the reverse short channel effect. The analysis demonstrates that for the fabrication of short-channel polysilicon TFTs an exact control of the implant-damaged regions is necessary.

The influence of channel doping on the threshold voltage of poly-Si thin film transistors (TFTs) has been investigated using both boron and phosphorus implants. For each dopant type, asymmetric TFT behaviour was seen between enhancement and depletion mode TFTs, with the enhancement mode TFTs always showing a greater shift in threshold voltage for a given dose. From a detailed analysis of the boron-doped samples, using a two-dimensional device simulator, it was demonstrated that the results could be best explained in terms of a non-symmetric density of states, in which the deep trapping state density in the lower half of the band-gap increased with increasing boron concentration. This is the first reported observation in poly-Si of shallow level dopants also introducing deep levels in the majority carrier half band-gap.

In this work we present the electrical characterization of non self-aligned p-channel thin film transistors fabricated by using laser doping technique for source/drain contact formation and gate oxide deposited at room temperature by Electron Cyclotron Resonance Plasma Enhanced Chemical Vapour Deposition. These techniques are suitable for a very low temperature process for TFT fabrication. The output characteristics show a current increase at high drain voltage, (“kink” effect) rather moderate, if compared to self aligned polysilicon TFTs, probably due to the gradual doping profile induced by laser doping process. After bias stress at low gate voltage and high drain voltage condition a strong reduction of kink current has been observed in the output characteristics at high drain voltage, whereas minor changes has been observed in the transfer characteristics. This behaviour is similar to what observed in n-channel Gate Overlapped Thin Film Transistors. In the high gate voltage and high drain voltage bias-stress condition we observed only a rigid shift of the transfer characteristics probably related to charge injection in the gate oxide, while subthreshold slope remains constant.

Short channel effects have been investigated in n-channel polysilicon thin film transistors. Transconductance degradation has been observed when reducing the channel length L and this effect has been explained with the presence of a parasitic resistance related to residual implant damage. Threshold voltage slighlty decreases for channel length around L=1 μm and simulations confirm that the roll-off of the threshold voltage is expected for L

Silicon dioxide films have been deposited at temperatures less than 270 °C in an electron cyclotron resonance (ECR) plasma reactor from a gas phase combination of O2, SiH4 and He. The physical characterization of the material was carried out through pinhole density analysis as a function of substrate temperature for different μ-wave power (Ew). Higher Ew at room deposition temperature (RT) shows low defects densities ( 10 MV/cm are observed from ramps I–V. Moreover, from high frequency and quasi-static C–V characteristics we studied interface quality as function of annealing time and annealing temperature in N2. We found that even for low annealing temperature (200 °C) is possible to reduce considerably the interface state density down to 5 × 1011 cm−2 eV−1. These results show that a complete low-temperatures process can be achieved for the integration of SiO2 as gate insulator in polysilicon TFTs on plastic substrates.

We report on the correlation between structural and electrical properties of pentacene thin film transistors fabricated by the novel supersonic molecular beam epitaxy (SuMBE) technique. We exploited the ability of SuMBE that, through the control on the molecular precursors in the beam, allows improving the quality in terms of structure and morphology of the semi-conducting thin films compared to the more standard OMBE growth. Different growth conditions were explored to find the better range of beam parameters improving the performance of the TFT device whereas the quality of the films grown was studied by atomic force microscopy. We show that the initial kinetic energy of the pentacene molecule strongly affects both the morphology of the films and the electrical properties of the devices that result to be strongly correlated. With our FET devices prepared, on SiO 2 /Si and top Au contact, we achieved the very promising field effect mobility larger than 0.5 cm 2 V −1 s −1 for films grown at room temperature at a pentacene kinetic energy of about 5.5 eV that are characterized by large crystalline grains (>2 μm).

Different drain field architectures have been recently investigated to reduce field-enhanced effects in conventional self-aligned polysilicon thin-film transistor (TFT) architecture, induced by the intense electric fields at the drain junction. Among these, gate overlapped lightly doped drain (GOLDD) architecture has been shown to be effective in reducing the drain field in both on and off states of the TFT, without introducing appreciable series resistance effects. In this paper, we investigate the electrical characteristics, both in the on- and in the off-regime, of GOLDD polysilicon TFTs, made with different LDD doses, by combining experimental data with two-dimensional (2-D) numerical analysis. We also demonstrate that both the on-state and off-state features of the GOLDD structure can be readily understood in terms of a simple, new model, based upon two TFTs series. This is consistent both with the experimental data and the results of full 2-D simulations. This paper not only clarifies the dependence of kink effect, leakage current, and series resistance upon the LDD-doping, but also provides the guidelines to optimize physical parameters of GOLDD TFTs.

The analysis of the grain size (GS) vs. energy density of silicon films irradiated with long pulse (LP) (150–200 ns) excimer laser has revealed that the maximum GS achievable is limited to 250–350 nm. In general, maximum GS occurs when the so-called super lateral growth (SLG) mechanism is triggered (almost complete melting) and in short-pulse (30 ns) irradiated films the maximum GS can be well above 1 μm. In order to clarify this discrepancy between the SLG regimes observed with short and LP irradiations, we performed an experiment with a LP (170 ns) excimer laser (HERCULES), having opportunely profiled the energy density to a ‘ramp’ distribution. In this way it was possible to have a continuous energy distribution and by analysing the structural (SEM) and topographical (AFM) properties it was possible to produce an accurate picture of their dependence upon the laser energy density. We were able to identify the SLG regime, with GS up to 1.5 μm and energy window Δ E / E =0.002, pointing out the difficulties in observing SLG in LP irradiations.

Structural properties of thin polycrystalline silicon films, crystallized by single shot excimer laser annealing at different laser energy densities, have been investigated. Formation of disk structures has been observed in a wide range of energy densities, from complete melting down to 180 mJ/cm 2 . These structures have been correlated to the lateral growth of grains starting from the small grains present in the central regions of the disks. We propose a new crystallization scenario for energy densities below the complete melting. In this framework, the recalescence effect plays an important role while the super lateral growth-regime is no longer a particular crystallization condition but simply represents the upper energy density limit of partial melt crystallization regime.

Grain size control in excimer laser crystallization has stimulated a growing activity aiming to locate large silicon grains in the thin-film transistor (TFT) channel. We present a new technique that can be applied to control the lateral growth (LG), by using thickness spatial modulation, and that can be used to the fabrication of high performance polysilicon TFTs. In particular LG can be triggered when thinner regions are completely melted and thicker regions are partially melted. Thicker regions are formed by a two layer structure of doped and undoped material while thinner regions are obtained by removing the doped layer. In this way the thicker regions can be used as source–drain regions of the device while the thinner regions, where large grains are formed, can be used as channel regions. In order to control the LG, different doped and undoped layer thickness have been investigated. The structures have been irradiated at different laser energy densities and we observed that the thicker regions became highly conductive (∼70 Ω/□), due to doping activation and redistribution induced by the melt/regrowth process, while triggering of the LG in the thinner region has been observed within an opportune energy density window. As the LG extension is limited at approximately 1 μm, active channel region ⩽2 μm could be formed. The proposed process is very attractive for polysilicon TFTs as LG-control and doping activation can be simultaneously achieved.

Hot-carrier induced degradation is a main issue in the electrical stability of polysilicon TFTs and drain field relief architectures have been introduced, such as lightly doped drain (LDD) and gate overlapped LDD (GOLDD), to improve the stability. Bias-stress experiments were performed on both LDD and GOLDD structures, biasing the devices above pinch-off at constant V g and different V ds . While the LDD structure presented considerable hot-carrier induced degradation, GOLDD devices were characterised by a very high electrical stability. To explain such a difference in electrical stability, we first analysed the spatial distributions of the electric fields, which are lower in GOLDD structures. In addition, we developed a new model to describe the hot-carrier induced degradation, based on the correlation between hot carrier injection currents and interface state generation. Indeed, hot carrier injection is known to produce interface states and oxide trapped charge, and, depending upon their spatial distribution, can strongly influence the local electric fields as well as the current. The proposed model nicely reproduces the degraded characteristics, thus providing indications on the spatial distribution of the generated interface states.

A novel fabrication process for low-temperature (

In this work, the design of a high-frequency AM demodulator in a printed complementary organic technology is presented. The behaviour and the variability of printed circuits are predicted by means of accurate transistor modelling, statistical characterization, and Monte Carlo simulations. The effectiveness of the design approach is readily verified by comparing measurements and simulations of simple digital blocks as well as two differential amplifiers. These amplifiers can be used as continuous-time comparators in the demodulator. In addition, the possibility of high-frequency rectification using the printed organic TFTs is shown by providing the experimental results of an envelope detector measured under different load and input conditions. All the measurements are performed in air. Finally, the simulation of a complete AM demodulator system including the measured blocks is demonstrated. © 2014 Elsevier B.V. All rights reserved.

Low-frequency noise has been investigated in self-aligned (SA) and gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors (TFTs). We found that, at low Vds, both device structures are characterised by 1/f noise, originating from carrier number fluctuations. However, when the SA devices were operated in the kink regime, an excess noise was observed, in contrast to GOLDD TFTs. This has been explained by attributing the excess noise to supplemental oxide charge fluctuations induced by hot-carrier injection into the gate oxide. By using two-dimensional numerical simulations, we show that the hot-electron emission current in SA polysilicon TFTs is much higher than in the GOLDD structure.

Self-heating-related instabilities have been studied in p-channel polycrystalline-silicon thin-film transistors. The spatial distribution of the interface-state and fixed-oxide-charge densities generated during self-heating experiments has been analyzed and quantitatively determined by using negative-bias temperature stress experiments and 2-D numerical simulations. In addition, the observed asymmetry in the output characteristics with respect to source/drain contact reversal is also perfectly reproduced, confirming the validity of the proposed model.

Hot-carrier effects on both the electrical characteristics and the noise performance in polycrystalline silicon thin film transistors are analysed. The devices were fabricated by using a combined solid phase crystallization (SPC) and excimer laser annealing (ELA) process, combining the beneficial aspects of the two techniques. Hot-carrier degradation results in the formation of both interface states, which have been evaluated through the analysis of the sheet conductance and of oxide traps near the insulator/semiconductor interface, as evidenced by the 1/f noise measurements. Oxide traps are calculated evaluating the flat band voltage spectral density associated with interface charge fluctuations in the damaged part of the interface. A strong correlation between interface state and oxide trap densities has been found, suggesting a common origin for the generation mechanism of the two types of defects.

Polysilicon thin-film transistors (TFTs) are of great interest for their circuit application in the large area microelectronics. A successful circuit design requires an accurate prediction of the circuit performances, which in turn needs a proper modeling of the electrical device characteristics. In this present work the specific aspects of the anomalous current increase in the output characteristics, often called the “kink” effect, are analysed. A new procedure to determine the excess current is presented and we analysed the excess current for different gate voltages, temperatures and device geometries. We show that, from the parameters that can be extracted by analysing a reduced set of experimental data, the excess current can be easily predicted for any bias and temperature condition and also for devices with different geometries. These results can be used to further up-grade the modeling of the electrical characteristics of polysilicon TFTs in circuit simulators.

Many functional properties of organic semiconductors, such as charge transport, are regulated by structural order. The control of crystallinity, orientation, and positioning of crystals—the highest form of order—inside devices presents an extraordinary opportunity to fully exploit their potentialities. On page 2387, M. Cavallini and co-workers demonstrate direct patterning of crystals of conjugated molecules onto devices, with defined shape and controlled size

Contact effects have been analyzed in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source-drain contacts. In these devices, contact effects lead to an apparent decrease of the field effect mobility with decreasing L and to a failure of the gradual channel approximation (GCA) in reproducing the output characteristics. Experimental data have been reproduced by two-dimensional numerical simulations that included a Schottky barrier (Phi(b) = 0.46 eV) at both source and drain contacts and the effects of field-induced barrier lowering. The barrier lowering was found to be controlled by the Schottky effect for an electric field E < 10(5) V/cm, while for higher electric fields we found a stronger barrier lowering presumably due to other field-enhanced mechanisms. The analysis of numerical simulation results showed that three different operating regimes of the device can be identified: (1) low vertical bar V-ds vertical bar, where the channel and the Schottky diodes at both source and drain behave as gate voltage dependent resistors and the partition between channel resistance and contact resistance depends upon the gate bias; (2) intermediate V-ds, where the device characteristics are dominated by the reverse biased diode at the source contact, and (3) high vertical bar V-ds vertical bar, where pinch-off of the channel occurs at the drain end and the transistor takes control of the current. We show that these three regimes are a general feature of the device characteristics when Schottky source and drain contacts are present, and therefore the same analysis could be extended to TFTs with different semiconductor active layers.

Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon thin-film transistors (TFTs), fabricated with a spacer technology and providing submicron (0.35 μm) LDD regions, have been analyzed. Device characteristics show negligible series resistance of the LDD region while effective drain field relief has been demonstrated by a reduced kink effect and off-current, if compared to conventional self-aligned (SA) devices. Short channel effects are also mitigated by the LDD region, while substantial reduction in the hot-carrier induced instability is found, when compared with conventional SA devices. Optimum doping dose of the LDD region has been identified to be 9 × 1012 cm2.

The electrical properties of untreated and hydrogen-irradiated GaAs${}_{1\ensuremath{-}x}$N${}_{x}$ are investigated by conductive-probe atomic force microscopy (CP-AFM). After hydrogen irradiation, the resistance R of GaAs${}_{1\ensuremath{-}x}$N${}_{x}$ increases by more than three orders of magnitude while that of a N-free GaAs reference slightly decreases. Thermal annealing at 550 \ifmmode^\circ\else\textdegree\fi{}C of H-irradiated GaAs${}_{1\ensuremath{-}x}$N${}_{x}$ restores the pristine electrical properties of the as-grown sample thus demonstrating that this phenomenon is fully reversible. These effects are attributed to the nitrogen-hydrogen complexes that passivate N in GaAs${}_{1\ensuremath{-}x}$N${}_{x}$ (thus restoring the energy gap of N-free GaAs) and, moreover, reduce the carrier scattering time by more than one order of magnitude. This opens up a route to the fabrication of planar conductive/resistive/conductive heterostructures with submicrometer spatial resolution, which is also reported here.

Self-heating-related instabilities have been investigated in p-channel polycrystalline-silicon thin-fllm transistor, showing an anomalous transconductance (gm) increase. The gm increase is a fingerprint of edge effects, resulting from a buildup of positive trapped charge in the gate oxide at the channel edges. This was confirmed by the annihilation of such positive charges obtained by sequential hot-carrier bias-stress experiments. From the analysis of the edge effects in devices with different channel lengths, we were able, using 2-D numerical simulations, to deter mine the size of the defected edge regions to be 400 nm.

Carrier quantum confinement has been achieved in dilute nitrides by controlling the peculiar kinetics of hydrogen in those materials. ${\text{GaAs}}_{1\ensuremath{-}x}{\text{N}}_{x}/{\text{GaAs}}_{1\ensuremath{-}x}{\text{N}}_{x}:\text{H}$ planar heterostructures have been fabricated by deposition of submicrometer titanium wires (width $w=485$, 175, and 80 nm) on ${\text{GaAs}}_{1\ensuremath{-}x}{\text{N}}_{x}$ and subsequent H irradiation. Continuous-wave photoluminescence, PL, in ensembles of ${\text{GaAs}}_{1\ensuremath{-}x}{\text{N}}_{x}/{\text{GaAs}}_{1\ensuremath{-}x}{\text{N}}_{x}:\text{H}$ heterostructures shows a blueshift of the PL peak energy and a marked increase in the PL radiative efficiency with decreasing one of the wire dimensions down to the nanometer-scale length. Concomitantly, time-resolved microphotoluminescence in single structures exhibits a pronounced slow down of carrier relaxation toward the ground state. All these results, supported by numerical calculations of H diffusion profiles, indicate that carrier quantum confinement can be achieved by H engineering of dilute nitrides.

Hydrogenated amorphous silicon thin-film transistors have been fabricated by using electron-beam lithography to define channel length down to 0.2 μm. In this way it has been possible to evidence, for the first time, short-channel effects on these devices. In this work two short-channel effects occurring in 0.2 μm devices are discussed: degradation of the off-current as the source-drain voltage is increased and avalanche increase of the drain current for high source-drain voltage.

Negative bias stress experiments on a-Si:H/a-SiO 2 Thin Film Transistors show that the instability is predominantly related to charge injection in the gate insulator. We propose that charge injection is occurring in a defected region of the gate insulator adjacent to a-Si:H, caused by the effect of activated hydrogen on a-SiO 2 surface during deposition. To investigate the hydrogen influence, we have studied low-energy (100 eV) hydrogen-ion and Ar-ion bombardment effects on a-SiO 2 using synchrotron radiation photoemission spectroscopies. Comparing the two kind of treatments, we show that hydrogen treatment produces predominantly Si-H defects, which are observed to induce gap states in a-SiO 2 .