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This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (V CM ). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038 m m 2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient dynamic-time current comparator for current mode signal processing. The proposed circuit utilizes a switched feedback-based inverter and a clock-shaping circuit. The switched feedback-based inverter can detect the polarity of the sensed current from the current subtraction circuit. While the clock-shaping circuit can manage the power consumption. Since the proposed current comparator exhibits a high sensitivity to ultra-low input current with a low input offset, it can be exploited in a current mode successive-approximation-register analog-to-digital converters for a wide range of wearable applications. Moreover, a design methodology for an efficient and robust current comparator is presented. The circuit is designed and simulated in TSMC 0.13 µm CMOS technology, and occupies a silicon area of 7834 µm2. The proposed current comparator consumes a power of 14 µW with a single power supply of 1.2 V. It provides a resolution of 2 nA, and a delay of 4.6 ns. Moreover, the post-layout simulation results indicate a good agreement compared to the prior art. [ABSTRACT FROM AUTHOR]

This paper presents a performance evaluation of an ultra low-voltage non-clocked voltage comparator, designed and fabricated in a standard twin-well 130 nm CMOS technology. The comparator can handle the input voltage within rail-to-rail range and is capable of working in temperature range from −20 to 85 °C and with power supply voltage as low as 0.4 V. The comparator is intended to be employed in an on-chip energy harvester system with minimized quiescent current consumption. So-called g m / I D low-voltage design methodology in combination with the bulk-driven design approach have been selected in the circuit topology. The measurement results obtained from fabricated prototype chips, including static and dynamic parameters, are presented and discussed as well. An excellent correlation between simulations and the measured bench data has been observed with the supply voltage value of 0.6 V, while slightly less tight correlation has been reported for V DD = 0.4 V. Anyhow, simulations and measurements both confirm that the presented silicon-proven comparator topology is capable of reliable operation with power consumption within nW range. [ABSTRACT FROM AUTHOR]

This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 µW using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications. [ABSTRACT FROM AUTHOR]

This paper presents a high-speed common-mode insensitive two-stage regenerative comparator designed for low supply voltage applications. The proposed comparator features a doubled transistor latch that enables rail-to-rail operation, which is pioneered to the best of the author's knowledge. The voltage swing of output nodes of the pre-amplifiers is limited to reduce the power consumption. This limitation boosts the regeneration speed of the doubled transistor latch. The proposed comparator realized by a standard 65 nm CMOS technology. The post-layout simulation results corroborate that the proposed comparator with 50 MHz sample rate and 0.6 V supply voltage dissipates 3.4 µW power, and occupies 168 µm2 area. Also, the offset voltage variation within the full common-mode range can be below 2 mV. In a worst-case scenario compared to the conventional single-stage comparator, the proposed comparator improves delay and energy efficiency by more than 80%. Considering its overall performance, this energy-efficient comparator is suitable for all low supply voltage applications, including Internet of Things (IoT), successive approximation registers analog-to-digital converters (SAR ADCs), and biomedical implants. [ABSTRACT FROM AUTHOR]

Abstract A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 μm technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC. [ABSTRACT FROM AUTHOR]

A fully integrated RC oscillator is presented. A current-capacitor-based voltage average feedback(IC-VAF) technique is proposed to improve frequency stability. A trip voltage adjustable invert technique(TVAI) is proposed to avoid using comparators, thus saving power and area. The simulation results show that the power consumption is 24. 72 μ W at 1.2 V power supply, and the temperature coefficient is 25 ppm/°C from −40 °C to 125 °C, The calculated figures of merits(FOMs) F O M 1 and F O M 2 are 1. 24 nW / kHz and 157. 2 dBc / Hz , respectively. The oscillator occupies an active area of 0. 027 mm 2 in a 55 nm standard CMOS process. [ABSTRACT FROM AUTHOR]

The article addresses a novel topology of analog voltage comparator capable of processing the input voltage in rail-to-rail range. We propose two different innovative comparator topologies. One topology is employing a standard "gate-driven" (GD) control of MOS transistors and is designed in 65 nm CMOS technology. The other one, designed in 130 nm CMOS technology, uses rather unconventional "bulk-driven" (BD) control of active devices in the circuit. Each presented circuit topology has its own pros and cons. However, both are suitable and actually aimed for ultra low-voltage (ULV) and/or ultra low-power (ULP) applications. The proposed comparator designs have been extensively analyzed for robustness and parameter stability across all fabrication process corners, wide temperature range (from −20 ° C to 85 ° C) and for random process variations as well. Both presented comparator designs can reliably operate with power consumption in nano-watt range without any fuse trimming or calibration, as the proof of concept has been confirmed by measurements performed on chip prototypes. [ABSTRACT FROM AUTHOR]

In this paper a new low-power high-speed offset-compensated dynamic latched comparator is presented. The proposed comparator uses a two-stage charge-steering preamplifier to achieve high pre-amplification voltage gain. Higher input voltage range of the latch stage significantly reduces the delay time of the latch and relaxes the need for high current in the regeneration process which ensures low-power structure. In addition, a new digitally controlled offset cancellation circuit based on the current-steering structure is used to reduce the offset of comparator. Offset voltage reduction in the startup time is the key advantage of the proposed calibration technique which does not require refreshing the offset cancellation process. Post-layout simulation results in 0.18 µm standard TSMC CMOS process show that the designed comparator dissipates 135 µW of power consumption from a 1.2 V supply voltage and has the 1 mV accuracy while operating at 1 GHz clock frequency. The power and delay time of the proposed comparator are less than about 10% of the new state-of-the-art comparator. Furthermore, from the Monte-Carlo analysis, the standard deviation of the input referred offset voltage in typical process corner and temperature is obtained about 17.53/1.09 mV before and after offset cancellation, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a capacitor sample-hold oscillator architecture which realizes temperature-stabilized operation without a precise reference generator by using a capacitor to sample-hold the peak charge voltage of the previous phase as the reference for the current phase. Due to its dual-way charging and discharging structure, the peak charge voltage for each phase will eventually stabilized around half the supply voltage. The frequency of the oscillator depends on the RC time constants of capacitors charging (discharging) across passively-temperature-stabilized resistive elements and the comparator delay time. By analyzing the temperature characteristics of the comparator delay time and using temperature compensated bias currents to achieve temperature stabilization of the delay time, this architecture improves the overall temperature stability. This architecture has been designed and verified in 0.18-μm CMOS technology. The simulation results demonstrate this design consumes 7.99 μW from a 1.8 V supply voltage at 58.9 kHz and achieves a temperature stability of best 22.19 ppm/℃(TT Corner) from −40◦C to 90◦C, and frequency variations of ± 0.3 % for supply changes from 1.25 to 1.8 V. [ABSTRACT FROM AUTHOR]

A single-layer 2-D substrate integrated waveguide (SIW) monopulse slot antenna is proposed in this paper. By adopting the dual-mode monopulse comparators (DMCs), the feeding network exhibited excellent amplitude-phase consistency and high isolations between input ports. Additionally, the structure of the proposed antenna is effectively simplified by integrating the feeding network with the radiation part on a single-layer substrate. Based on it, a monopulse antenna prototype is fabricated and measured. The measured results show that the −10 dB shared impedance bandwidth of 4 ports is 2.05 % (9.65–9.85 GHz) and the isolations between ports are better than 25 dB. The measured gain of the sum pattern is 13.93 dBi at 9.75 GHz, and the null depths of the difference patterns are lower than −30 dB. [ABSTRACT FROM AUTHOR]

This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V. [ABSTRACT FROM AUTHOR]

A state-of-the-art energy-efficient digital-to-analog converter (DAC) switching scheme suitable for single-ended successive approximation register (SAR) analog-to-digital converter (ADC) is proposed in this paper. The proposed scheme synthesizes two reference voltages V r e f and V q to generate relevant voltage levels. The reference voltage V q is a quarter of the V r e f. To ease logic design, the V r e f is only utilized during the third phase of conversion with the MSB capacitor of each DAC. The proposed scheme reduces DAC's average switching energy and the area by 94.44 % and 50 % in comparison with the conventional single-ended scheme. Furthermore, a novel 3-stage common-mode insensitive regenerative comparator is proposed to reduce non-linearity errors caused by common-mode voltage variations of DAC. The proposed single-ended ADC is simulated in a standard 65-nm CMOS technology with a resolution of 8-bit and sampling rate of 25 MS/s. The simulation results corroborate that the ADC consumes 124 µW power with 1.2 V supply voltage and attain a 7.23 effective number of bits, resulting in a 33fJ/conversion step FOM. [ABSTRACT FROM AUTHOR]

A successive approximation register (SAR)-assisted digital-slope analog-to-digital converter (ADC) with an "8-bit + 4-bit" hybrid topology is presented. In the coarse quantization with an 8-bit SAR ADC, a voltage-controlled oscillator (VCO)-based comparator with a reset-in-time function is proposed for energy saving. Once the phase detector generates the comparison result, the VCO resets to significantly reduce the power of the comparator. Moreover, in a 4-bit fine digital-slope ADC, the delay cell is reused from the VCO-based comparator to the delay line; thus, the area of the entire ADC is reduced to a certain extent. The proposed ADC is designed using 0.18-µm CMOS technology and can operate at a supply voltage as low as 0.6 V. The ADC achieves a signal-to-noise-and-distortion ratio of 70.53 dB with a sampling rate of 20 kS/s and an input frequency of 9.74 kHz. The power consumption is only 330 nW, and the Walden figure-of-merit is 6.02 fJ/conversion-step, making it suitable for low-supply low power internet-of-things applications. [ABSTRACT FROM AUTHOR]

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage , is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing PMOS transistors at the input of the comparator. [ABSTRACT FROM AUTHOR]

This paper presents an evolutionary approach to design CMOS Two-Stage Comparator (TSC) and CMOS Folded Cascode Operational Trans-conductance Amplifier (FCOTA) using simplex particle swarm optimization (Simplex-PSO) method. The simplex particle swarm optimization (Simplex-PSO) is a swarm intelligent based evolutionary computation method. Simplex-PSO is the hybridization of Nelder–Mead Simplex method (NMSM) and Particle Swarm Optimization (PSO) without the velocity term. The Simplex-PSO has fast optimizing capability and high computational precision for high-dimensionality functions. This work has focused on the optimization of the area, power and has improved all other performance parameters of the CMOS TSC and CMOS FCOTA with minimum computational time. The proposed Simplex-PSO based circuit optimization technique is relieved from the inherent drawbacks of premature convergence and stagnation, unlike Differential Evolution (DE), Harmony Search (HS). The simulation results prove that Simplex-PSO yields the optimized result with improved functionality. Simulation results obtained for CMOS TSC and CMOS FCOTA prove the effectiveness of the proposed Simplex-PSO method based approach over the reported DE, HS, and PSO in terms of convergence speed, design specifications and design objectives. The optimally designed TSC and FCOTA circuits, individually, occupy the least MOS areas and dissipate the least powers. The simulation plots and results are shown to have the improved performance parameters compared with those of other reported literature. Validation of the design is carried out by Cadence version 5 (IC 5.10.41) of TSMC 0.35 μm technology. [ABSTRACT FROM AUTHOR]

This paper presents a boost converter with variable output voltage and a new maximum power point tracking (MPPT) scheme for biomedical applications. The variable output voltage feature facilitates its usage in a wide range of applications. This is achieved by means of a new low-power self-reference comparator. A new modified MPPT scheme is proposed which improves the efficiency by 10%. Also, to further increase the efficiency, a level converter circuit is used to lower the V dd of the digital section. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. Using this approach, a thermoelectric energy harvesting circuit has been designed in a 180 nm CMOS technology. According to HSPICE Simulation results, the circuit operates from input voltages as low as 40 mV and generates output voltages ranging from 1 to 3 V. A maximum power of 138 μW can be obtained from the output of the boost converter which means that the maximum end-to-end efficiency is 52%. [ABSTRACT FROM AUTHOR]

A dynamic latched comparator with a programmable tail transistor is proposed. The tail transistor is divided into N branches that could be enabled or disabled to allow optimizing the delay and offset of the comparator across process, voltage, and temperature variations. As a proof of concept, a 2.5 GHz design example with 4 branches is carried out in a 65 nm CMOS technology. The design utilizes digital calibration circuitry to automatically set the number of enabled branches under given operating conditions, with the goal to minimize the offset while achieving the target speed. Such offset reduction helps in efficiently cancelling the offset with simple overhead circuitry. Simulation results show that the offset and power consumption of the proposed comparator in the fast-fast corner are reduced by 41% and 26% respectively compared to a conventional StrongARM design targeting the same speed. [ABSTRACT FROM AUTHOR]

A bipolar low-power pipeline time-to-digital converter (TDC) for digital phase-locked loop (DPLL) applications is implemented with six 1-bit cascaded stages. The stages consist of a compensated ×2 time amplifier (TA) using the time-to-current conversion technique, two modified SR-latch-based time comparators, and a static logic called offset-64, which aligns the output bit of the stage to create a 7-bit output code without the zero-gain issue. The presented mathematical analyses reveal the low sensitivity of the proposed TDC to the offset of the TA. The layout of the proposed TDC was designed in a 65 nm CMOS technology. Post-layout simulation results demonstrate a 1.7 ps time resolution and power consumption of 450 μW for a sampling frequency of 125 MS/s. [ABSTRACT FROM AUTHOR]

This paper briefs a design of N-bit binary search (BS) analog to digital converter (ADC) employing only 'N/2' comparator using double activation reusable comparator methodology. By inserting smart switching network, the 4 comparators are getting activated twice and reused to generate the 8-bit output pattern for proposed 8-bit ADC. In addition to this, the asynchronous mode has been adopted for activation of comparators in sequential manner to optimize the power consumption. The proposed ADC dissipates 20.4 mW of power with a supply voltage of 1.8 V and achieves conversion rate of 123.15 MSPS, SNR of 45.1 dB, SFDR of 52.7 dBc and Walden figure of merit (FOM) of 13.8 pJ/conv-step. [ABSTRACT FROM AUTHOR]

A compact multi-layer substrate integrated waveguide (SIW) monopulse antenna array operating at X-band is proposed. The structure consists of four stacked layers, including one layer for the radiating 4 × 4 rectangular microstrip antenna elements and two SIW layers for the comparator network. The sum and difference modes provide orthogonal radiation patterns in the azimuth and elevation planes. The two SIW layers of the comparator network feature a compact multi-feed design while maintaining high isolation between the antenna ports. To validate the proposed antenna concept, silmulations and measuremets are carried out. The obtained resuts show good performnces, a −10-dB impedance bandwidth of 13.45 % (9.35–10.7 GHz) for the sum and difference ports, better than 30 dB isolation between the antenna ports, the difference radiation patterns better than −38 dB null-depth. The comparison between the simulated and measuremed results shows a good agreement. [ABSTRACT FROM AUTHOR]

This article presents a fully-synthesizable digital voltage regulator for applications with extremely low power consumption. The proposed design uses a synthesizable controller (DLDOC) to detect load fluctuations and control a tri-loop structural design. This tri-loop structure minimizes the ripples on output voltage (V OUT) and provides a fast-transient response (TR). This structure decreases the length of bi-directional shift register (Bi-SR) which reduces the overall power consumption. A quivering control is introduced to minimize the V OUT oscillations in steady-state. To demonstrate this design using CMOS standard-cells, a fully-synthesizable comparator (FS-comp) is utilized. A tri-state buffer array (TBA) is employed instead of conventional PMOS switch array to make this design fully-synthesizable. A pattern detection mechanism is used to switch between different loops. The proposed prototype occupies 6394 µm2 area in 45 nm CMOS technology. This design is implemented using conventional synthesis and place-and-route (P & R). For a supply voltage (VDD) of 0.5–1 V, a regulated V OUT is attained with a dropout voltage of 50 mV. At 10 MHz clock frequency, the proposed LDO achieves a quiescent current (I Q) and fast-TR of 2.2 µA and 300 ns, respectively. A maximum current efficiency (C.E.) of 99.98% is attained with output ripples < 1 mV. [ABSTRACT FROM AUTHOR]

A high-resolution dynamic voltage comparator with an input signal dependent power down technique for low power applications is presented here. Without affecting the resolution, a preamplifier stage has been removed from the proposed dynamic voltage comparator in order to reduce the power consumption and its delay. In this design, an input signal dependent power-down technique is used. The proposed design consists of NMOS & PMOS Input Stage Dynamic Voltage Comparator with power down (NISDVC_PD & PISDVC_PD) along with multiplexers for full rail-to-rail input swing. One out of PISDVC_PD and NISDVC_PD is active at a time to reduce power consumption. The proposed comparator has been designed using SCL 180 nm CMOS technology at 1.8 V. The simulation results of the proposed design show that the power consumption and delay is 94.1 µW and 208.28 ps at 500 MHz whereas at 2 GHz the value of the power consumption and delay is 147.7 µW and 212.5 ps, respectively. Furthermore, the offset voltage is obtained as 185.3 µV and the sensitivity of the circuit is 0.15 µV. [ABSTRACT FROM AUTHOR]

This paper presents a high-sensitivity high-speed dynamic voltage comparator, which is a key component for low power CMOS mixed signal applications. The proposed dynamic comparator employs ten transistors with only one cross-coupled latch to reduce the circuit complexity. The parallel clocked input switches reduce parasitic resistance in the latch ground path that results in a significant decrease in latch delay time. In addition, a symmetric, three stacked transistor, single stage architecture reduces the process variation effects, increases input sensitivity and provides more head room for low power-supply applications. The proposed design is implemented in 90 nm CMOS with 1.2 V power supply and 0.6 V reference voltage, and it provides 30 μV resolution, 105.6 μW power consumption at 2 GHz clock frequency. [ABSTRACT FROM AUTHOR]

• A scheme for power consumption reduction in a conventional comparator is presented. • The proposed scheme turns off the preamplifier, to reduce the power consumption. • The power-delay product is optimized using dynamic inverters. • The input referred offset is compensated using an offset cancellation scheme. Dynamic comparators are an essential part of low-power analog to digital converters (ADCs) and are referred to as one of the most important building blocks in mixed mode circuits. The power consumption and accuracy of dynamic comparators directly affects the overall power consumption and effective number of bits of the ADC. In this paper, an early shutdown approach is proposed to deactivate the first stage preamplifier at the suitable time. Furthermore, a time domain offset cancellation technique is incorporated to reduce offset effects. With the proposed method power consumption can be reduced in low power high precision dynamic comparators. The proposed method has been simulated in a standard 0.18 µm CMOS technology and the results confirm its effectiveness. The proposed circuit has the ability of reducing the power consumption by 21.7% in the worst case, while having little effect on the speed and accuracy in comparison with the conventional methods. The proposed comparator consumes only 47 µW while operating at 500 MHz. Furthermore, Monte Carlo evaluations showed that the standard deviation of the residual input referred offset was 620 µV. [ABSTRACT FROM AUTHOR]

• The simplicity of the proposed oscillator hides very complex dynamic behaviors. • This novel oscillator can be called "Voltage-Tunable Colpitts Oscillator" (VTCO). • The voltage comparator is responsible for the complex dynamics of the model. • The reference voltage source of the circuit acts as a reversible control paramete. • A new dynamic phenomenon named "antimonotonicity-reversible" is observed. Designing simple chaotic circuits with complex dynamic behaviors that can generate coexisting and hidden attractors has attracted much interest recently. In this paper, a new voltage-tunable Colpitts oscillator based on a two op-amps voltage comparator that can exhibit self-excited and hidden behaviors is proposed. Only the intrinsic nonlinearity of the voltage comparators is responsible for the complex dynamic behaviors of the proposed model and no additionally nonlinear devices are required. In this circuit, a reference voltage source acts as a reversible control parameter, since it can be varied indifferently in a positive or negative direction. Basic dynamic properties of the proposed Colpitts oscillator are investigated and the entire dynamics is analyzed numerically based on standard nonlinear analytical tools. Very rich dynamic behaviors and phenomena are reported, including; hidden attractors, period-doubling bifurcations, antimonotonicity, bursting oscillations, offset-boosting, and coexistence of multiple attractors for a set parameter values of the system. PSpice simulations are also carried out to validate theoretical and numerical results. Furthermore, the feasibility of the proposed Colpitts oscillator is confirmed through a practical realization which is in good agreement with the theoretical results. [ABSTRACT FROM AUTHOR]

In this paper, an ultra high speed dynamic comparator is presented. The PMOS pass transistors are used in the latch and pre-amplifier stage of the comparator. At the regeneration phase, the latch is activated faster with sufficient preamplification gain and very less power consumption. Meanwhile, a cross-coupled set up of NMOS transistors in latch stage enhances the gain and speed. Unlike the previous reported comparator, the proposed dynamic circuit avoids the extra power consumption as well as delay, and establishes the optimum offset and kickback noise. The benefits in delay and power are verified with the help of analytical expressions, meticulous Monte Carlo simulations and process corner analysis in CADENCE SPECTRE at 90 nm CMOS technology. The simulation results validate that the proposed structure provides the about 2.5 times better speed and minimizes the power consumption by 3 times in comparison to hybrid double tail dynamic comparator with only 0.348 fJ/conv. energy per conversion. Moreover, it provides 2.44 mV offset with optimum kickback noise and area. [ABSTRACT FROM AUTHOR]

This paper introduces novel solution of triangular and square wave generator employing circuitry of interesting and unusual Schmitt trigger and specially prepared modification of lossless integrator connected in low-impedance input terminal of the comparator that allows linear charging of capacity and therefore also triangular wave generation that is not available in standard cases of applications (only relaxation generator available – exponential and square wave). Design and supposed operation of the circuit was verified not only theoretically but also experimentally with CMOS implementation of employed active elements available in form of IC device fabricated in 0.35 μm I3T ON Semiconductor process. Achieved result confirmed studied features of triangular wave generation and linear electronic tunability of its frequency between 23 and 151 kHz. [ABSTRACT FROM AUTHOR]