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This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC’s resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. [ABSTRACT FROM AUTHOR]

Injection-locked ring oscillators (ILROs) are widely used for quadrature clock generators (QCG) in multi-lane wireline or optical transceivers because of their low power, low area, and technology scalability. However, locking a four-stage I/Q oscillator with a two-phase injection signal generates imbalances in amplitude and phase, resulting in I/Q phase errors and degraded jitter performance. This paper proposes a modified frequency-domain analysis with amplitude constraint for even-phase ILROs. Combining theoretical derivations with simulation results in 28nm CMOS technology, the behaviors of ring oscillators with partial injection and ILRO-based QCG are discussed and concluded. [ABSTRACT FROM AUTHOR]

The analysis of injection-locked clock multipliers (ILCMs) using bang-bang phase detectors (BBPDs) is challenging due to the nonlinear BBPD and the multi-rate injected oscillator. This paper presents an explicit analysis of digital ILCMs using BBPDs and proposed an intuitive approach to optimizing parameters with given noise sources. A time-domain analysis in the single-clock domain is presented to solve the closed-form expression of jitter in the ILCM. The proposed approach exhibits good consistency with simulations, for various design parameters and noise cases. With the predicted input-referred jitter, the equivalent BBPD gain is resolved to derive the frequency-domain noise transfer functions in concise forms. To achieve the desired performance with given specifications, recommended design procedures are summarized based on the proposed analysis and verified by simulations. [ABSTRACT FROM AUTHOR]

This paper presents a linear current-reuse sampling phase detector for a single-loop type-I phase-locked loop (PLL) to simultaneously achieve a wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures an integrated jitter of 440 fsRMS, and a spur level of −63.9 dBc at 3.296 GHz. It draws 3.3 mW at a 0.9-V supply and scores a jitter-power figure-of-merit (FoM) of −241.9 dB. With a 103-MHz reference input, a bandwidth of ~20 MHz aids suppressing significantly the ring VCO’s phase noise (PN), leading to an in-band PN of −116 dBc/Hz at 1-MHz offset. The die size is 0.003 mm2. [ABSTRACT FROM AUTHOR]

As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself. [ABSTRACT FROM AUTHOR]

This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover- points distribution at the transitions introduces the single-loop phase tracking technique. In addition, low-power techniques at both the architecture and circuit levels are employed to greatly improve the overall energy efficiency and multiply data throughput by increasing the number of levels on the magnitude. Fabricated in 28-nm CMOS, our BBCDR prototype scores a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s under NRZ/PAM-4/PAM-8 modes, respectively. The jitter is < 0.53 ps (integrated from 100 Hz to 1 GHz) with approximately-equivalent constant loop bandwidth, and we achieve at least 1-UIpp jitter tolerance up to 10 MHz for all the three modes. [ABSTRACT FROM AUTHOR]

This paper presents an analytical method for the performance evaluation of the correlation-based impulse radio (IR) receivers, which detect the data based on synchronizing the received signal with a locally generated template pulse. In this paper, a phase interpolation technique is employed to preserve synchronization accuracy with low power consumption. The analytical method computes the spectral density of jitter at the phase interpolator output, resulting from both flicker and thermal noise components. The analysis considers the aliasing phenomenon due to the sampling of the noise to predict the induced jitter accurately. Bit error rate (BER) of the receiver is also statistically estimated in terms of the induced jitter on the template pulse, the noise effect of the receiver chain, and the template signal level. The proposed estimation procedure is validated by comparing its results with transient noise simulations. It is shown that increasing the template signal range in the correlator and improving the linearity of the phase interpolation transfer curve, at a given power consumption, enhances the receiver sensitivity by 2 and 3.5 dB, respectively. The BER estimation results also reveal that the effect of the template signal jitter on the sensitivity of the correlation-based IR receivers becomes dominant with the increasing input signal level. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma–delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sampling clock, on which the sampling period can be considered constant. In the proposed time-base, clock jitter can be modeled as the modulation of the input signal frequency and the integrators gain. Unlike standard techniques, we do not rely on the feedback pulse properties, which enables a broader application of our technique to band-pass or VCO-based $\Sigma \Delta $ modulators. In this paper, we present the basic theory of this technique and its application to some practical examples, showing a good matching between prediction and numerical simulation. [ABSTRACT FROM AUTHOR]

This paper presents a calibration-free and low-jitter phase-locked loop (PLL) with small performance degradation over PVT. We introduce an open-loop discrete-time phase noise cancellation (OPDTPNC) technique to achieve a wideband filtering and circuit inner-gain-tracking for PVT stabilization. The OPDTPNC is an effective phase realignment that enables a filtering bandwidth ~1/4 of the reference clock frequency. Besides, with the common structures and PVT tracking bias for sampler and corrector of the OPDTPNC, the prototype PLL maintains its low jitter under a wide range of PVT variations. Eventually, by cascading a Type-II PLL with the OPDTPNC, the proposed hybrid PLL attains the benefits of both Type-II PLL and injection-locked clock multiplier (ILCM). Fabricated in 28-nm CMOS with an active area of 0.023mm2 it consumes 4.1 mV from a 1 V supply with a reference spur of -63 dBc. The measured rms jitter of the 2.4 GHz PLL is 248 fs and 686 fs with and without OPDTPNC, respectively. When the temperature, supply and loop gain vary from 0 to 100°C, ±5%, and 6dB, respectively, the jitter performance only degrades less than 9%. [ABSTRACT FROM AUTHOR]

A 5-13.5 Gbps multi-standard I/O link receiver is presented in this paper. An inductor-free CTLE, whose gain and bandwidth are highly adjustable, is achieved by using the second-order negative capacitance circuit. A high jitter tolerance clock and data recovery (HJTOL-CDR) is proposed for Spread Spectrum Clock applications. In this work, the JTOL is improved by two ways: first, a partial-noise-shaping-based digital loop filter (PNS-DLF) is implemented to reduce the output jitter caused by the truncation error in the integral path; second, the proposed CDR logic is fully custom designed to operate at a quarter-rate clock of 5 GHz. Moreover, the CDR bandwidth can be tuned to satisfy various data rates and jitter masks. Post-layout simulation shows that the proposed CTLE can provide wide gain tuning range, the boost gain at 10 GHz is beyond 29 dB and the proposed CDR can tolerate up to 31-kppm frequency offset. The proposed receiver is fabricated in 40-nm CMOS with an active area of 0.06 mm2 and 65 mW power consumption at 20 Gbps from 1.2-V supply. Measurement results show that, when receiving the PRBS31 data at 10 Gbps with 5-kppm frequency offset across a channel with 14-dB loss, the JTOL is 0.39 UIpp at 10 MHz and can guarantee a 0.34 UIpp at high frequency, which proves that the proposed receiver can meet stringent standards such as PCIe 3.0/4.0, USB 3.2, DisplayPort 1.4. [ABSTRACT FROM AUTHOR]

This paper presents a 3.125-to-28.125 Gb/s dual-lane multi-standard parallel transceiver supporting channel-independent operation. Network equipment supports multiple data rates to encompass diversified communication standards. However, network equipment supports only a fixed number of channels at each supported data rate. This lack of flexibility limits the utilization rate of the network equipment. This study proposes a clock and data recovery (CDR) IC to obtain utilization flexibility and scalability in each channel with complete channel independency. The CDR IC achieves a wide tuning capability for data rates ranging from 3.125 to 28.125 Gb/s with low clock jitter owing to the use of injection-locked oscillators in each channel. Each CDR lane generates a channel-independent injection clock signal with a fixed-frequency global clock signal using a variable clock divider and a phase rotator with the proposed harmonic distortion compensator. In addition, a frequency tracking loop is proposed using a bang-bang phase detector-based natural frequency detector to align the natural frequency of the injection-locked oscillator with the input data rate, thereby suppressing the injection spur. The test chip fabricated in a 40 nm CMOS exhibits a power efficiency of 4.72 mW/Gb/s, while generating a recovered clock jitter of 976 fsrms at a data rate of 25.78125 Gb/s. [ABSTRACT FROM AUTHOR]

This paper proposes an ultra-compact 4 to 10-Gb/s 5-tap current-mode transmitter to realize the sub 1-UI fractional de-emphasis (DE) using a hybrid delay line, which is alternatively controlled by the voltage bias and clock. It exhibits the scalability between the clocked 0.5-UI and 1-UI DEs and data rate. The sub-1-UI DE provides wide tunability of the data amplitude and delay to compensate different channel losses between the $1^{st}$ and $2^{nd}$ Nyquist frequencies while effectively compensating the high-frequency portion of the pseudo-random binary sequence (PRBS) spectrum for data jitter improvement. Additional techniques are a two-step current-summing scheme, namely, two-step DE in the data path, and active inductors in both the data and clock paths to enhance the internal bandwidth without the need for passive inductors. In addition, we present an analytical model for predicting data-dependent jitter (DDJ) based on a generic system’s step response, derive the exact closed-form DDJ expression of DE, and verify its validity by mean of circuit simulation. Prototyped in 65-nm CMOS technology, it achieves a figure-of-merit of 4.6 mW/Gb/s and an output jitter of 10.8 pspp at 10 Gb/s under a PRBS $2^{31}-1$ pattern. The data eyes measure 0.62-UI-horizontal and 19.5%-vertical openings after −20-dB channel loss. The die area is 0.0071 mm2. [ABSTRACT FROM AUTHOR]

This paper proposes a sub-harmonically injection-locked all-digital PLL (SIL-ADPLL). The SIL-ADPLL includes five main circuit blocks: injection-locked digitally controlled oscillator with single-ended injection technique (SILDCO), injection-locked frequency divider (ILFD), timing-adjusted phase detector (TPD), multiplexed time-to-digital converter (MTDC), and the pulse generator (PG). The single-ended injection technique relaxes the pulse width constraint of the injection pulse and thus reduces the design complexity of PG. The proposed ILFD aided injection timing alignment technique can align the injection timing adaptively at output frequency higher than 20 GHz. The ILFD block is inserted between the SILDCO and the TPD without much penalty of power consumption. The proposed MTDC can quantize the output of TPD with only one TDC core to further save power consumption. The proposed PG can relax the trade-off between the phase noise suppression and the power consumption. Implemented in 65 nm CMOS process with a core area of 0.462 mm2, the SIL-ADPLL achieves 18- to 23-GHz frequency range, 57.4-fs rms jitter at 20 GHz, 13.7-mW power consumption, and −253.5-dB FoM. The measurement results also show robustness over environment variation. [ABSTRACT FROM AUTHOR]

In this paper, a design method for high-order delay-lock loops (DLLs) is presented and verified through simulations and physical experiments. The general approach is based on selecting the closed-loop transfer function of the DLL, together with identifying the coefficients of the phase-detector and voltage-controlled delay line, and subsequently, solving for parameters of the loop filter of the DLL. Past DLL design approaches relied more on establishing a desired phase margin requirement than attempting to establish a desired input–output behavior. This limited the realization of DLLs to second order; largely a result of the complicated mathematics that arise. As the method proposed in this paper is based on selecting a desired closed-loop transfer function, the issues of stability or phase margin never come to the forefront. This paper will show how a DLL can be designed to achieve a fast-settling-zero-overshoot step response with large jitter-rejection capabilities. The method is simple and easy to execute. No optimization or iteration is necessary. The method is similar to the methods used to design active-RC filter circuits. A fully programmable experimental prototype involving a custom IC implemented in a 130-nm IBM CMOS process was constructed. DLLs with orders ranging from second to eighth will be investigated. [ABSTRACT FROM PUBLISHER]

A new, all-digital on-chip peak-to-peak (p-p) jitter measurement circuit (OCJM) that features automatic resolution calibration for high PVT-variation resilience without a reference clock and off-line calibration is presented in this paper. The OCJM uses a front-end self-referenced circuit (SRC) to eliminate the jitter-free reference signal and a back-end p-p jitter detector (PPD) to perform p-p jitter measurements. The key design of the proposed OCJM is that the SRC and the PPD share a Vernier delay line (VDL) so that the run-time PVT information automatically extracted from the SRC operation can be carried onto the PPD to achieve automatic on-line resolution calibration. Besides this feature, the OCJM uses on-chip direct p-p jitter measurement with only 1-time readouts to eliminate the huge power consumption of the off-chip data communication while avoiding data loss of a possible large jitter caused by PVT variations during off-chip data communication. These techniques make the proposed OCJM suitable for any-time, any-site jitter measurements for SoC applications. The proposed OCJM is fabricated in a 28-nm CMOS. The measurement results show that the timing resolution and minimum measurable jitter range specifications are met under extreme PVT conditions while achieving 98% clock cycle and energy reduction compared to the conventional OCJM designs. [ABSTRACT FROM AUTHOR]

In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slewing requirements on the OpAmps in the modulator’s loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC’s disadvantageous trade-off between the modulator’s jitter, slewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM’s loop filter, noise- and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable. [ABSTRACT FROM AUTHOR]

In this paper, signal-to-noise ratio (SNR) degradation from random clock jitter in a current-steering digital-to-analog converter (CS-DAC) is analyzed based on a timing-to-amplitude error conversion method. A closed-form equation is derived to predict SNR for white noise clock jitter (WN-J) and low-pass filtered clock jitter (LPF-J) in non-return-to-zero (NRZ) and return-to-zero (RZ) DAC. Especially for the clock source with LPF-J, our equation predicts that the return-to-zero (RZ) DAC SNR is better than what the conventional analysis foresees due to the high-pass filter function derived in our analysis. Our analysis completely captures both WN-J and LPF-J in NRZ and RZ DAC, and is verified in both MATLAB simulation and measurement with the difference of less than 2 dB. [ABSTRACT FROM AUTHOR]

A 2.5–5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported injection-locked phase-locked loops (ILPLLs) require additional circuitry for resolving a phase alignment mismatch between the PLL loop and injection path, the presented ILPLL exhibits a simplified architecture owing to the proposed injection technique and sub-sampling bang-bang phase detector (SSBBPD). Because the proposed injection technique exploits dual-edge injection, we analyze the performance impact of dual-edge injection when inaccurate injection timing occurs. This paper also offers an analysis of the injection technique based on the charge transfer and derives the realignment factor of the injection. With the proposed injection technique and the direct connection of the digitally controlled oscillator (DCO) clock to the SSBBPD, the timing mismatch between the PLL loop and injection path becomes insensitive to voltage and temperature drift. The proposed ILPLL prototype is fabricated in a 65-nm CMOS process and achieves a 168-fs integrated rms jitter over 1 kHz to 40 MHz at a 5-GHz output frequency with 156.25-MHz reference clock while consuming 15.4 mW with an active area of 0.06 mm2. [ABSTRACT FROM AUTHOR]

This paper presents simple but accurate expressions for the noise components caused by clock jitter, in the output signal of self-oscillating sigma delta modulators (SOSDM). Contrary to conventional continuous time sigma delta modulators (CTSDM), the SOSDM's loop contains a strong oscillation, whose attribution to the system's jitter caused noise has not previously been explored. In this paper, the SOSDM system is modeled, and the effect of the self oscillation, the input signal and the quantization noise on the jitter caused noise in the output signal, is calculated. Results are confirmed by system level simulations. [ABSTRACT FROM AUTHOR]

This paper presents an analysis based on the impulse sensitivity function to precisely characterize and estimate the jitter caused by the common-mode interference (CMI). Unlike the conventional common-mode rejection ratio concept, the proposed method considers the CMI jitter in a transient rather than in an ac perspective. Inspired by the analytical results, we propose a clock receiver circuit (CRC) based on the self-bias amplifier topology. The accuracy of the analysis and the efficiency of the proposed CRC are verified both in simulations and measurements. A 1-GS/s ADC was fabricated in 65-nm CMOS containing simultaneously three CRCs, including an inverter-chain, a differential amplifier and the proposed structure, serving as the sampling clock. Both simulation and measurement results show a good agreement with the presented analysis. The proposed CRC achieves a 30-fsms jitter with a 620- \mu \textW power at 1.2 V supply. With a similar CMI rejection and random jitter performance, the proposed CRC exhibits a 20-fold power reduction when compared with the state-of-art designs. [ABSTRACT FROM PUBLISHER]

The use of a single-bit quantizer in a wideband CT \Delta \Sigma \textM is attractive, as the quantizer can be implemented in a power and area-efficient manner. Unfortunately, 1-bit CT $\Delta \Sigma $ Ms are plagued by a host of difficulties. Clock jitter and quantizer metastability are particularly problematic, and the higher loop filter linearity needed to process the full-scale feedback waveform results in increased power dissipation. The use of a finite impulse response (FIR) feedback DAC is a power efficient way of addressing the challenges above. However, even this technique runs into difficulties at multi-GHz clock rates. This paper introduces the idea of time-interleaved (TI) FIR feedback to enhance the performance of a conventional FIR DAC. A single-bit CT \Delta \Sigma \textM that uses a $2\times $ TI-FIR DAC achieves 67.6/68.8/76 dB SNDR/SNR/DR in a 60 MHz bandwidth. Designed in a low leakage 65 nm CMOS process, the modulator operates at 6 GHz and occupies only 0.07 mm2. Its Walden Figure of Merit is 56.5 fJ/lvl. [ABSTRACT FROM PUBLISHER]

A 1.5–3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with dead-zone free phase detector to overcome the dead-zone problem of conventional phase detectors. The D-type flip-flops in the phase detector are modified to detect sub-ps level delay difference between the input and output clocks, so that a delay resolution of better than 1 ps is achieved in the proposed design. The combination of both coarse and fine locking processes gives outstanding performance in terms of residual phase difference and output jitter. The overall design occupies 0.0077 mm2 area. The experimental results show that the peak-to-peak and root mean square jitters are 12 and 1.629 ps at 3.3 GHz, respectively, while the input jitter is 2.6 ps peak-to-peak and 612 fs rms. [ABSTRACT FROM PUBLISHER]

In this paper, we present a bang-bang phase detector (BBPD) and a delay-line frequency discriminator-based phase noise filter (PNF). With a larger phase detection gain, the BBPD-based PNF enhances the sensitivity by suppressing the charge pump noise. A time-amplifier and a five times voting machine are introduced together with the sense-amplifier-flip-flop to minimize the BBPD noise to make its effects negligible in the PNF sensitivity. At 1-MHz offset, the PNF demonstrates 15-dB phase noise suppression with −120.2-dBc/Hz sensitivity. Its phase noise suppression offset frequency is from 100 kHz to 8 MHz with 10–10.1-GHz input frequency range. The circuit is fabricated in a 65-nm CMOS technology, and dissipates 98-mW power. [ABSTRACT FROM PUBLISHER]

Tolerating timing error due to power supply noise (PSN) in digital circuits can be done with adding voltage margins. Conservative addition of voltage margins leads wastes of power reducing the battery life in Internet of Things (IoT) devices. This paper aims to provide guidelines to avoid over-design due to PSN especially for the low-cost IoT devices. To this end, we first present an accurate time-domain behavioral model of timing slack variation due to PSN accounting for the clock-data compensation. The accuracy of the model is verified against SPICE for complex designs, including AES engine and LEON3 processor. To prove the effectiveness of our model for reducing voltage margin, we utilize our model in standard VLSI design flow for various examples, such as timing slack versus noise frequency analysis, determining optimal value of an on-die capacitor, analyzing the effects of time borrowing technique, and PVT variation simulations. The analysis shows that the model helps reduce pessimism in estimated timing slack. [ABSTRACT FROM PUBLISHER]

This paper presents a quarter-rate forwarded clock (FC) receiver based on an injection-locked oscillator (ILO) which exploits a phenomenon in which phases of the output clock are shifted by the duty-cycle of an injection clock. Also, this paper describes the principle of this phase shifting phenomenon. To utilize the phase shifting phenomenon, a simple duty-cycle adjuster (DCA) is proposed. By using the DCA, the proposed FC receiver achieves 760 MHz of wide jitter tracking bandwidth (JTB) and 60 MHz JTB variation in spite of clock deskew. The proposed receiver achieves a 12 Gb/s data rate with 0.92 mW/Gb/s in a 1 V 65 nm CMOS process. [ABSTRACT FROM AUTHOR]

This paper presents a reference-less digital clock and data recovery (CDR) for liquid crystal display (LCD) intra-panel interfaces. The increments of the display resolution, the color depth, and frame rate demand high speed transmission capacity between timing controller and source driver IC (SDIC). As the data rate increases, the performances of the CDR in the SDIC especially for the tolerance of input jitter and ground noise become important to recover the data without an error. This work exploits the half-bit previous input data with feed forward method and early/late signal from CDR to be tolerant to the input jitter and power noise. Two prototypes are tested with half-rate clocking at 5 Gb/s data rate, and quarter-late clocking at 10 Gb/s data rate. Both 5 Gb/s and 10 Gb/s prototypes improve the tolerance of the input jitter and power noise. Fabricated in 65 nm CMOS technology, the test chips consume 17.44 mW and 20.7 mW, respectively. [ABSTRACT FROM AUTHOR]

Bias phenomenon has been a ubiquitous problem in the designs of digital True Random Number Generator (TRNG). Circuit performance can be improved with some auxiliary modules such as analog circuits and post-processing components, which usually involve the compromising of cost, compatibility, throughput, and security as well. In some cases only sub-optimal designs can be achieved. In this paper, by utilizing the diverse timing characteristics of different initial states, a staged-running Self-timed Ring (STR) architecture, which is able to suppress the degree of bias, is proposed. The proposed architecture is compared with some conventional free-running architectures using a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) platform for a throughput of 100 Mbps. With the increase of the ring size, the bias degree of the newly proposed structure is within a negligible level of less than 1%; whereas those of the conventional architectures can exceed 10%. Statistical tests were also conducted and the results show that the quality of randomness rises as the complexity in initial-state mapping and the ring nodes of the proposed structure increases. The test passes the National Institute of Standards and Technology (NIST) test suite with high p-values. [ABSTRACT FROM PUBLISHER]

This paper describes a power and area-efficient forwarded-clock (FC) receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a delay-locked loop (DLL) based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-\textUI\mathrm{pp} sinusoidal jitter of 300 MHz. [ABSTRACT FROM AUTHOR]

This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit that utilizes common-mode clock-embedded signaling (CM-CES) and injection locking techniques to reduce design complexity for the half-rate data recovery. In the proposed receiver, the use of wideband injection-locked oscillator (ILO) greatly suppresses its phase noise while the narrowband digital phase tracking loop (DPTL) tunes retiming phase. For wide-range and continuous-rate operation, four circuit techniques have been adopted: a VCO with active inductance load for low VCO gain at high frequency, a wide-range digitally-controlled delay line (DCDL) with adaptive band selection, a linearized delay control unit with CM-to-delay conversion technique, and a coarse frequency detection scheme to drive the free-running oscillator frequency toward injection locking. The prototype CDR, fabricated in low power CMOS 65 nm technology, successfully detects 0.8–6.5 Gb/s data rates over 5 ^\prime\prime FR4 trace with 2^31-1 PRBS pattern satisfying \textBER<10^-12. The power efficiency was 2.4 mW/Gb/s at 6.5 Gb/s. [ABSTRACT FROM AUTHOR]

This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit with an asynchronous baud-rate sampling to achieve an adaptive equalization as well as a data rate acquisition. The proposed scheme also enables the use of a successive approximation register (SAR) based approach in the frequency acquisition and results in a fast coarse lock process. The CDR guarantees a robust operation of a fine locking even in the presence of large input data jitter due to the adaptive equalization and a jitter-tolerable rotation frequency detector (RFD) that eliminates a dead-zone problem with a simple circuitry. The fabricated CDR in 65 nm CMOS shows a wide lock range of 0.65-to-10.5 Gb/s at a bit error rate (BER) of 10^-12. The CDR consumes 26 mW from a single supply voltage of 1 V at 10 Gb/s including the power consumption for equalizer. By an adaptive current bias control, the power consumption is also linearly scaled down with the data rate, exhibiting a slope of about 2 mW decrease per Gb/s. [ABSTRACT FROM AUTHOR]

This paper presents a forwarded-clock receiver using a mixing cell integrated injection-locked oscillator (MIILO) and an I/Q generator based on injection-locked oscillator (IQGILO). By using MIILO, jitter tolerance is enhanced by about 1.8 times at high frequency compared to using a conventional injection-locked oscillator. In addition, the proposed receiver is robust against power supply induced jitter (PSIJ) caused by a clock distribution network because jitter tracking bandwidth of IQGILO is always lower than peak frequency of PSIJ regardless of latency mismatch between data and clock. The test chip achieves 9.6 Gb/s data rate with 0.96 mW/Gb/s and occupies only 0.0162 mm^2 in a 1 V 65 nm CMOS. [ABSTRACT FROM AUTHOR]

Clock jitter is one of the most fundamental obstacles in realizing future generations of wideband receivers. Stringent jitter specifications in the sampling clocks of high-performance single-channel and multichannel time-interleaved analog-to-digital converters severely limit the evolution of baseband receivers. This paper presents an analytical framework for the design of clock-jitter-tolerant low-order multichannel filter-bank receivers, with techniques to dramatically lower the sampling-clock-jitter specifications. Although it is well understood that high-order frequency-channelized receivers provide higher tolerance to sampling jitter, this paper shows that low-order bandwidth-optimized multichannel receivers can achieve similar sampling-jitter tolerance. Additionally, this paper presents design tradeoffs and specifications of an example multichannel receiver that can process a 5-GHz baseband signal with 40 dB of signal-to-noise-ratio using sampling clocks that can tolerate up to 5\ \psrms clock jitter. In comparison, existing architectures based on time-interleaving require 0.5\ \psrms clock jitter for the given specifications. This extreme jitter tolerance allows for relaxed design of clocking systems, which averts a major roadblock in future wideband-communication-receiver development and provides the potential to enable several high-data-rate communication applications. [ABSTRACT FROM PUBLISHER]

In this paper, a low-voltage fourth-order 2-2 cascade delta–sigma (\Delta\Sigma) modulator using the proposed double-sampling switched-operational-amplifier (SOP)-based integrator is presented. In the analog part of the \Delta\Sigma modulator, most of the power consumption comes from the SOP used in the integrator. Hence, the requirement of the SOP must effectively be relaxed to reduce the power consumption of the modulator. In each cascade stage, the second-order \Delta\Sigma modulator with a cascade-of-integrators input feedforward structure is used to reduce the output swing. The second integrator output of the first stage is directly connected to the second stage to simplify circuit design on the analog part. Furthermore, the double-sampling SOP-based integrator is also adopted to reduce the applied clock frequency by half. In this paper, systematic means of designing the presented modulator and searching the minimum current of the SOP in a specified supply voltage are also developed. The presented \Delta\Sigma modulator is fabricated in a 0.18-\mu\m 1P6M CMOS technology. The chip core area without PADs is 1.57 \mm^2. The modulator achieves an 84-dB peak signal-to-noise plus distortion ratio and an 88-dB dynamic range in 20-kHz signal bandwidth with a clock frequency of 2 MHz. The power consumption of the presented modulator core is 0.66 mW at a supply voltage of 1 V. The presented modulator can also be operated in a wide range of supply voltages from 1.8 V down to 0.9 V without seriously degrading the performance. [ABSTRACT FROM PUBLISHER]

This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts: Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edges in the FA's multiplexer's output establishes a discrete-time index that is used to analytically derive the fundamental discrete-time periods of all FA's signals. The continuous-time intervals between the rising edges are calculated and used to derive the fundamental continuous-time periods of the signals from the corresponding discrete-time ones. It is shown that the FA behaves differently within different ranges of the frequency word, and the practically useful range is identified. The FA's output average frequency, along with its maximum and minimum values, is analytically derived by calculating the number of cycles in the output signal within a fundamental continuous-time period of it. The relationship between the average and the fundamental output frequencies is also established, indicating the potential frequencies and density of output spurious frequency components. Part II of the paper characterizes the timing structure of the output signal, providing analytical expressions of the pulses' locations, analytical strict bounds of the timing irregularities, and exact analytical expressions of several standard jitter metrics. Spectral properties of the output waveform are presented, including the dominance of the frequency component at the average frequency, and analytical expressions of the dc value and average power of the output signal are derived. The FA has been implemented in a Xilinx Spartan-3E field-programmable gate array, and spectral measurements are presented, confirming the theoretical results. Extensive MATLAB simulation has also been used to generate numerous examples illustrating the developed theory. [ABSTRACT FROM PUBLISHER]

This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts. Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edges in the FA's multiplexer's output establishes a discrete-time index that is used to analytically derive the fundamental discrete-time periods of all the FA's signals. The continuous-time intervals between the rising edges are calculated and used to derive the fundamental continuous-time periods of the signals from the corresponding discrete-time ones. It is shown that the FA behaves differently within different ranges of the frequency word, and the practically useful range is identified. The FA's output average frequency, along with its maximum and minimum values, is analytically derived by calculating the number of cycles in the output signal within a fundamental continuous-time period of it. The relationship between the average and the fundamental output frequencies is also established, indicating the potential frequencies and density of output spurious frequency components. Part II of the paper characterizes the timing structure of the output signal, providing analytical expressions of the pulses' locations, analytical strict bounds of the timing irregularities, and exact analytical expressions of several standard jitter metrics. Spectral properties of the output waveform are presented, including the dominance of the frequency component at the average frequency, and analytical expressions of the dc value and average power of the output signal are derived. The FA has been implemented in a Xilinx Spartan-3E field-programmable gate array, and spectral measurements are presented, confirming the theoretical results. Extensive MATLAB simulation has also been used to generate numerous examples, illustrating the developed theory. [ABSTRACT FROM PUBLISHER]

An accurate performance evaluation of jitter-power figure-of-merit (FOM) for multiplying delay-locked loop (MDLL) is presented. For a typical MDLL employing a single-ended multiplying-delay ring voltage-controlled oscillator (MDVCO), it can be tuned via the capacitive loads to uphold a constant normalized phase noise (PN) across different frequencies for better jitter-power performance. Linear approximation and z-domain PN model are utilized to simplify the analysis with excellent agreement between the time-domain simulation and z-domain approximation. The influences of the asymmetric waveform, flicker noise corner, frequency error and reference noise are also discussed and then ignored based on the reasonable approximation. Under a given process, reference clock frequency and supply voltage, the ideal FOM can be derived theoretically. Based on these insights, the predicted FOM can be the benchmark metric in the design of MDLL for the possible best jitter-power performance. [ABSTRACT FROM AUTHOR]

This paper presents a loop gain optimization technique for integer-N digital phase-locked loops with a time-to-digital converter. Due to noise filtering properties, a phase-locked loop has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the loop gain optimization technique, the digital phase-locked loops can automatically attain this loop gain in background to minimize the jitter. Theoretical analysis is presented. The stability issue and the impact of loop latency are also discussed. Finally, the analysis is compared to behavioral simulations with good agreement. [ABSTRACT FROM AUTHOR]

This paper presents the design of a continuous-time \Delta\Sigma modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR, and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 mm^2 and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved. [ABSTRACT FROM AUTHOR]

This paper proposes using a 3-bit ADC to blindly sample the received data from a channel with 20 dB loss at Nyquist at 3x the baud rate. By moving from 2x to 3x sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our test chip fabricated in Fujitsu's 65 nm CMOS show a high frequency jitter tolerance of 0.25 UIpp for a 5 Gb/s PRBS31 with a 60" FR4 channel. [ABSTRACT FROM AUTHOR]

This paper presents a 40 Gb/s (38.4-to-46.4 Gb/s) half rate SerDes transmitter with automatic serializing time window search and 2-tap pre-emphasis. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at the highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. A divider-less sub-harmonically injection-locked PLL (SILPLL) with auto-adjust injection timing is employed to provide low jitter clock source. A power-efficient 2-tap feed-forward equalizer (FFE) based on open loop 1-UI delay generation is implemented as the transmitter equalizer. Fabricated in 65 nm CMOS technology, the transmitter running at 40 Gb/s consumes 80 mW power under 1.2 V supply. The PLL RMS jitter is 98 fs integrating from 100 Hz to 100 MHz and the total jitter of 40 Gb/s eye diagram is 6.7 ps for 1e-12 BER. [ABSTRACT FROM AUTHOR]

This paper presents a continuous-time third-order \Sigma\Delta modulator designed for closing the feedback loop of a digital class-D audio amplifier. The closed-loop digital class-D amplifier fully exploits the potential of the used 40-nm CMOS technology to achieve at the same time the flexibility of digital implementations and the performance of analog solutions. The proposed \Sigma\Delta modulator consumes 1.7 mW from a 1.1-V power supply, achieving 101-dB dynamic-range (DR) and 72-dB peak signal-to-noise and distortion ratio (SNDR). The active-RC implementation allows the 1.1-V \Sigma\Delta modulator inputs to be directly connected to the 5-V class-D amplifier power stage outputs and inherently guarantees third-order anti-aliasing filtering. [ABSTRACT FROM AUTHOR]

Traditional all-digital delay-locked loops (ADDLLs) have a long control loop, and false skew compensation may occur due to late code adjustment. To avoid this problem, the ADDLLs either simply sacrifice the maximum operating frequency or adopt a lower code adjustment rate to achieve a higher maximum operating frequency. However, lowering the code adjustment rate not only increases the number of the locking cycles but also results in large output jitter because the clock skew induced by run-time variations cannot be compensated in time. This paper presents a 55 nm 1.0 V 0.1-to-2.5 GHz ADDLL, which is constructed on a previously proposed half-delay-line skew-compensation circuit with several new circuit design techniques developed to achieve low jitter, small area, low power, fast lock-in, and high PVT- variation tolerance across a large operating frequency range. The key design feature is a ping-pong phase maintenance scheme that allows the code adjustment to be performed in time in each clock cycle, even for gigahertz operations. The measurement results show that the ADDLL achieves a peak-to-peak (p-p) jitter of 3 ps with 1.96 mW power consumption and 8 lock-in cycles when operated at 2.5 GHz. [ABSTRACT FROM AUTHOR]

This paper describes a delta-sigma modulator with a new feedback topology in combination with the recently proposed two-step residue-discharging quantizer. Instead of using a single digital-to-analog converter (DAC) with a large number of levels, a mixed-mode DAC is presented which takes advantage of the two-step nature of the quantizer. Hence, only one feedback DAC, which is associated with the coarse bits (MSBs), is required for the modulator and LSBs are fed back as a time-modulated pulse (TMP). Therefore, high quantization resolution is achieved without increasing the front-end DAC complexity. Additionally, a new data weighted averaging (DWA) technique is proposed which not only suppresses the mismatch between the unit elements of the MSB DAC, but also aims to average out the gain error between the MSB and LSB DACs. Therefore, the possible quantization noise leakage is drastically reduced. Detailed mathematical models as well as comprehensive simulation results are provided to prove the efficiency of the proposed structure. [ABSTRACT FROM AUTHOR]

This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11 \mum CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than 10^-13 while consuming 82 mW at 10-Gb/s. [ABSTRACT FROM AUTHOR]

This paper presents a power and area efficient approach to embed a continuous-time linear equalizer (CTLE) within a clock and data recovery (CDR) circuit implemented in 65-nm CMOS. The merged equalizer/CDR circuit achieves full-rate operation up to 28 Gb/s while drawing 104 mA from a 1-V supply and occupying 0.33 mm2. Current-mode-logic (CML) circuits with shunt peaking loads using customized differential pair layout are used to maximize circuit bandwidth. To minimize the area penalty, differential stacked spiral inductors (DSSIs) are employed extensively. A novel and practical methodology is introduced for designing DSSIs based on single-layer inductors provided in foundry process design kits (PDK). The DSSI design increases the inductance density by over 3 times and the self-resonance frequency by 20% compared to standard single-layer inductors in the PDK. The measured BER of the recovered data by the CDR is less than 10-12 at 27 Gb/s for 211-1 400 mV PP pseudo-random binary sequence (PRBS) as input data. The measured rms jitter of the recovered clock and data are 1.0 and 2.6 ps, respectively. The CDR is able to lock to inputs ranging from 26 to 28 Gb/s with 29-1 PRBS pattern. Measurement results show that with the equalizer enabled, the CDR can recover a 26-Gb/s 27-1 PRBS data with BER ≤ 10-12 after a channel with 9-dB loss at 13 GHz. [ABSTRACT FROM AUTHOR]

Incremental delta-sigma data converters are useful in applications where one ADC is needed to digitize multiple channels. They can be realized using single- or multi-bit feedback. In both cases, the use of FIR feedback is beneficial in terms of improving the modulator’s linearity, reducing the quantizer’s complexity, and mitigating the effects of clock jitter (in a continuous-time realization). In the incremental mode, however, the maximum stable amplitude of the ADC is severely impacted by FIR feedback. The reasons behind this are examined, and techniques that mitigate this problem are given. Circuit simulations of an example fourth-order single-bit incremental modulator with an eight-tap FIR DAC are given to illustrate the efficacy of the theory. [ABSTRACT FROM AUTHOR]

State-of-the-art TDCs can have a precision close to one picosecond, for which reason clock instability is starting to be one of the most significant factor limiting the precision. This paper provides methods to estimate clock jitter induced error by phase noise PSD measurements. Due to the different noise processes of the power-law model, convergence problems might restrict the time domain conversion of clock instabilities. Since time interval measurement corresponds to measuring the first difference of phase error, the convergence problems cannot be completely avoided as is usually done when characterizing frequency instabilities in time domain by measuring the 2nd differences of the phase error. This issue is addressed by taking into account the finite observation window of the phase error. Also a simple PSD measurement technique is introduced to provide an estimate of the jitter due to noise floor with an unknown bandwidth. Spurious tones in the phase noise PSD are also shown to have a significant impact on the precision of a TDC. The results are confirmed by several measurements done with a time-to-digital converter having a 1-ps precision. [ABSTRACT FROM PUBLISHER]

In typical direct radio frequency (RF) sampling receivers, the sample clock jitter results in SNR degradation on received signals that increases log linearly with RF signal frequency. De-jittering received signals is computationally expensive, especially for wideband communications signals, because the induced jitter on received signals varies as a function of RF signal frequency. This paper considers a reconfigurable direct RF receiver (RDRFR) that has a stair-step jitter pattern as a function of RF signal frequency. The RDRFR uses a two-stage sampling circuit. In the first stage, the RF input is bandpass filtered and pulse sampled without quantizing the signal. The discrete-time analog signal is then interpolated with a continuous time low-pass filter, then sampled and quantized by a traditional analog-to-digital converter. With this two-stage sampling circuit, the induced signal jitter from the RF sampling is identical for all in-band signals and is the same to within an integer scale factor for all signals, in-band or out-of-band. This key circuit property means that it is possible to remove jitter with very low computational complexity in the RDRFR. Furthermore, this result can be exploited to improve system performance with non-ideal anti-alias filters by identifying non-desired signals caused by out-of-band leakage. [ABSTRACT FROM PUBLISHER]

This paper presents a 5.4-Gb/s clock and data recovery circuit using a seamless loop transition scheme which has minimal phase noise degradation. The proposed scheme enables the CDR circuit to change the operation mode without output phase noise degradation or stability problems. A modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufactured using 0.13-μm CMOS technology. The rms jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps lower than the CDR circuit with the conventional scheme. The measured power dissipation is 138 mW with output drivers and an embedded 2:1 MUX at 5.4-Gb/s data rate. [ABSTRACT FROM PUBLISHER]