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This paper proposes a new method to determine the overdrive (OD) to improve the response characteristics of displays based on the linearity in voltage domain. The proposed method estimates OD values by using a simple function between the slope of linearity and transition. The values of the function can be determined using only two measurements. The proposed work can be applied to both active-matrix liquid-crystal displays and active-matrix organic light-emitting diode (AMOLED) displays. OD artifacts were observable when OD deviation was over three gray levels. However, the average OD deviations were 1.47, 0.87, and 0.69 when the proposed method was applied to twisted nematic, in-plane switching, and fringe-field switching modes, respectively. The deviation in AMOLED displays was 0.45 gray levels. [ABSTRACT FROM AUTHOR]

Selector-less resistive random-access memory (RRAM) devices require high nonlinearity (NL) in low-resistance state current ( ${I}_{\textsf {LRS}}$ ). In this paper, we investigate the effect of composition (here, Ca%)-dependent material properties, viz., ion migration barrier, and thermal conductivity, on memory performance of recently demonstrated Pr1–xCaxMnO3-based selector-less RRAM with high NL. First, the NL increases as “ $\mathit {x}$ ” decreases. This is attributed to higher self-heating in $\textsf {PCMO}{(}\mathit {x}{)}$ films as composition-dependent thermal conductivity ( $\kappa $ ) decreases as “ $\mathit {x}$ ” is decreased. This enables selector-less operation. Second, larger memory window is observed as “ $\mathit {x}$ ” increases due to decrease in the voltage required for onset of RESET process (i.e., $V_{\textsf {MIN, RESET}}$ ) as “ $\mathit {x}$ ” is increased. Lower $V_{\textsf {MIN, RESET}}$ at higher “ $\mathit {x}$ ” is due to higher oxygen-ion conductivity attributed to lower migration barrier ( ${E}_{m}$ ). Third, retention is measured at different temperatures to extract composition-dependent ${E}_{m}$. The poor memory retention performance for $\mathit {x}= 1$ is consistent with lower ${E}_{m}$ estimated. Finally, enhanced endurance is observed for lower ${E}_{m}$ due to low-energy requirement for switching. Based on these observations, an interrelation between ${E}_{m}$ , retention, and endurance is established. Therefore, an interplay of composition-dependent thermal conductivity and oxygen-ion migration barrier enables tunable memory characteristics in Pr1–xCaxMnO3-based RRAM. [ABSTRACT FROM AUTHOR]

This paper reports the significance of device architecture to enhance impact ionization (I.I.) resulting in steep increase in the current from OFF- to ON-state. Recognizing that the area over which I.I. occurs is a key factor governing impact generated power per unit volume in the semiconductor film, we use raised source/drain (RSD) architecture to achieve sub-60-mV/decade subthreshold swing (S-swing) in germanium (Ge) junctionless (JL) devices at drain bias ( ${V}_{\text {ds}}$ ) of 0.9 V. The performance of RSD Ge JL device is compared with double-gate Ge JL transistor to highlight the occurrence of subthermal S-swing <5 mV/decade in RSD topology. The impact of band-to-band tunneling (BTBT) on the switching characteristics shows that RSD JL device with relatively thicker side oxide can effectively suppress BTBT while enhancing I.I. The influence of parasitic capacitance due to RSD regions and vertical doping gradient is also analyzed. Results highlight new viewpoints for the design of RSD Ge JL MOSFETs with channel doping $({N}_{\text {ch}}) \ge {5}\times {10}^{18}$ cm−3 to facilitate sharp current transition. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) is among the most mature technologies for next generation storage class memory with low power, high density, and improved performance. The biggest challenge toward industrialization of RRAM is the large variability and noise issues, causing distribution broadening which affects retention even at room temperature. Noise and variability can be addressed by enlarging the resistance window between low-resistance state and high-resistance state, which requires a proper engineering of device materials and electrodes. This paper presents an RRAM device technology based on silicon oxide (SiOx), showing high resistance window thanks to the high bandgap in the silicon oxide. Endurance, retention, and variability show excellent performance, thus supporting SiOx as a strong active material for developing future generation RRAMs. [ABSTRACT FROM AUTHOR]

The cross-point architecture for memory arrays is widely considered as one of the most attractive solutions for storage and memory circuits thanks to simplicity, scalability, small cell size, and consequently high density and low cost. Cost-scalable vertical 3-D cross-point architectures, in particular, offer the opportunity to challenge Flash memory with comparable density and cost. To develop scalable cross-point arrays, however, select devices with sufficient ON–OFF ratio, current capability, and endurance must be available. This paper presents a select device technology based on volatile resistive switching with Cu and Ag top electrode and silicon oxide (SiOx) switching materials. The select device displays ultrahigh resistance window and good current capability exceeding 2 MAcm−2. Retention study shows a stochastic voltage-dependent ON–OFF transition time in the 10~\mu \texts –1 ms range, which needs to be further optimized for fast memory operation in storage class memory arrays. [ABSTRACT FROM PUBLISHER]

Transport properties of realistic phosphorene nanoribbons (PNRs) with edge defects are studied by using statistical atomistic quantum transport simulations. Regarding the impact of nanoribbon width downscaling and increasing of edge defect percentage, we show that PNRs exhibit qualitatively similar behavior of the ON- and OFF-state conductance, and of the ON–OFF conductance ratio as graphene nanoribbons (GNRs). However, we demonstrate that PNRs are superior to GNRs in terms of the absolute values of the conductance parameters, and that PNRs are much more immune to edge defects than their graphene counterparts. This paper identifies PNRs as a more promising channel material than GNRs for the extremely scaled postsilicon transistor technology. [ABSTRACT FROM PUBLISHER]

The high current density required by magnetic tunneling junction (MTJ) switching driven by the spin transfer torque (STT) effect leads to large power consumption and severe reliability issues, hindering the timetable for STT magnetic random access memory to mass market. By utilizing the voltage-controlled magnetic anisotropy (VCMA) effect, the MTJ can be switched by the voltage effect and is postulated to achieve ultralow power (fJ). However, the VCMA coefficient measured in experiments cannot meet the requirement for MTJ with dimensions below 100 nm. And an external in-plane magnetic field usually is demanded for precessional VCMA switching. Here, in this paper, a novel approach for the amplification of the VCMA effect, which borrows ideas from negative capacitance, is proposed. The feasibility of the proposal is proved by physical simulation and in-depth analysis. Since the amplified VCMA effect, the external magnetic field can be eliminated. A three-terminal novel MTJ memory cell is designed with which both low power and high speed can be achieved. [ABSTRACT FROM AUTHOR]

Due to high surface-to-volume ratio, surface traps play crucial role in electronic properties of semiconductor nanowires and nanowire-based devices. Recently, it was experimentally demonstrated that surface traps even can induce conductivity type inversion in semiconductor nanowires. Here, we have performed theoretical and numerical analyses to investigate the influence of surface traps on semiconductor nanowire conductivity including possible inversion due to surface traps. The Poisson equation with consideration of both type of mobile charges and ionized donors was solved having surface trapped charges in Neumann boundary conditions. Different semiconductor materials and surface trap densities have been considered. Calculations were done considering single energy level of surface traps and then the results were generalized to exponential energetic distribution of surface states density. The effect of surface traps was analyzed both for low-doped and highly doped nanowires. It was shown that for moderate or lightly doped NWs, the conductivity type switching from n- to p-type can occur at small radii. The developed potential-based analytical model allows calculating the inversion charge raised due to surface traps. The accuracy of analytical calculations has been validated with TCAD simulations and qualitatively compared with published experimental data. This paper is useful for design optimization of nanowire-based photodetectors, sensors, and reconfigurable FETs. [ABSTRACT FROM AUTHOR]

Nonvolatile logic computations are of particular interest due to their zero standby leakage power consumption. In this paper, we explore a nonvolatile majority logic using voltage-driven magnetoelectric (ME) switching of ferromagnets. Specifically, we employ ME magnetic tunnel junctions (ME-MTJs) connected in parallel to construct a majority gate. We also present the cascadability of the proposed majority gate using CMOS inverters. Furthermore, through a mixed-mode simulation framework consisting of magnetization dynamics and electron transport model, we analyze the robustness of the proposed majority gate under process variations. Our analysis shows that due to parallel connection of the ME-MTJs, high tunnel magnetoresistance (TMR) ratios are required for proper functioning of the proposed majority gate, in presence of variations. In order to relax the constraints on the TMR requirements, we present an alternate implementation of the majority logic that does not require a parallel connection of ME-MTJs, thereby increasing the robustness against process variations. Energy and delay metrics are presented for a full adder implementation using the proposed majority gates. [ABSTRACT FROM AUTHOR]

Ferroelectric (FE) hafnium oxide is a promising candidate for memory applications. In this paper, endurance, imprint, and retention tests are carried out on FE aluminum-doped hafnium oxide thin films with different electrodes: 1) metal–insulator–metal (MIM) and 2) silicon–insulator–silicon(SIS). MIM devices exhibit higher endurance than SIS devices. However, SIS devices show superior imprint and retention, with an extrapolated retention time-to-failure larger than 10 years at 85 °C. These results are very promising to integrate FE-HfO2 in 3-D structures, either for dynamic random access memory or for NAND applications. [ABSTRACT FROM PUBLISHER]

In this paper, we present an effective switching current model ( I\textsf {eff} ) for inverter followed by a transmission gate structure (Inv-Tx) based on its switching trajectory. Unlike an inverter or NAND/NOR gates, where I\textsf {eff} depends only on nMOSFET (pMOSFET) current for a falling (rising) transition, it is a function of both nMOSFET and pMOSFET currents for an Inv-Tx cell. The proposed model is verified against HSPICE simulations for a wide range of supply voltages and fan-outs at different technology nodes (e.g., 180, 130, and 65 nm). The model predicts the transition delay values with an average (maximum) error of 7% (11%) compared with HSPICE simulations. Synopsys TCAD Sentaurus simulations at 32-nm technology node are also used to validate the basic model assumptions. To demonstrate the utility of our model, design of some representative circuits while incorporating layout-dependent effects and inverse-narrow-width effect is presented. Finally, we show that a 256X1 multiplexer and a static D-flip-flop, with their transistor sizes and layout, optimized using the proposed model improves the performance of these circuits significantly over the conventional design methodologies. [ABSTRACT FROM PUBLISHER]

Resistive-switching random access memory (RRAM) is widely considered as a disruptive technology. Despite tremendous efforts in theoretical modeling and physical analysis, details of how the conductive filament (CF) in metal-oxide-based filamentary RRAM devices is modified during normal device operations remain speculative, because direct experimental evidence at defect level has been missing. In this paper, a random-telegraph-signal-based defect-tracking technique (RDT) is developed for probing the location and movements of individual defects and their statistical spatial and energy characteristics in the CF of state-of-the-art hafnium-oxide RRAM devices. For the first time, the critical filament region of the CF is experimentally identified, which is located near, but not at, the bottom electrode with a length of nanometer scale. We demonstrate with the RDT technique that the modification of this key constriction region by defect movements can be observed and correlated with switching operation conditions, providing insight into the resistive switching mechanism. [ABSTRACT FROM PUBLISHER]

The aim of this paper is to introduce a compact model for perpendicular spin-transfer torque (STT)-magnetic tunnel junctions (MTJs) implemented in Verilog-A to assure easy integration with electrical circuit simulators. It takes into account the effects of voltage-dependent perpendicular magnetic anisotropy, temperature-dependent parameters, thermal heating/cooling, MTJ process variations, and the spin-torque asymmetry of the Slonczewski spin-polarization function in the switching process. This translates into a comprehensive modeling that was adopted to investigate the writing performance under voltage scaling of a $256\times256$ STT- magnetic random access memory array implemented at three different technology nodes. Obtained results show that scaling from 30- to 20-nm node allows a write energy saving of about 43%, while the supply voltage that assures the minimum-energy write operation increases. [ABSTRACT FROM PUBLISHER]

Stateful in-memory logic (IML) is a promising paradigm to realize the unity of data storage and processing in the same die, exhibiting great feasibility to break the bottleneck of the conventional von Neumann architecture. On the roadmap toward developing such a logic platform, a critical step is the effective and efficient realization of a complete set of logic functions within a memory. In this paper, we report a realization of stateful reconfigurable logic functions via a single three-terminal magnetic tunnel junction (MTJ) device within a spintronic memory by exploiting the novel voltage-gated spin Hall-effect driven magnetization switching mechanism. This proposed reconfigurable IML methodology can be implemented within either a typical memory array or a cross-point array architecture. The feasibility of the proposed approach is successfully demonstrated with hybrid MTJ/CMOS circuit simulations. We believe our work may promote the research and development of the revolutionary IML for future non-von Neumann architectures. [ABSTRACT FROM PUBLISHER]

This paper reports on the impact of soft- and hard-switching conditions on the dynamic ON-resistance of AlGaN/GaN high-electron mobility transistors. For this study, we used a special double pulse setup, which controls the overlapping of the drain and gate waveforms (thus inducing soft and hard switching), while measuring the corresponding impact on the ON-resistance, drain current, and electroluminescence (EL). The results demonstrate that the analyzed devices do not suffer from dynamic R {\mathrm{\scriptscriptstyle ON}} increase when they are submitted to soft switching up to V{\text {DS}}= 600 V. On the contrary, hard-switching conditions lead to a measurable increase in the dynamic ON-resistance (dynamic- R \mathrm{\scriptscriptstyle ON}) . The increase in dynamic R \mathrm{\scriptscriptstyle ON} induced by hard switching is ascribed to hot-electrons effects: during each switching event, the electrons in the channel are accelerated by the high electric field and subsequently trapped in the AlGaN/GaN heterostructure or at the surface. This hypothesis is supported by the following results: 1) the increase in R \mathrm{\scriptscriptstyle ON} is correlated with the EL signal measured under hard-switching conditions and 2) the impact of hard switching on dynamic R \mathrm{\scriptscriptstyle ON} becomes weaker at high-temperature levels, as the average energy of hot electrons decreases due to the increase scattering with the lattice. [ABSTRACT FROM PUBLISHER]

This paper presents low insertion loss, high isolation, ultra-wideband double-pole-double-throw (DPDT) switch matrix designed in a 0.13- \mu \textm commercial high resistivity trap-rich silicon-on-insulator (SOI) CMOS process for the first time. The switches are designed using series–shunt–series configuration in a ring-type structure with input and output matching networks. Transistor width and transistor channel length effects on the wideband DPDT switch performance are thoroughly investigated. The designed switches achieve widest bandwidth from dc to 30 GHz with a low insertion loss of 2.5 dB and a high isolation of 32 dB up to 30 GHz. The measured input P1dB of designed switches is higher than 18 dBm. It was found both second and third harmonics can be improved by widening switch transistor channel width, and third harmonic can be improved by shortening channel length. The active chip area of designed $2 \times2$ switch matrix is very small size of only 0.28 mm $\times0.21$ mm. [ABSTRACT FROM PUBLISHER]

This paper presents a methodology to model GaN power HEMT switching transients. Thus, a compact model to predict devices’ pulse switching characteristics and current collapse reliability issue has been developed. Parasitic RC subcircuits and a standard double-pulse switching tester to model intrinsic parasitic effects and to analyze power dissipation of GaN power HEMT are proposed and presented. Switching transient including gate-lag and drain-lag is predicted for ideal (without trap) and nonideal (with trap) devices. The results are validated by and compared to 2-D finite-element technology computer-aided design simulations. The original aim of this exercise is to develop a fast (near-real-time) model which can predict dynamic behavior of single and multiple power GaN HEMTs used for the switching transients of GaN power devices at circuit level. [ABSTRACT FROM PUBLISHER]

In this paper, implication (IMP) operations are demonstrated in a circuit with two SiOx-based memristors and a CMOS transistor. Specifically, a circuit with two one-diode and one-resistor (1D1R) memory elements and a transistor are designed to perform the IMP operations. A circuit consisting of a $4 \times 4$ crossbar 1D1R memristor array together with selection transistors is proposed and used to realize the functionality of a one-bit, full adder in 43 steps. Compared with CMOS logic circuits, the advantages and disadvantages of memristor-enabled logic circuits are discussed. This result suggests that the memristor-enabled logic circuit is most suitable for low-power and high-density applications, as well as a simple and robust approach to realize programmable memcomputing chips compatible with large-scale CMOS manufacturing technology. [ABSTRACT FROM PUBLISHER]

This paper investigated the performance of flexible resistive random access memory devices based on simple spin-coated sol–gel-derived strontium titanate nickelate (STN) thin films on polyethylene terephthalate substrate. A high on/off ratio of 10^5 and a uniform current distribution were demonstrated. The strong bonding between bidentate ligands of nickel (II) acetylacetone and titanium metal ion enabled the chelation effect, which contributed to the stability of the STN thin film, especially for moisture resistivity. Fourier transform infrared spectroscopy analysis was utilized to examine the effects on the resistive switching behaviors after 90 days under an atmospheric environment according to the chelation effect of the STN thin films. The devices were fabricated on a flexible plastic substrate, and they exhibited excellent durability upon repeated bending tests. They demonstrated good potential application for flexible and low-cost memory devices. [ABSTRACT FROM PUBLISHER]

3-D integrations are unavoidable task for new emerging memories, including resistive switching random-access memory (RRAM), in order to overcome the market-leading nand flash. However, an RRAM crossbar array (CBA) suffers severe read margin degradation due to the sneak current, which becomes even more critical as the memory density increases with the 3-D integration. In this paper, we extend the two-port readout scheme for a 2-D CBA, proposed in our previous work, to the 3-D vertical structure. A closed-form expression of the operating principle is derived, and HSPICE simulation using a $32\times 32\times8$ vertical RRAM CBA considering practical circuit parameters verifies feasibility of the two-port scheme to the 3-D CBA. [ABSTRACT FROM AUTHOR]

The efficiency of the human brain in performing classification tasks has attracted considerable research interest in brain-inspired neuromorphic computing. The spiking neuromorphic architectures attempt to mimic the computations performed in the brain through a dense interconnection of the neurons and synaptic weights. A leaky-integrate-fire (LIF) spiking model is widely used to emulate the dynamics of the biological neurons. In this paper, we propose a spin-based LIF spiking neuron using the magnetoelectric (ME) switching of ferromagnets. The voltage across the ME oxide exhibits a typical leaky-integrate behavior, which in turn switches an underlying ferromagnet. Due to the effect of thermal noise, the ferromagnet exhibits probabilistic switching dynamics, which is reminiscent of the stochasticity exhibited by biological neurons. The energy efficiency of the ME switching mechanism coupled with the intrinsic nonvolatility of ferromagnets results in lower energy consumption, when compared with a CMOS LIF neuron. A device to system-level simulation framework has been developed to investigate the feasibility of the proposed LIF neuron for a hand-written digit recognition application. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use. [ABSTRACT FROM AUTHOR]

In this paper, we will present an overview of the latest results covering both Insulated Gate Bipolar Transistor (IGBT) and packaging technologies intended for demanding high-power applications. We will present the recently developed press pack module rated at 4500 V and 3000 A utilizing an advanced reverse conducting RC-IGBT for hard switching application, which together with the improved module layout yields the most powerful IGBT-based device up to date. For applications that require isolated modules, we will show our new dual IGBT module rated up to 3.3 kV and 450 A. The module layout was optimized to allow highly scalable converter designs with overall low stray inductances. This opens up new possibilities to further reduce losses due to the fact that the devices can be made thinner than today’s limits for achieving lower switching losses with soft performance. We will show the latest results from the enhanced trench IGBT-cell development and give an outlook for the power levels that can be achieved by combining the new cell with the RC-IGBT concept. [ABSTRACT FROM AUTHOR]

This paper presents a 512-column linear CMOS image sensor (CIS) with 32-stage digital time-delay integration (TDI) operation. A signal processing architecture consists of analog-front-ends, analog-to-digital converters (ADCs), and digital accumulators (DAs) are designed with optimization of timing, area, and power efficiency. An eight-column-shared 10-b successive approximation register ADC with data prediction switching technique and 11-b DA are proposed to achieve a data depth of 15 b after 32-stage TDI. The achieved signal-to-noise ratio boost is 14.84 dB after 32-stage TDI operation. The proposed linear TDI sensor is implemented in 0.11- \mu \textm TSMC backside illumination CIS technology with a line time of 104~\mu \texts , a pixel pitch of 7.5~\mu \textm , and a power consumption of 153.2~\mu \textW /column. [ABSTRACT FROM AUTHOR]

Vertical alignment liquid crystal (LC) cell driven by in-plane field with 3-D polymer network exhibited no pooling mura under an external mechanical pressure; however, the operating voltage of the device was increased, because the polymer network hinders field-induced reorientation of LC. In this paper, we adopted a modified cell structure in which a counter electrode on top substrate of the conventional mode is existed, to improve upon this drawback. The proposed device in which the polymer network is formed in bulk of vertically aligned LC layer shows a very fast response time of 2 ms (rise + decay), 57% reduction in operating voltage, and also keeps image quality although the cell is curved. [ABSTRACT FROM AUTHOR]

Bidirectional power transistors are essential components of several power electronics systems, such as matrix converters. In this paper, we present the operating principles, design considerations, and experimental characteristics of a novel planar gate 4H-SiC bidirectional insulated gate bipolar transistors. The impact of various drift layer and unit cell parameters on blocking, on-state, and switching performance has been evaluated by using numerical simulations, and critical performance tradeoffs have been discussed. Based on the optimized design, devices were fabricated on lightly doped free-standing n-type 4H-SiC wafers. Fabricated devices showed good conductivity modulation, with a forward voltage drop of 9.7 V at 50 A/cm2 at room temperature, which increased to 11.5 V at 150 °C. [ABSTRACT FROM AUTHOR]

This paper analyzes write errors in spin-torque switching due to thermal fluctuations in a system with perpendicular magnetic anisotropy. Prior analytical and numerical methods are summarized; a physics-based general 2-D Fokker–Planck equation (FPE) is solved numerically. Due to its computational efficiency and broad applicability to all switching regimes and system symmetries, the 2-D FPE has been used to study the relation between write error slope and material parameters as well as some emerging switching schemes. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a test system for active-matrix organic light emitting diode (AMOLED) panels with various pixel structures with the external compensation method. The proposed AMOLED panel test system employs universal data drive ICs to measure the current of a driving thin-film transistor (TFT) and the anode voltage of the OLED in various pixels by only programming the field-programmable gate array in the proposed test system. The universal data driver IC are fabricated and implemented in the proposed AMOLED panel test system whose test board is assembled with a 55-in full-high-definition AMOLED panel. A fabricated universal data driver IC includes 640 data channels with a 12-b linear gamma digital-to-analog converter and 12-bit variable current sources. To evaluate the repeatability error of the proposed panel test system, the current of the driving TFT is repeatedly measured and the measured maximum repeatability error is 9.8 nA. In addition, to evaluate the measurement accuracy of the proposed panel test system, the variation in the currents of the driving TFTs is measured and compensated for, and its maximum value after compensation is 26 nA. [ABSTRACT FROM PUBLISHER]

Devices with ferromagnetic layers possessing a perpendicular magnetic easy axis are of great interest due to miniaturization capability and thermal stability, retaining deeply scaled magnetic bits over long periods of time. While the tunneling magnetoresistance effect has significantly enhanced electrical reading of magnetic bits, fast and energy efficient writing of magnetic bits remains a challenge. Current-induced spin-orbit torques (SOTs) have been widely considered due to significant potential for fast and energy-efficient writing of magnetic bits. However, to deterministically switch the magnetization of a perpendicularly magnetized device using SOTs, the presence of a magnetic field is required, which offsets possible advantages and hampers applications. In this paper, a perpendicularly magnetized device is presented, which, without the need for a magnetic field, can be deterministically switched in both toggle and nontoggle modes using a damping-like SOT induced by an in-plane current pulse. This capability is realized by shaping the magnetic energy landscape. Present device does not require any materials other than those widely utilized in conventional spin-orbit devices. The device provides two orders of magnitude enhancement in switching energy-time product as compared with state-of-the-art perpendicularly magnetized devices operating on spin-transfer torques. [ABSTRACT FROM AUTHOR]

In this paper, indium-tin-oxide (ITO) was used to act as both insulator and top electrode in resistive random access memory (RRAM) on identical bottom substrates. This is achieved by cosputtering an ITO target with nitride (N2) or oxygen (O2) gas as the insulator; then capping by an ITO electrode, such that both the rectifier and RRAM characteristics can be achieved before and after a forming process, respectively. In contrast, using pure ITO as an insulator does not exhibit RRAM behavior. To verify the rectifier and RRAM characteristics, material analyses and electrical measurements at various temperatures were conducted. Reliability tests including retention and endurance were also applied to verify the resistance switching stability. Finally, the rectifier and RRAM conduction models were proposed to examine the resistance switching behaviors. By applying the ITO material as both electrode and insulator, the resistance switching characteristic with high reliability is thus obtained. [ABSTRACT FROM AUTHOR]

Spintronics is the exploitation of both the degree of freedom of electron that is spin as well as the charge, which leads to tremendous development in the field of microelectronic applications. In this paper, bimetallic Co–Ni-based spin FET device is fabricated, and its magnetoresistance behavior has been studied. While, spin current as a function of thickness of Co–Ni-based concatenable spin switch has been studied. The results obtained for spin current using simulation and experimentation show good agreement. [ABSTRACT FROM PUBLISHER]

The effect of voltage on the anisotropy of a magnetic tunnel junction (MTJ) is of substantial interest for low-power nonvolatile memory applications. In this paper, we develop a device-to-bit-cell level simulation framework for voltage-assisted switching of the MTJs, which can satisfactorily reproduce the published experimental data. Our simulation framework is based on a coupled Landau–Lifshitz–Gilbert–Slonczewski equation and nonequilibrium greens function formalism. Using this simulation framework, we investigate the effect of scaling the oxide thickness of an MTJ to enhance the electric field effect. Although it seems attractive for an isolated device, yet, in a bit-cell configuration, reducing the oxide thickness leads to an increase in the supply voltage. In addition, we demonstrate that the unipolar characteristic of the voltage-assisted switching leads to write failures depending on the initial state stored in the MTJ. We, therefore, suggest a read before write scheme exhibiting approximately $2\times $ improvement in the write energy consumption at a bit-cell level compared with a standard STT-MRAM for iso-oxide thickness. However, the latency overhead associated with voltage-assisted MTJs results in a $1.55\times $ degradation of the write speed. Moreover, our layout analysis indicates that the bit-cell area reduction is constrained by the metal pitch, in spite of smaller access transistors. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2) thin films show high potential for future embedded nonvolatile memory applications. However, HfO2 films besides their recently discovered ferroelectric behavior are also prone to undesired charge trapping effects. Therefore, the scope of this paper is to verify the possibility of the charge trapping during standard operation of the HfO2-based FeFET memories. The kinetics of the charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse ID – VG technique. Furthermore, the impact of the charge trapping on the important memory characteristics such as retention and endurance is investigated. [ABSTRACT FROM AUTHOR]

In this paper, the presence of filamentary current instabilities in the high resistance state of Ni/HfO2-based RRAM devices and their associated current fluctuations mechanisms are explored. After systematic measurements, the advanced weighted time-lag plot method is employed to accurately identify the contribution of multiple electrically active defects and to minimize the negative effect of the background noise. Special attention is given to the physical analysis of multilevel random telegraph noise (RTN) signals caused by both independent and interactive defects located in the vicinity of the conductive filament (CF), which may alter the tunneling path and induce large stochastic current fluctuations. In addition, irreversible current changes, owing to trap density variations inside or near the CF, are also identified. Finally, the voltage dependence of the RTN phenomena and the occurrence of stress-induced complex fluctuations is evaluated. [ABSTRACT FROM PUBLISHER]

Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy–performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal Ion/Ioff and Edyn/Eleak ratios are set only by circuit-level parameters as well as the device transfer characteristic off-state Soff, on -state Son, and effective Seff inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal Edyn/Eleak ratio is approximately (K/\2)(Seff/Soff) - \0.56(Son/Soff) - \0.56, where K ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for Soff, Son, and Seff are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope S is insufficient, since energy dissipation is set mainly by Seff and not by S. Finally, the general shape of the energy–delay curve is also set by these inverse slopes, with its steepness directly proportional to Son/Soff. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology. [ABSTRACT FROM AUTHOR]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

Deep spiking neural networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing studies on such computing models are developed with limited insights on the underlying hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this paper, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a deep spiking neural network capable of performing high-accuracy and low-latency classification tasks, where the neural computing unit is enabled by the stochastic switching behavior of a magnetic tunnel junction. The simulation studies indicate an energy improvement of $20 \times $ over a baseline CMOS design in 45-nm technology. [ABSTRACT FROM PUBLISHER]

In this paper, static and dynamic performances of an AlGaN/GaN-on-Si power FET utilizing the integrated photonic-ohmic drain (PODFET) were systematically investigated. The operational mechanisms of the PODFET, including both the conditions of photon generation and the related physical processes, were explained. The dynamic switching tests were carried out under two types of hard switching conditions. With the photon generation and channel current inherently switched ON and OFF in synchronization, the dynamic performances of the PODFET can be significantly enhanced owing to photon pumping of deep electron traps. In addition, the generated photons were proved to be confined in proximity of the drain terminal without causing adverse effects on the device performances (e.g., the OFF-state leakage degradation). [ABSTRACT FROM PUBLISHER]

Switching behavior in electron–hole bilayer tunnel FETs is known to be unaffected by the subthreshold swing limitation of 60 mV/decade imposed by thermal injection, due to the band-to-band tunneling phenomena on which they rely. However, in this paper, we show that, once parasitic lateral tunneling processes are suppressed by means of heterogate configurations, a new physical limitation arises at the onset of tunneling in this type of transistors, resulting from the interplay between field-induced quantum confinement and asymmetric concentrations of electrons and holes inside the channel. We demonstrate that this limitation comes from the fact that, regardless of the band profile sharpness, the tunneling distance at subband alignment cannot be reduced beyond a certain limit, which we find to be dependent on the body thickness and the material properties. [ABSTRACT FROM PUBLISHER]

Disordered ionic-bonded transition metal oxide thin-film transistors (TFTs) show promise for a variety of dc and RF switching applications, especially those that can leverage their low-temperature, substrate-agnostic process integration potential. In this paper, enhancement-mode zinc-oxide TFTs were fabricated and their switching performance evaluated. These TFTs exhibit the drain-current density of 0.6 A/mm and minimal frequency dispersion, as evidenced by dynamic current–voltage tests. A high-frequency power switch figure of merit $R_{{\mathrm{\scriptscriptstyle ON}}}Q_{G} of 359 \textm\Omega \,\cdot \, nC was experimentally determined for 0.75- \mu \textm long-channel devices, and through scaling 45.9 \textm\Omega \,\cdot \, nC is achievable for 11 V-rated devices (where R\mathrm{\scriptscriptstyle ON} is ON-state drain–source resistance, and QG is gate charge). An RF switch cutoff frequency fc of 25 GHz was measured for the same 0.75- \mu \textm TFT, whereas fc exceeding 500 GHz and power handling in the tens of watts are projected with optimization. [ABSTRACT FROM AUTHOR]

A comprehensive physical model on the resistive switching (RS) behaviors of bilayered TaOx-based RS access memory [resistive random access memory (RRAM)] is presented. In the model, the effects of the generation and recombination (G-R) of oxygen vacancies ( $V_{{\rm{O}}}$ ), phase transition (P-T) between Ta2O5 and TaO2, and the interaction (I-A) between Ta2O5 and TaOx layers are involved to explain the RS behaviors based on ab initio calculations. An atomistic Monte Carlo simulation method based on the model is developed to investigate the dynamic physical processes and reproduce the experimental phenomena. The impacts of G-R and P-T as well as the I-A effects on the RS behaviors of a bilayered Ta2O5/TaOx structure and the device performances are identified. This paper indicates that the G-R effect dominates the RS behaviors, and self-compliance is due to the I-A effect. Based on the simulations, the optimization guidance of a bilayered TaOx-based RRAM is presented. [ABSTRACT FROM AUTHOR]

A positive feedback (PF) mechanism was adopted for the first time in the cell string of a 3-D NAND flash memory where n+ and p+ regions are formed on both ends of the string to implement a diode-type cell string. The body consists of a tube-type poly-Si channel. To generate the PF in the channel during a read operation, a new read operation scheme is proposed. In this paper, the simulator was calibrated in terms of trap density ( D\mathrm {it}) of a poly-Si channel extracted from fabricated 3-D NAND flash memory cells. By utilizing the PF, a NAND flash memory cell in a cell string has a steep subthreshold swing of <1 mV/decade. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed, low power, infinite endurance, and easy integration with CMOS circuits. However, a relatively high current flowing through an MTJ is always required by most of the switching mechanisms, which results in a high electric field in the MTJ and a significant self-heating effect. This may lead to the dielectric breakdown of the ultrathin ( $\sim 1$ nm) oxide barrier in the MTJ and cause functional errors of hybrid CMOS/MTJ circuits. This paper analyzes the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier and proposes an SPICE-compact model of the MTJ. The simulation results show great consistency with the experimental measurements. This model can be used to execute a more realistic design according to the constraints obtained from simulation. The users can estimate the lifetime, the operation voltage margin, and the failure probability caused by TDDB in the MTJ-based circuits. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) has been proposed as an artificial synapse in neuromorphic circuits due to its tunable resistance, low power operation, and scalability. For the development of high-density neuromorphic circuits, it is essential to validate the state-of-the-art bistable RRAM and to introduce small-area building blocks serving as artificial synapses. This paper introduces a new synaptic circuit consisting of a one-transistor/one-resistor structure, where the resistive element is a HfO2 RRAM with bipolar switching. The spike-timing-dependent plasticity is demonstrated in both the deterministic and stochastic regimes of the RRAM. Finally, a fully connected neuromorphic network is simulated showing online unsupervised pattern learning and recognition for various voltages of the POST spike. The results support bistable RRAM for high-performance artificial synapses in neuromorphic circuits. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the influence of the drain electrode on the dynamic switching behavior of AlGaN/GaN high-electron-mobility transistors on Si substrate. By adding a field plate to the drain electrode, a dramatic increase in the dynamic ON-resistance dynR \mathrm{\scriptscriptstyle ON} was identified. The dispersion effect is correlated with the high electric field below the drain field plate (DFP), the onset of which is caused by the full electron depletion from both the channel and the GaN cap layer. We show that the electron distribution is modified by the passivation method, backside bias, or surface charges and, hence, shifts the onset voltage of the trapping effect. Trapped electrons underneath the DFP are thought to be responsible for the measured rise of the dynR \mathrm{\scriptscriptstyle ON} . With the introduction of an extended ohmic drain contact, the influence of a metallization overhang at the drain edge can be suppressed. The detrapping energies associated with the surface defects were determined to 0.2, 0.3, and 0.7 eV, respectively. Simulations and measurements indicate that charges inside the passivation below the DFP worsen the switching behavior. [ABSTRACT FROM AUTHOR]

Resistive-switching memory (RRAM) is attracting a widespread interest for its outstanding properties, such as low power, high speed, and good endurance. A crucial concern for RRAM is the current fluctuation, which induces significant broadening of resistance levels in single-bit and multilevel applications. This paper addresses low-frequency fluctuations focusing on $1/f$ and random telegraph noise contributions in intrinsic, i.e., typical, cells. The current fluctuations are studied in both the time and frequency domains, and the analytical models are presented to predict the resistance broadening for different RRAM states. Finally, the resistance dependence of noise and broadening is studied with the support of a 3-D finite-element model. [ABSTRACT FROM AUTHOR]

Noise in resistive switching memory (RRAM) is among the main concerns due to its impact on the reliability of single-bit and multilevel cell devices. Although noise in typical RRAM cells is understood fairly well, the statistics of noise and the presence and impact of statistical tails in the current fluctuation is what mostly affects the RRAM reliability at the array level. This paper addresses current noise in RRAM arrays, focusing on high-resistance state distribution and its broadening with time. We highlight two main contributions to the tail behavior, namely, random walk (RW) and random telegraph noise (RTN) with random start and stop. We provide evidence for a time decay of RW amplitude with time, which we explain by time-dependent stabilization of defects. We finally develop a statistical Monte Carlo model for noise, which is capable of explaining the broadening of the resistance distribution based on a physical description of RW and RTN components. [ABSTRACT FROM AUTHOR]

In this paper, we investigate in depth Forming, SET, and Retention of conductive-bridge random-access memory (CBRAM). A kinetic Monte Carlo model of the CBRAM has been developed considering ionic hopping and chemical reaction dynamics. Based on inputs from ab initio calculations and the physical properties of the materials, the model offers the simulation of both the Forming/SET and the Data Retention operations. It aims to create a bond between the physics at atomic level and the device behavior. From the model and experimental results obtained on decananometric devices, we propose an understanding of the physical mechanisms involved in the CBRAM operations. Using the consistent Forming/SET and Data Retention model, we obtained good agreement with the experimental data. Finally, the impact of each layer of the CBRAM on the Forming/SET behavior is decorrelated, allowing an optimization of the performance. [ABSTRACT FROM AUTHOR]

In this paper, the nonlinear switching mechanism of the Ti/HfO2/Al2O3/TiN crossbar structure resistive random access memory device with good reliability is investigated. The nonlinearity of the device can be revealed by inserting a large bandgap of an Al2O3 thin layer between the TiN bottom electrode and the HfO2 switching film. The nonlinear switching mechanism caused by Flower–Nordheim tunneling involves the tunneling barrier of the Al2O3 layer. Besides, the nonlinear behavior is also sensitive to the thickness of the inserting Al2O3 layer. A high nonlinear factor of 37, large endurance more than 10^4 , and good retention properties are achieved in the Ti/HfO2/Al2O3 (1-nm)/TiN structure. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]