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As a promising new generation of nonvolatile memory, HfO2-based resistive random-access memory (RRAM) has attracted extensive research. However, the problem of data retention has prevented its industrial production as embedded memory. In this paper, from the microscopic understanding, a Monte Carlo simulator is developed to investigate the effects of an oxygen reservoir layer (ORL) on the resistance instability of HfO2-based RRAM. The evolution of conductive filaments (CF) during the retention degradation is visualized by our simulation considering the physical mechanisms of oxygen ions absorbed and released by the ORL. The simulation results are further validated with experiments to provide the prediction of retention performance of RRAMs with different ORLs and operation schemes. [ABSTRACT FROM AUTHOR]

This paper deals with the design of an ac switch structure for specific ac mains applications 230 V–50 Hz. The targeted power level is about a hundred watts, and the currently used converter circuits make use of bidirectional switches that are realized using anti-series connected MOS transistors. Despite the improvements in performance provided by some of these structures, their fabrication cost is still high and limits their widespread diffusion in a market shared with the triac. To replace the triac, an original current and voltage bidirectional bipolar device called a Bipolar ac (Bipac) is proposed, designed, realized, and characterized. It can be controlled both to turn-on and turn-off with respect to a single reference electrode. It exhibits a very low ON-state voltage drop that makes it interesting for specific mains applications with low load current (0.5 $\text{A}_{{\text {rms}}}$). The study of the Bipac structure is carried out using 2-D Sentaurus physical simulations. The Bipac structure is realized on n-type and on p-type substrates for two different wafer thicknesses. The operating modes of the monolithic bidirectional Bipac switch were validated through electrical characterizations. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage V\mathrm{ set} , the reset voltage V\mathrm{ reset} , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array. [ABSTRACT FROM AUTHOR]

The focus of this paper is to understand the impact of the material properties of GaN, exploited using a vertical device, in power switching by estimating switching loss. The study was performed with a cascoded current aperture vertical electron transistor (CAVET). The normally OFF device was simulated and analyzed using a Silvaco ATLAS 2-D drift diffusion model integrated to SPICE-based circuit simulator. Besides evaluating the performance space and, hence, potential application space for GaN CAVETs, this paper presents significant accomplishment in establishing a device to circuit model, thereby, offering a reliable method of evaluating GaN-based power transistors. The accuracy of the model was established through the excellent agreement of simulated data with the data sheet specs of a commercial cascoded GaN high electron mobility transistor. The model was successfully applied to compare SiC MOSFETs with GaN CAVETs. A cascoded GaN CAVET has $2\times $ faster switching time, $3\times $ lower switching loss compared with standard commercial SiC MOSFET, owing to the higher electron mobility in GaN. Operating at frequencies of megahertz with low power loss, a GaN CAVET will, therefore, lead to smaller converter size and higher system efficiency. [ABSTRACT FROM PUBLISHER]

In this paper, the requirements of device cross section and aspect ratio (AR) are examined to facilitate steep switching in heavily doped 3-D multiple gate junctionless (JL) transistors. It is shown through well-calibrated simulations and physical insights that the sharp OFF-to- ON switching action is predominantly governed by the area of cross section (${A} _{\textsf {cross}}$) instead of the gate length. A 3-D JL architecture preferably oriented toward a planar topology, i.e., with wider fin and low AR, is conducive for steep switching as a greater bulk area is available for impact ionization. On the contrary, narrow vertical architectures with AR > 1 suppress ${A} _{\textsf {cross}}$ in the bulk and are less likely to support the steep current transition. Steep switching specific scaling methodology is showcased to attain a sharp increase in drain current with a sub-60 mV/decade swing in a tri-gate JL transistor along with an associated negative value of total gate capacitance. [ABSTRACT FROM AUTHOR]

Due to outstanding properties of silicon carbide (SiC) and unipolar current conduction mechanism, the active chip size of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) is significantly shrunk, which significantly improves switching performance. However, the termination region cannot be scaled down due to the existence of high breakdown electric field enclosing active region. Therefore, a SiC MOSFET switching loss model considering termination region effect is proposed in this paper with revealing physical insights into termination region during switching process. Furthermore, through theoretical analysis, model establishment, and simulation results, the loss breakdown under various blocking voltages (800, 1000, and 1200 V) for 1-, 3-, and 6-A current rated devices is obtained. ${E}_{\textsf {term}}$ and ${E}_{\textsf {acti}}$ as intrinsic loss of turn-on process make a significant contribution to the total switching loss under fast gate drive condition. The model shows that the turn-on and turn-off losses are under and overestimated, respectively, by using the commonly used electrical measurement. The loss from termination region aggravates the underestimation of turn-on loss and overestimation of turn-off loss further. The proposed loss estimation equation could provide accurate loss to help choose device and design power circuit for power electronic community. The results also raise new perspective to edge termination of efficient/reliable SiC MOSFET for device people. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

In the study of resistive random access memory using GeTeOx film as the switching layer, the device performed excellent property of bipolar resistive switching (BRS), which could be gradually transformed to the complementary resistive switching (CRS) by varying SET process current compliance. The conductive filament conduction mechanism of BRS could be verified by electrical characteristics and reliable data fitting. Through increasing current compliance of the SET process, CRS could be achieved due to higher activity of oxygen vacancies originated from the intensified thermal effect. This paper was beneficial to understand the switching mechanisms of BRS and CRS and provide a method to realize interconversion. Moreover, it was also a potential and promising device to be applied in the neurosynaptic biomimetic field. [ABSTRACT FROM AUTHOR]

A new concept high-voltage pseudo-p-channel lateral double-diffused MOS (p-LDMOS) with multiple current paths for conduction is proposed and investigated in this paper. The proposed power device consists of two hole current paths (p-channel MOS device) and one electron current path (n-channel MOS device). The gate of the n-channel device is automatically controlled by an induced signal inside the chip, thus the proposed device can be considered as a p-LDMOS with more than 66.2% reduction of specific on-resistance in comparison with the conventional p-LDMOS device. Furthermore, the proposed device has a much better safe operation area, since the compensation of the electric flux density brought by electron and hole currents. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel technique of realizing discrete-time (D-T) signal amplification using Nano-Electro-Mechanical systems (NEMS). The amplifier uses mechanical switches instead of traditional solid-state devices and acts as an inherent sample and hold amplifier. The proposed NEMS D-T amplifier operates on a wide dynamic range of signals without consuming the dc power. Moreover, the proposed amplifier does not suffer from the leakage current and the nonlinearity associated with the sampling ohmic switch. As a proof of concept, the proposed NEMS D-T amplifier is demonstrated in circuit simulations using the calibrated verilog-A models of the NEMS device. The simulated amplifier achieves a gain of ~5, handles the maximum differential input signal of 0.65 V, and consumes only $0.6~\mu \text{W}$ of power for a sampling frequency of 100 kHz. The nonidealities present in the proposed amplifier are highlighted and possible ways to overcome them are discussed. Finally, the design considerations required for the NEMS D-T amplifier are described. [ABSTRACT FROM AUTHOR]

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor ${Q}_{F2}={(}{\lambda {E}_{c}}/{R_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}}{)}$ along with ${Q}_{G}$ and ${T}_{j\textsf {max}}$ may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where $\lambda $ and ${E}_{c}$ are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ is the specific on-state electrical resistance, ${Q}_{G}$ is the gate charge, and ${T}_{j\textsf {max}}$ is the maximum junction temperature of the semiconductor power device, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate the linear conductance-change characteristics of a conductive-bridging RAM (CBRAM) to be employed as an artificial synapse device in neuromorphic systems. The CBRAM with a bilayer electrolyte structure (${\mathrm {Cu/Cu}}_{{2}-{x}}\text{S}$ / $\mathrm {WO}_{{3}-{x}}$ /W) exhibits analog switching behavior during the depression process due to the well-controlled dissolution of the conductive filament. To analyze the origin of this motion, we investigate the effective voltage applied to $\mathrm {Cu}_{{2}-{x}}\text{S}$ and $\mathrm {WO}_{{3}-{x}}$. Our findings reveal that $\mathrm {Cu}_{{2}-{x}}\text{S}$ , acting as a voltage divider, helps in suppressing the large voltage drop in $\mathrm {WO}_{{3}-{x}}$ , where the formation/dissolution of filament occurs. Furthermore, due to the diode-like characteristics of $\mathrm {Cu}_{{2}-{x}}\text{S}$ and the division of voltage drop between $\mathrm {WO}_{{3}-{x}}$ and $\mathrm {Cu}_{{2}-{x}}\text{S}$ , an optimum programming energy is applied to $\mathrm {WO}_{{3}-{x}}$ during the depression process. This leads to linear conductance-change characteristics under identical pulses. However, abrupt conductance-change characteristics are observed during the potentiation process. Thus, we use only the device characteristics of the depression part for the neuromorphic system. An excellent classification accuracy is achieved due to the linear conductance-change characteristics and optimized pulse conditions. [ABSTRACT FROM AUTHOR]

The accurate calculation of switching voltage (${V}_{s}$) is necessary for the reliable and low-power operation of monolithic 3-D (M3D) CMOS-nanoelectromechanical (NEM) hybrid reconfigurable logic circuits because ${V}_{s}$ corresponds to the operating voltage (${V}_{\text {dd}}$) of NEM memory switches. In this paper, based on the Euler–Bernoulli equation, the physics-based analytical model is proposed to determine ${V}_{s}$. The accuracy of the proposed model is verified by both the finite-element analysis and experimental results. Our proposed model shows >3% error compared with experimental data. Also, the design guidelines of NEM memory switches are presented in terms of minimum ${V}_{s}$ (${V}_{s\_{}{m}}$) and device dimensions. [ABSTRACT FROM AUTHOR]

A comprehensive study on the dielectric modulated (DM) drift region for power devices is presented in this paper. The performance of this drift region structure is theoretically analyzed and compared with other two structures: conventional and superjunction. In this paper, a study is focused on switching performance. The C – V relationships during switching are analytically derived, and the depletion widths predicted by the proposed analytical model agree well with simulation in a wide reverse bias region. The switching energy loss is evaluated based on the analytical model and its accuracy is verified by 2-D simulations. An effective depletion charge QD is defined as E\mathrm {loss} / breakdown voltage (BV), from which a figure of merit (FOM) of R\mathrm{\scriptscriptstyle ON,\mathrm {sp}}{}^\ast QD is proposed to compare the performances of these different drift region structures, considering both the conduction and switching losses. The discussions in part I on Si and silicon carbide device structures are extended in part II to include FOMs. It is found that the DM drift region structures show better R\mathrm{\scriptscriptstyle ON,\mathrm {sp}} -BV tradeoffs compared with the conventional structures, but slighter inferior FOMs. However, DM structures are still attractive for applications, where switching loss is less critical than the conduction loss, such as low frequency or soft switching. [ABSTRACT FROM PUBLISHER]

This paper presents a detailed numerical analysis of work-function modulated cylindrical gate metal–oxide–semiconductor field-effect transistor (MOSFET)-based CMOS inverter. Introduction of work-function modulation in the control gate of dual-material cylindrical gate MOSFET exhibits significant reduction in short-channel effects (SCEs) and threshold voltage. The analytic potential-based model of this device is developed by considering 2-D Poisson’s equation in the cylindrical coordinate system. Development of the numerical model is based on certain boundary conditions to study the electrostatic behavior effectively. The results thus obtained from the analytical model are in good agreement with the model developed in the TCAD simulator. Improved drain current, reduced threshold voltage, immunity against SCEs, lower circuit delay, and high-speed switching have made this device a leader in CMOS logic family. [ABSTRACT FROM AUTHOR]

Mott materials have been investigated since late 1950s for their remarkably abrupt insulator to metal transition (IMT) in response to changes in temperature, strain, or electrical stimulus. Interest in these materials has been revived by recent demonstration of nanosecond-scale switching along with reproducible and fully reversible transitions in VO2-based thin film devices. These phenomena make VO2-based Mott insulator devices technologically relevant for various applications, such as memory selectors, logic switches, and building blocks for neuromorphic computing. Several groups have provisionally attributed the IMT switching to Joule heating. However, an electrothermal device simulation framework that self-consistently reproduces IMT phase transition, and in addition, explaining a variety of electrical/optical phenomena associated with IMT is still lacking. In this paper, we develop a self-consistent electrothermal device simulation framework which captures these key experimental attributes of IMT using VO2 as a model material. This framework will enable predictive modeling as well as provide insight on switching mechanisms and design of novel Mott insulator devices. [ABSTRACT FROM AUTHOR]

A new oscillational phenomenon has been found in high-biased semi-insulating (SI) 4H-SiC photoconductive semiconductor switches (PCSSs) with high densities of vanadium and nitrogen dopants, and this oscillational phenomenon has no relationship with the laser wavelength, bias voltage, the charge capacitor, and the shape/size of the 4H-SiC PCSS. This paper shows that the photo activated charge domain theory in SI GaAs PCSS may explain this phenomenon. Due to the high densities of vanadium and nitrogen dopants, the intervalley scattering may occur in the 4H-SiC PCSS, and the space charge field region will appear in the 4H-SiC PCSS for the electrons accumulation. This region looks upon an equivalent capacitor, when the accumulation of the electrons is over, the equivalent capacitor will discharge, and the oscillational phenomenon appears. [ABSTRACT FROM AUTHOR]

This paper presents low insertion loss, high isolation, ultra-wideband double-pole-double-throw (DPDT) switch matrix designed in a 0.13- \mu \textm commercial high resistivity trap-rich silicon-on-insulator (SOI) CMOS process for the first time. The switches are designed using series–shunt–series configuration in a ring-type structure with input and output matching networks. Transistor width and transistor channel length effects on the wideband DPDT switch performance are thoroughly investigated. The designed switches achieve widest bandwidth from dc to 30 GHz with a low insertion loss of 2.5 dB and a high isolation of 32 dB up to 30 GHz. The measured input P1dB of designed switches is higher than 18 dBm. It was found both second and third harmonics can be improved by widening switch transistor channel width, and third harmonic can be improved by shortening channel length. The active chip area of designed $2 \times2$ switch matrix is very small size of only 0.28 mm $\times0.21$ mm. [ABSTRACT FROM PUBLISHER]

The physics of the different failure modes that limit the maximum avalanche capability during unclamped inductive switching (UIS) in punchthrough (PT) and not PT (NPT) insulated-gate bipolar transistor (IGBT) structures is analyzed in this paper. Both 3-D electrothermal numerical simulations and experimental evaluations support the theoretical analysis. Experimental results for UIS test show that, at low time duration (or inductance value) of the test, the UIS limit moves from energy limitation to current limitation. While the energy limitation is well known, the current-limited failures are less studied. In this paper, the current limit for UIS test is analyzed in detail, and the cause is attributed to a filamentary current conduction due to the presence of a negative differential resistance (NDR) region in the IC– VCE curve in breakdown. The filamentary current conduction locally increases the current density causing early device latch-up and possible device failure at a current much lower than the one dictated by energy limitations. The physical parameters that affect both the onset of NDR region and the failure current are discussed for both an NPT trench IGBT structure with a local lifetime control and a PT trench IGBT structure with a field-stop layer. [ABSTRACT FROM PUBLISHER]

Current collapse is a phenomenon that increases the channel resistance during the switching process when the high gate and drain voltages are applied. The effect can be found from GaN-based high-electron mobility transistors (HEMTs) and is an obstacle for their applications to power electronics. There have been numerous reports on suppressing current collapse using semiconductor process technologies. In this paper, an enhancement mode (E-mode) AlGaN/GaN/AlGaN double heterostructure was proposed. The current collapse phenomena were studied on devices of E-mode MIS and Schottky gate HEMTs. The results indicate the suppression of current collapse for devices with double heterostructure. [ABSTRACT FROM AUTHOR]

Vertical alignment liquid crystal (LC) cell driven by in-plane field with 3-D polymer network exhibited no pooling mura under an external mechanical pressure; however, the operating voltage of the device was increased, because the polymer network hinders field-induced reorientation of LC. In this paper, we adopted a modified cell structure in which a counter electrode on top substrate of the conventional mode is existed, to improve upon this drawback. The proposed device in which the polymer network is formed in bulk of vertically aligned LC layer shows a very fast response time of 2 ms (rise + decay), 57% reduction in operating voltage, and also keeps image quality although the cell is curved. [ABSTRACT FROM AUTHOR]

This paper analyzes write errors in spin-torque switching due to thermal fluctuations in a system with perpendicular magnetic anisotropy. Prior analytical and numerical methods are summarized; a physics-based general 2-D Fokker–Planck equation (FPE) is solved numerically. Due to its computational efficiency and broad applicability to all switching regimes and system symmetries, the 2-D FPE has been used to study the relation between write error slope and material parameters as well as some emerging switching schemes. [ABSTRACT FROM PUBLISHER]

In this paper, indium-tin-oxide (ITO) was used to act as both insulator and top electrode in resistive random access memory (RRAM) on identical bottom substrates. This is achieved by cosputtering an ITO target with nitride (N2) or oxygen (O2) gas as the insulator; then capping by an ITO electrode, such that both the rectifier and RRAM characteristics can be achieved before and after a forming process, respectively. In contrast, using pure ITO as an insulator does not exhibit RRAM behavior. To verify the rectifier and RRAM characteristics, material analyses and electrical measurements at various temperatures were conducted. Reliability tests including retention and endurance were also applied to verify the resistance switching stability. Finally, the rectifier and RRAM conduction models were proposed to examine the resistance switching behaviors. By applying the ITO material as both electrode and insulator, the resistance switching characteristic with high reliability is thus obtained. [ABSTRACT FROM AUTHOR]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

In this paper, nonpolar resistive switching behavior is reported for the first time in a SZO-based memory device. The electrode materials used which have different conductivities affect the resistive switching properties of the device. The AI/V:SZO-LNO/Pt device shows nonpolar switching behavior, whereas the AI/V:SZO/LNO device has bipolar switching property. The resistance ratios of these two devices are quite distinct owing to the difference between the resistance of low resistance states. The AI/V:SZO-LNO/Pt device with lower resistive switching voltages (±7 V turn on and ±2 V turn off) and higher resistance ratio (107) is more suitable for practical applications compared to the AI/V:SZO/LNO device. The switching speed of the AI/V:SZO-LNO/Pt device is 10 ns, which is the fastest speed that has ever been reported. The conduction mechanisms, nondestructive readout property, retention time, and endurance of this device are also reported in this paper. [ABSTRACT FROM AUTHOR]

Disordered ionic-bonded transition metal oxide thin-film transistors (TFTs) show promise for a variety of dc and RF switching applications, especially those that can leverage their low-temperature, substrate-agnostic process integration potential. In this paper, enhancement-mode zinc-oxide TFTs were fabricated and their switching performance evaluated. These TFTs exhibit the drain-current density of 0.6 A/mm and minimal frequency dispersion, as evidenced by dynamic current–voltage tests. A high-frequency power switch figure of merit $R_{{\mathrm{\scriptscriptstyle ON}}}Q_{G} of 359 \textm\Omega \,\cdot \, nC was experimentally determined for 0.75- \mu \textm long-channel devices, and through scaling 45.9 \textm\Omega \,\cdot \, nC is achievable for 11 V-rated devices (where R\mathrm{\scriptscriptstyle ON} is ON-state drain–source resistance, and QG is gate charge). An RF switch cutoff frequency fc of 25 GHz was measured for the same 0.75- \mu \textm TFT, whereas fc exceeding 500 GHz and power handling in the tens of watts are projected with optimization. [ABSTRACT FROM AUTHOR]

In this paper, a distributed circuit model for on-die power distribution network in single and 3-D ICs is developed, and a set of difference equations are derived based on the circuit model and numerically solved using the finite-difference method. Both IR-drop and simultaneous switching noise, two components of power supply noise (PSN), are iteratively solved in time domain, thereby enabling a transient analysis of PSN. Under the assumptions that on-die power/ground pads, power density, and decoupling capacitors are uniformly distributed, PSN within a unit cell is accurately simulated with <1% error compared with HSPICE simulation. By reducing modeling grid fineness, the numerical modeling approach is applied to a full chip that has multiple blocks with nonuniform power/ground pads, power density, and decoupling capacitance density. Based on full-chip modeling, the PSN distribution of a two-die stack is simulated, and the impact of increasing decoupling capacitance and power/ground pads is investigated. [ABSTRACT FROM PUBLISHER]

GaN-based devices are seen as ideal candidates for power-switching applications. For the acceptance of GaN-based devices by module designers, obtaining enhancement-mode (e-mode) behavior in GaN-based heterostructure field-effect transistors (HFETs) has long been in the focus. Although the gate-injection approach appears to be the most promising one to achieve e-mode devices, using a double heterostructure in conjunction with a gate insulator has still its advantages, such as steeper turn-ON characteristics and lower leakage currents. An analytical expression to predict the threshold voltage V\mathrm {th} for a given double heterostructure device has not yet been derived. Moreover, neither an evaluation of the tradeoff between V\mathrm {th} and ON-state resistance $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}} has been performed to date. This paper addresses these two aspects. We will show an analytical expression for a metal–insulator–semiconductor double HFET (MIS-DHFET), which in certain cases is also valid for the gate-injection transistor. On the basis of this, we will discuss the actual influence of the Al concentration in the backbarrier on V\mathrm th . We will further employ technology computer aided design (TCAD) device simulations to evaluate the impact on R{\text {ds},\mathrm {\scriptstyle {{ON}}}} when using MIS-DHFETs. It will be shown that by implementing a double heterostructure in MIS devices, it is possible to suppress the typically observed negative V\mathrm {th} –oxide thickness relationship while maintaining a constant $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}}$ . [ABSTRACT FROM AUTHOR]

This paper presents the development of electrostatically actuated polymer-based microelectromechanical relays as a potential replacement for organic field-effect thin-film transistors in order to enable near-zero-power flexible transparent large-area electronics. A low-temperature five-mask surface-micromachining process is developed to fabricate two types of prototype relays: purely polymeric and partially polymeric (inorganic–organic hybrid) relays. Experimental results demonstrate the operation of the prototypes as a switch, showing immeasurably low OFF-state leakage current ( $\sim 10$ fA), abrupt switching behavior and high ON/OFF-current ratio (>105 over an effective input voltage swing of ≤100 mV), small hysteresis voltages (≤100 mV), and low contact adhesive forces (<10 nN/ \mu \text{m}^{2}) . The influence of temperature on switching characteristics, including hysteresis voltages, is investigated as well. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the influence of the drain electrode on the dynamic switching behavior of AlGaN/GaN high-electron-mobility transistors on Si substrate. By adding a field plate to the drain electrode, a dramatic increase in the dynamic ON-resistance dynR \mathrm{\scriptscriptstyle ON} was identified. The dispersion effect is correlated with the high electric field below the drain field plate (DFP), the onset of which is caused by the full electron depletion from both the channel and the GaN cap layer. We show that the electron distribution is modified by the passivation method, backside bias, or surface charges and, hence, shifts the onset voltage of the trapping effect. Trapped electrons underneath the DFP are thought to be responsible for the measured rise of the dynR \mathrm{\scriptscriptstyle ON} . With the introduction of an extended ohmic drain contact, the influence of a metallization overhang at the drain edge can be suppressed. The detrapping energies associated with the surface defects were determined to 0.2, 0.3, and 0.7 eV, respectively. Simulations and measurements indicate that charges inside the passivation below the DFP worsen the switching behavior. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model for metal–oxide-based resistive random access memory (RRAM) devices with bipolar switching characteristics. The switching mechanism relies on the dynamics of conductive filament growth/dissolution in the oxide layer. Besides the dc and pulsed $I$ – $V$ characteristics, the model also captures the RRAM retention property and the temperature dynamics. The model parameters and the device variations are calibrated from the experimental data of IMEC HfOx-based RRAM devices. The model has been implemented in Verilog-A, which can be easily adapted into the SPICE simulator for the circuit-level analysis. As case studies, we demonstrate the model’s applications on the programming scheme design of the 1-transistor-1-resistor array, as well as the design space exploration of the 1-selector-1-resistor cross-point array toward megabit-level. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of cell variability on the read performance of the one-selector one-resistor (1S1R) cross-point array. A variability-aware array-sizing analysis methodology is introduced, considering three independent variability sources, namely, the data pattern randomness, the selector variability, and the resistive switching element (RSE) variability. By analyzing the impact of each variability factor separately, we show that the data pattern randomness is not an important contributor for the read margin (RM) degradation. While the intrinsic RSE variability reflected in the narrowing of the ON/OFF RSE window degrades the RM, the selector variability adds to this further, mainly affecting the ON-state readout current, and causing extra RM degradation. To accommodate cell variability and guarantee acceptable read performance, additional cell performance margin is required. The 1S1R requirements are extrapolated for 1-Mb array, assuming variability-affected cells. It is found that, with a typical selector variability, a minimal RSE window of 5 and a selector half-bias nonlinearity of $\sim 8000$ are required to achieve at least 10% RM. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

Logic gates based on the resistive switching random access memory (RRAM) allow normally-off digital computing because of the nonvolatile nature of the RRAM switch [1]. An extremely small area consumption can be achieved because of the 2–terminal structure of the RRAM switch and its capability of 3-D stacking. However, the details of RRAM organization within the array must be thoroughly investigated. This paper discusses the array organization and the select/unselect schemes of the RRAM logic circuits. We demonstrate a 1-bit adder to support the high functionality of RRAM logic. These results support RRAM as a promising technology for nonvolatile logic circuits beyond CMOS. [ABSTRACT FROM AUTHOR]

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) is the most promising converter topology for medium- and high-power applications. One of the main concerns in the operation of the MMC, particularly for high-power applications, is its efficiency, which should be maximized. Silicon Carbide (SiC)-based devices have the potential to provide significant efficiency improvement compared with silicon devices. However, the possibility and impact of using SiC-based devices instead of silicon devices for high-power conversion have not been thoroughly explored. This paper reports on the results obtained from a detailed study to evaluate the performance of MMCs based on medium-voltage SiC MOSFETs and diodes with hybrid MMCs that employ silicon IGBTs and SiC diodes. The results are based on detailed circuit simulations that use simple physics-based circuit models. The study suggests the potential for significant efficiency gain for MMCs based on SiC power devices. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the properties of the trap with activation energy equal to 0.6 eV, which has been demonstrated to be responsible for current collapse (CC) in AlGaN/GaN HEMTs. The study was carried out on AlGaN/GaN HEMTs with increasing concentration of iron doping in the buffer. Based on pulsed characterization and drain current transient measurements, we demonstrate that for the samples under investigation: 1) increasing concentrations of Fe-doping in the buffer may induce a strong CC, which is related to the existence of a trap level located 0.63 eV below the conduction band energy and 2) this trap is physically located in the buffer layer, and is not related to the iron atoms but—more likely—to an intrinsic defect whose concentration depends on buffer doping. Moreover, we demonstrate that this level can be filled both under OFF-state conditions (by gate-leakage current) and under ON-state operation (when hot electrons can be injected to the buffer): for these reasons, it can significantly affect the switching properties of AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

A compact microelectromechanical (MEM) switch design and associated family of logic gates, memory cells, and other basic very-large-scale integration (VLSI) digital circuit sub blocks are proposed to ensure zero crowbar current in addition to zero leakage current while minimizing mechanical delay. The circuit design methodology introduced in this paper also provides for lower device count and hence lower operating power consumption. A prototype of the MEM switch design is demonstrated. [ABSTRACT FROM PUBLISHER]

To allow for novel memory and computing schemes based on the resistive switching memory (RRAM), physically based compact models are needed. This paper presents a new analytical model for HfO2-based RRAM, relying on a simplified description of the conductive filament (CF) in terms of its diameter and gap length. The set and reset operations are described by CF growth and gap opening, respectively, activated by the local field and temperature. The analytical model is then used to describe the switching dynamics in the complementary resistive switch (CRS), consisting of an antiserial connection of two resistive devices. The impact of the gap resistivity on the CRS characteristics is discussed, highlighting the tradeoff between off-state leakage and set/reset window. [ABSTRACT FROM AUTHOR]

This paper presents a novel 2-D–3-D switchable gate driver circuit for active-matrix liquid crystal displays (AMLCDs) applications using the hydrogenated amorphous silicon (a-Si:H) technology. While consisting of 12 thin-film transistors (TFTs), the proposed gate driver circuit includes a pull-up circuit, two alternative circuits, and a key pull-down circuit. To provide a stable output waveform for switching between the 2-D and 3-D modes in AMLCD panel, the proposed circuit can improve the threshold voltage shift of a-Si:H TFT using reversed bias stress. Based on a real circuit integrated on glass with a standard five-mask process applied to a large-sized FHD TFT-LCD panel, the layout area of each gate driver circuit is 359.25 \mum\times\, 2296.25 \mum . In addition, the power consumption of a 12-stage gate driver circuit is 3.25 and 7.21 mW, while operating at 2-D and 3-D modes, respectively. Measurement results indicate that the output waveform, including output voltage, rising time, and falling time can be stabilized and made almost equal to the initial state after the reliability test at 100 ^\circC over 240 h. [ABSTRACT FROM AUTHOR]

A highly transparent resistive random access memory with a configuration of multilayer graphene (MLG)/ Dy2O3 /indium tin oxide (ITO) structure is demonstrated in this paper. The fabricated device is transparent, with 80% transmittance at 550 nm. The MLG/ Dy2O3 /ITO device shows unipolar resistance switching with a low operation current (<100~\muA) , low operation voltage (<1~V) , low power consumption (<100~\muW) , high resistance ratio (>10^4) , fast switching speed (<60~ns) , reliable data retention, and promising cycle endurance properties (>200~cycles) , which makes a step toward the realization of low-power transparent electronics for next-generation nonvolatile memory application. The MLG/ Dy2O3 /ITO device exhibited typical filamentary-conduction-type resistive random access memory behavior and no forming process is required. High resistance state (HRS) increases with a reduced device area while low resistance state (LRS) is insensitive to the device sizes. Moreover, Raman spectra obtained in pristine state, HRS, and LRS indicate that the lower power consumption of MLG/ Dy2O3 /ITO device is attributable to the formation of oxygen graphene layers. [ABSTRACT FROM AUTHOR]

Metal/NiO/Pt films with various electrodes were fabricated to investigate the effects of standard free energy (SFE) on NiO resistive switching devices. By selecting Ti, Ta, Ag, Cu, and Co as the top electrodes (TEs), we found that the switching voltage was inversely proportional to the SFE. The reason for this is attributed to the different thicknesses of the oxidized interface between TE and NiO. Since the thickness of the oxidized interface depends on the SFE, this paper provides an effective way to control and adjust the switching voltage. [ABSTRACT FROM PUBLISHER]

This paper investigates and models the dc behavior of thin-film-based switching devices. The devices are based on sputtered vanadium dioxide thin films that transition from 200 k\Omega/\square at room temperature to 390 \Omega/\square at temperatures above 68^\circC, with the transition occurring over a narrow temperature range. The device resistance is characterized over temperature and under current- and voltage-sourced electrical bias. The finite-element model predicts the device's nonuniform switching behavior. Electrothermally heated devices show the same transition ratio and switching behavior as externally heated devices suggesting a purely electrothermal switching mechanism. [ABSTRACT FROM PUBLISHER]

This paper demonstrates the efficacy of phase-change (PC) vias in reconfiguring RF front-end circuits for multiband/multi-standard operation. Constructed using two series-connected (SC) GeTe vias, a PC switch can be reversibly transformed between a high R{OFF} state and a low R{ON} state within 1 \mus. Using such PC switches to switch the inductor in a resonator, two LC voltage-controlled oscillators (VCOs) based on: 1) a SC and 2) a coupling-controlled (CC) resonator are developed. Designed and fabricated in 0.13-\mum CMOS in conjunction with an in-house GeTe process, the VCOs can switch their operating frequency over widely separated bands. Wide tuning ranges of 2.89–4.23/(4.93–7.79) and 4.80–8.53/(5.28–10.20) GHz were achieved in the off/on state for the SC/(CC) VCOs. The measured phase noise over the entire tuning range was lower than -103.4 and -102.7~dBc/Hz, at a 1-MHz offset frequency, respectively. [ABSTRACT FROM AUTHOR]

In conventional integrated circuit technologies, a grounded metal guard ring (MGR) is widely used to mitigate the coupling effect between any pair of inductors. Full-wave electromagnetic (EM) simulation results indicate that the guard ring size can significantly affect the inductance value of a single-turn planar inductor. This paper proposes a switchable artificial grounded MGR technique that can not only serve as a guard ring but also change the inductance. Accordingly, an inductor, featuring switchable inductance and high quality factor, is developed for a 60-GHz millimeter-wave wide-frequency tuning range (wide-FTR) and low phase-noise voltage-controlled oscillator (VCO) in 90-nm bulk CMOS technology. The VCO testkey achieves a total tuning range of 9.43 GHz (17%). The measured phase noise levels are -92.2 and -119 dBc/Hz at 1- and 10-MHz offsets, respectively. The experimental results demonstrate that the proposed inductor topology offers the VCO an increase of 36% in the FTR and a competitive performance in phase noise, as contrasted with a conventional varactor-tuned VCO. This VCO achieves a record of -188 dBc/Hz for the \FOMT. [ABSTRACT FROM PUBLISHER]

Soft-switching techniques are very attractive and often mandatory requirements in medium-voltage and medium-frequency applications such as solid-state transformers. The effectiveness of these soft-switching techniques is tightly related to the dynamic behavior of the internal stored charge in the utilized semiconductor devices. For this reason, this paper analyzes the behavior of the internal charge dynamics in high-voltage (HV) semiconductors, giving a clear base to perform overall converter optimizations and to understand the previously proposed zero-current-switching techniques for insulated-gate bipolar-transistor (IGBT)-based resonant dual active bridges. From these previous approaches, the two main concepts that allow switching loss reduction in HV semiconductors are identified: 1) shaping of the conducted current in order to achieve a high recombination time in the previously conducting semiconductors; and 2) achieving zero-voltage-switching (ZVS) in the turning-on device. The means to implement these techniques in a triangular-current-mode dual-active-bridge converter, together with the benefits of the proposed approaches, are analyzed and experimentally verified with a 1.7-kV IGBT-based neutral-point-clamped (NPC) bridge. Additionally, the impact of the modified currents in the converter's performance is quantified in order to determine the benefits of the introduced concepts in the overall converter. [ABSTRACT FROM PUBLISHER]

Ion implantation technique can be applied for planar isolation of AlGaN/GaN heterojunction field-effect transistors (HFETs), which enables high-density integration of the power switching transistors. So far, the reported isolation using ion implantation for GaN devices has never maintained high isolation voltages after high-temperature processing over 800 ^\circ\C which is commonly used for the fabrication. In this paper, we present detailed analysis and mechanism of thermally stable isolation of GaN devices by Fe ion implantation keeping high breakdown voltage between the devices after high-temperature annealing. Ion species forming deep levels at atomic sites in GaN are examined by using first-principle calculation prior to the experiments. The calculation indicates that the Fe ions stay at Ga sites with deep levels in GaN. The following experiments using various ion species well agree with the aforementioned predictions, where implanted regions by other ions than Fe exhibit reduction of the resistivity after high-temperature annealing to recover the processing damage by the ion implantation. As a result, it is experimentally found that Fe is the only choice to serve high resistivity after the annealing. The Fe ion implantation enables high breakdown voltage of 900 V after the annealing at 1200 ^\circ\C. This technique is indispensable to enable monolithic integration of the lateral AlGaN/GaN HFETs for high-voltage power switching systems. [ABSTRACT FROM PUBLISHER]

This paper gives an overview about different failure mechanisms which limit the safe operating area of power devices. It is demonstrated how the device internal processes can be investigated by means of device simulation. For instance, the electrothermal simulation of high-voltage diode turn-off reveals how a backside filament transforms into a continuous filament connecting the anode and cathode and how this can be accompanied with a transition from avalanche-induced into thermally driven carrier generation. A similar current destabilization may occur during insulated-gate bipolar transistor turn-off with a high turn-off rate, when the channel is closed quickly leading to strong dynamic avalanche. It is explained how the current filamentation depends on substrate resistivity, device thickness, channel width, and switching conditions (gate resistor and overcurrent). Filamentation processes during short-circuit events are discussed, and possible countermeasures are suggested. A mechanism of a periodically emerging and vanishing filament near the edge of the chip is presented. Examples on current destabilizing effects in gate turn-off thyristors, integrated gate-commutated thyristors, and metal–oxide–semiconductor field-effect transistors are given, and limitations of current device simulation are discussed. [ABSTRACT FROM PUBLISHER]

With the availability of advanced computing capability, it is fashionable to analyze and design insulated-gate bipolar transistors (IGBTs) using sophisticated 2-D and 3-D numerical simulation tools. However, analytical modeling of IGBTs allows a deeper understanding of the physics of operation, which can foster innovation. This paper reviews 1-D analytical models developed for the IGBT on-state characteristics, switching behavior, and safe operating area for symmetric (nonpunchthrough) and asymmetric (punchthrough) devices. [ABSTRACT FROM PUBLISHER]

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design. [ABSTRACT FROM AUTHOR]