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Abstract Multi-element nitride films of AlCrNbSiTiV high-entropy alloy (HEAs) are deposited on a cermet cutter (T1200A) and glass substrates using reactive direct current magnetron sputtering (DCMS) and high power impulse magnetron sputtering (HIPIMS) with a single equimolar AlCrNbSiTiV HEA target. This study determines the effect of the ratio of the nitrogen flow (varying from 0 to 40%) on the chemical composition, microstructure, mechanical properties and cutting tool performance of the (AlCrNbSiTiV)N film. The films are found to have increased hardness and elastic recovery when the nitrogen flow ratio is increased. The (AlCrNbSiTiV)N film adheres well to the substrate and the Rockwell indentation results are HF1. (AlCrNbSiTiV)N films that are grown using DCMS and HIPIMS feature only a simple face-center-cubic structure. The samples that are deposited using HIPIMS exhibit a higher film density, a smoother surface and excellent hardness and elastic recovery, compared to coatings that are deposited using DCMS. The (AlCrNbSiTiV)N films are coated onto cutters for the dry turning of a SCM440 steel work-piece. The machining surface of a coated tool that is deposited using a HIPIMS system exhibits fewer surface defects and the tool flank wear is decreased. Highlights • TEM pattern of (AlCrNbSiTiV)N film shows a simple NaCl-type FCC phase. • Nitride films shows good adhesion strength to the substrate be classified as HF1. • The distribution of elements is homogeneous through the depth of the nitride film. • The films deposited with the HIPIMS are smoother, better crystallized and good mechanical property. [ABSTRACT FROM AUTHOR]

Scaling of dimensions for traditional Si-based metal oxide semiconductor field-effect transistors (MOSFETs) is limited. Thus, a promising transistor material and a corresponding fabricated process should be selected to improve the electrical performance of advanced nanodevices. According to the viewpoint of material survey, germanium-based MOSFET, which exhibits intrinsic high mobility, is considered a promising candidate for next-generation transistors. With the suitable introduction of stress-induced thin coating, such as silicon nitride contact etch stop layer (CESL), the electron mobility of devices can be further enhanced to compensate for the significant degeneration of lattice-mismatched stress resulting from rigorous dimensional shrinkage. The tensile CESL is commonly adopted to induce a biaxial tensile stress on the wide scope of n-type MOSFETs. However, the induced tensile stress that occurs along the transverse direction of a concerned device channel decreases the carrier mobility. Hence, this study proposes special layout designs with dummy gates placed on the transverse direction of the device channel. The effect of stress magnification from CESL coating on Ge-based n-type MOSFET is presented via a finite element analysis and a high-order piezoresistance model. Result shows that an enhanced carrier mobility gain of approximately 16.47% is obtained when a 50 nm-thick CESL with a tensile of 2.0 GPa is considered. [ABSTRACT FROM AUTHOR]

The considerably high carrier mobility of Ge makes Ge-based channels a promising candidate for enhancing the performance of next-generation devices. The n-type metal–oxide semiconductor field-effect transistor (nMOSFET) is fabricated by introducing the epitaxial growth of high-quality Ge-rich Ge 1 − x Si x alloys in source/drain (S/D) regions. However, the short channel effect is rarely considered in the performance analysis of Ge-based devices. In this study, the gate-width dependence of a 20 nm Ge-based nMOSFET on electron mobility is investigated. This investigation uses simulated fabrication procedures combined with the relationship of the interaction between stress components and piezoresistive coefficients at high-order terms. Ge 1 − x Si x alloys, namely, Ge 0.96 Si 0.04 , Ge 0.93 Si 0.07 , and Ge 0.86 Si 0.14 , are individually tested and embedded into the S/D region of the proposed device layout and are used in the model of stress estimation. Moreover, a 1.0 GPa tensile contact etching stop layer (CESL) is induced to explore the effect of bi-axial stress on device geometry and subsequent mobility variation. Gate widths ranging from 30 nm to 4 μm are examined. Results show a significant change in stress when the width is < 300 nm. This phenomenon becomes notable when the Si in the Ge 1 − x Si x alloy is increased. The stress contours of the Ge channel confirm the high stress components induced by the Ge 0.86 Si 0.14 stressor within the device channel. Furthermore, the stresses (S yy ) of the channel in the transverse direction become tensile when CESL is introduced. Furthermore, when pure S/D Ge 1 − x Si x alloys are used, a maximum mobility gain of 28.6% occurs with an ~ 70 nm gate width. A 58.4% increase in mobility gain is obtained when a 1.0 GPa CESL is loaded. However, results indicate that gate width is extended to 200 nm at this point. [ABSTRACT FROM AUTHOR]

This study employed the four-point bending test (4-PBT) to measure the interfacial strength of pressure-sensitive adhesive (PSA)/SiN passivation stacked thin films. Finite element analysis (FEA) is combined with the J integral approach and the modified virtual crack closure technique to validate the results of 4-PBT. The FEA simulation results verify the measurement results. The stress status and energy release rate of the delaminated tip are also determined at different elevations of stacked thin films of 4-PBT specimens adjacent to the PSA/SiN interface. The crack in the PSA parallel to the foregoing interface with a slight span occurs on the fractured interface. This behavior is confirmed by observing the scanning electron micrographs of the specimens after 4-PBT. [ABSTRACT FROM AUTHOR]

The CrAlSiN coatings with Si contents from 0 at.% to 13.0 at.% were deposited on AISI 304 stainless steels and tungsten carbide by RF magnetron sputtering. In the ball-on-disc wear tests, the improved friction coefficient of (Cr 0.5 Al 0.5 ) 1 − x Si x N coatings with increasing Si content was revealed. The hardness (H) and the reduced elastic modulus ( E ⁎ ) of (Cr 0.5 Al 0.5 ) 1 − x Si x N coatings were acquired by a nanoindentation. The H 3 / E ⁎2 ratio of (Cr 0.5 Al 0.5 ) 1 − x Si x N coatings was found be proportional to the abrasion resistance of coatings, and therefore the (Cr 0.5 Al 0.5 ) 1 − x Si x N coating with maximum H 3 / E ⁎2 ratio as high as 0.475 by adding 9.0 at.% Si exhibited superior resistance to plastic deformation and wear. In addition, it was revealed that the columnar grains of the CrAlN coatings were switched to refined and equi-axial ones after Si addition. From the observation of crack propagation, it was evidenced that the equi-axial grains with sophisticated boundary of (Cr 0.5 Al 0.5 ) 1 − x Si x N coating prevents the direct penetration of the cracks. On the basis of these improved tribological behaviors, the superior durability of (Cr 0.5 Al 0.5 ) 1 − x Si x N coating is thus demonstrated. [ABSTRACT FROM AUTHOR]

The mobility enhancement of metal-oxide-semiconductor field-effect transistors (MOSFETs) using narrow gate lengths and channel widths is sensitive to the stress effects of silicon channels related to advanced strain engineering. The layout pattern of MOSFETs significantly influences the device performance, particularly the protruding gate width on shallow trench isolation structures. This paper investigates the geometric construction of an n-channel MOSFET composed of silicon–carbon stressors embedded in source/drain regions. The stressors have a 1.65% carbon mole fraction and a 1.1 GPa tensile contact etch stop layer. Finite element analysis and analysis of variance were used to determine the bending effect of protruding gate widths on the MOSFETs. Results show that the main variation parameters are channel lengths and protruding gate widths, which determine the improvement in device performance. These results can serve as guidelines of stress impacts for predicting the next-generation node technologies of layout patterns. [ABSTRACT FROM AUTHOR]

Abstract: This study demonstrated that advanced strained engineering in contact etching stop layer (CESL) combined with silicon germanium (Si1−xGex) stressors can be efficiently utilized to enhance the performance of devices. Lattice mismatch stress was induced to establish an Si1−xGex channel integrated with intrinsic stress of CESL, which consists of multiple stressors, to analyze the stress contour of the concerned channel in n-type metal–oxide–semiconductor field effect transistors (nMOSFETs) by three-dimensional (3D) finite element analysis (FEA). The types of intrinsic CESL stress considered in this study were tensile (1.1GPa) (t-CESL) and compressive (−2.0GPa) (c-CESL). Germanium mole fractions, including 0%, 22.5%, and 25%, utilized in the Si1−xGex channel were selected to carefully analyze their impact on the Si1−xGex channel. The effect of channel geometries, which are composed of aspect ratio of length and width, was considered as well. Results reveal that the stress components of the Si1−xGex channel increases significantly when the amount of Si1−xGex layer increases. A change in the length and width of the channel induces inversion in the Si1−xGex channel regarding stress conventions in the direction of the channel's length and width. Results predicted by the proposed FEA were consistent with experimental data as validated by the nMOSFET with an Si0.775Ge0.225 channel. Comparison of the simulation results of FEA with two-dimensional (2D) and 3D models was performed. The results show that wide gate width in the 3D model can induce a response to the calculated results similar to that obtained in a 2D situation. [Copyright &y& Elsevier]

Abstract: The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22nm and lower. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10% to 20% enhancement in carrier mobility. [Copyright &y& Elsevier]

Abstract: The layout patterns of nano-scale devices have significant impacts on device performance when an increase in operating velocity is considered. Thus, advanced strain engineering of metal-oxide-semiconductor field-effect transistors (MOSFETs) is necessary when highly scaled gate lengths are employed. The foregoing mechanical effects are observable when a device with a narrow channel width is utilized. However, when a device integrated with an extended poly gate is scaled down to several hundreds of nanometers, the induced stress contours of the channel region and corresponding mobility gain become troublesome and must be resolved. This study investigates the mechanical impacts of extended gate widths on the mobility gains of p-type MOSFETs. The selected MOSFET has a SiGe stressor embedded in its source and drain regions, as well as a compressive contact etch stop layer. Three-dimensional finite element simulation is performed to emulate the stress contour within the Si channel and estimate the related mobility gain. Sensitivity analyses of the simulation results using factorial designs and response surface methodology indicate that stresses within the Si channel are induced by a bending force determined by the extension of the poly width. A significant enhancement in mobility gain is found when an extended poly width combined with proper arrangements of the device geometry is applied. [Copyright &y& Elsevier]

Abstract: The integration of thin film technology into the fabrication of semiconductor transistors has given rise to significant challenges in the design of multi-level back-end-of-line interconnects. The interfacial adhesion between Al metal and TiN barrier is one of the major factors that affect interconnect reliability. Analyzing the effect of the interconnect structures of Al/TiN barriers on interfacial cracking energy under flexural loading is an interesting research direction. This work proposes a robust estimation of interfacial cracks by simulation-based methods to satisfy the mechanical design requirements for multi-level interconnect systems. A constant bending moment can be generated with the framework of the four-point bending test (4-PBT). A 4-PBT simulation model can be used in finite element analysis, combined with the J-integral method and the modified virtual crack closure technique, to accurately predict the interfacial fracture energy of Al/TiN films. Preliminary results indicate a considerable increase in energy release rate. Energy is released as a crack along the interface of the Al/TiN films passes through the region above the parallel metal lines of patterned interconnects, especially for a Cu/SiLK material system. The results also show that dielectrics can serve as stress buffer layers that inhibit crack growth. [Copyright &y& Elsevier]

Abstract: Organic electronic devices with multi-stacked thin films based on polymeric substrates are proposed for use in mainstream flexible organic light-emitting diode displays. To achieve the above-mentioned requirements, indium tin oxide (ITO) thin film, a brittle, inorganic material, is necessary to be utilized as a transparent electrode in flexible electronics. The failure rate of ITO films is of concern when introducing harsh flexural load in terms of reliability. This study utilizes a simulation-based factorial-design approach to determine a suitable combination of mechanical characteristics of ITO film stacked with other films to reduce the neutral plane (NP) impact of stacked films. The results indicate that both Young's modulus and cover plate thickness are major factors that alter the stress magnitude of ITO films. Moreover, the simulated results for stacked structures reveal that the distance between the ITO film and NP is significantly reduced when polyimide materials, rather than steel metal, are used for the cover plate. In the meanwhile, ITO film stress drops in virtue of lower mechanical stiffness and lesser thickness direction between the NP and ITO films in a multi-stacked film structure. [Copyright &y& Elsevier]

Abstract: The minimum etched pits of 300nm diameter and the trenches of 300nm width with a 50nm depth for both geometries are prepared in the GeSbSn oxide photoresist on the silicon substrates. The lithographic patterns are recorded by direct laser writing, using a 405nm laser diode and 0.9 numerical aperture media disc mastering system. The developed pit diameters in an inorganic oxide photoresist are smaller than the exposed laser beam spot diameter due to thermal lithography. The crystal structures of the as-sputtered and the annealed powder samples scraped from the sputtered films are examined by X-ray diffractometer. The effect of the heating rate on the crystallization temperatures is evaluated by a differential scanning calorimeter and the crystallization activation energy is determined from Kissinger's plot. The optical and absorption characteristics of the oxides are strongly dependent on the oxygen flow rate during the reactive magnetron sputtering process. The transmittance of the deposited films increases and the absorption decreases with increasing oxygen flow rate, which implies that at high oxygen flow rate, the film resembles dielectric material. The oxygen flow rate during the deposition process is defined within a limited range to obtain the proper extinction coefficient. The working extinction coefficients of the films ranging from 0.5 to 0.8 are applied in this study to achieve the sharp and vertical edge of the etched pits and trenches of 50nm depth. [Copyright &y& Elsevier]

The stress evolution of n-type metal-oxide-semiconductor field-effect transistors with silicon–carbon stressor is systematically examined using three-dimensional finite element analysis. The effect of gate width dependence with a layout arrangement of dummy active of diffusion (OD) on device performance is also discussed. Results indicate that as a 1.0 μm gate width is adopted, a drain current enhancement of 26.19% could be achieved through an increase in tensile and compressive stress along the transport and vertical directions, respectively. However, the enhancement in device performance deteriorates from 22.02% to 15.98% as the gate width decreases from 1.0 μm to 0.1 μm. This phenomenon is attributed to the dependence of stress domination along the channel direction on the width dimensions of device gate. This study also finds that when a long dummy OD is used, the effect of length on performance improvement is enhanced for a device with a small OD. [ABSTRACT FROM AUTHOR]

Abstract: Chemical and electrical characteristics of Ti-based nanocrystals containing germanium, fabricated by annealing the co-sputtered thin film with titanium silicide and germanium targets, were demonstrated for low temperature applications of nonvolatile memory. Formation and composition characteristics of nanocrystals (NCs) at various annealing temperatures were examined by transmission electron microscopy and X-ray photon-emission spectroscopy, respectively. It was observed that the addition of germanium (Ge) significantly reduces the proposed thermal budget necessary for Ti-based NC formation due to the rise of morphological instability and agglomeration properties during annealing. NC structures formed after annealing at 500°C, and separated well at 600°C annealing. However, it was also observed that significant thermal desorption of Ge atoms occurs at 600°C due to the sublimation of formatted GeO phase and results in a serious decrease of memory window. Therefore, an approach to effectively restrain Ge thermal desorption is proposed by encapsulating the Ti-based trapping layer with a thick silicon oxide layer before 600°C annealing. The electrical characteristics of data retention in the sample with the 600°C annealing exhibited better performance than the 500°C-annealed sample, a result associated with the better separation and better crystallization of the NC structures. [Copyright &y& Elsevier]

Abstract: Formation and composition analyses of titanium oxinitride nanocrystals (NCs) fabricated via treating a magnetron co-sputtered thin film of titanium and silicon dioxide with a rapid thermal annealing in nitrogen ambient were demonstrated for nonvolatile memory applications. Phase separation characteristics with different annealing conditions were examined by transmission electron microscopy and chemical bonding characteristics were confirmed by X-ray photon emission spectra. It was observed that a blanket layer composed mainly of titanium oxide was still present as annealing temperature was increased to 700°C, associated with the thermodynamically stable phase of titanium oxide. Furthermore, a higher thermal treatment of 900°C induced formation of a well-separated NC structure and caused simultaneously partial nitridation of the titanium oxide, thereby forming titanium oxinitride NCs. A significant capacitance–voltage hysteresis in threshold voltage shift at 1V was easily achieved under a small sweeping voltage range of +2V/−2V, and a memory window retention of 2.2V was obtained after 107 s by extrapolation under a 1s initial-program/erase condition of +5V/−5V, respectively. [Copyright &y& Elsevier]

Abstract: This research presents a simulation-based methodology to accurately predict interfacial adhesion behaviors of heterostructures. Validation of the proposed approach is achieved through comparison of 4-point bending test results on interfaces of multiple stacked low-k films with those of theoretical solutions from the finite element analysis. Impact induced by the compliance of 4-point bending test system can be neglected using the averaged energy release rate of various crack lengths in simulations. On the basis of precise predictions drawn from the considered analyses, uncertainty of experimental tests for the nano-scale fractured strength could be promptly observed and estimated. [Copyright &y& Elsevier]

Based on wavelet transforms extracting characteristic features from experimental data, the wavelet neural network (WNN) is used as an elementary model to study the characteristics of field emission from thin films. The WNN model is trained with learning samples of thin film thickness. The function mappings that the trained WNN model contains are the very ones that thin film thickness varies with characteristic parameters of field emission. A predicting model on thin film thickness of field emission is obtained. The data of thickness of diamond thin films is used to test this model. The results show that the absolute value of the relative error is within 2.98%, and the well-trained WNN model possesses good forecasting characteristics. [Copyright &y& Elsevier]

• Stress mechanism investigated for the dielectric films of SiO 2 , TiO 2 , Ta 2 O 5 and Nb 2 O 5. • Dielectric films deposited on PET and PC substrate for anisotropic stress investigation. • The anisotropic stress of dielectric films was analyzed with Mohr circle method. • Finite element method numerical simulated intrinsic stress for the dielectric films. • High-order polynomial fitting curvature could reduce the stress error within 2.47 %. In this study, an investigation was made into the optical and stress properties of four dielectric films: silicon dioxide (SiO 2), titanium dioxide (TiO 2), tantalum pentoxide (Ta 2 O 5) and niobium pentoxide (Nb 2 O 5). This was because they are commonly used in the optoelectronic and semiconductor devices. The classification of these stress properties includes tensor & compressive, thermal & intrinsic, and principal & shearing. The stress mechanism of these dielectric films deposited on polyethylene terephthalate (PET) and polycarbonate (PC) flexible substrates with ion-beam assisted deposition (IBAD) was investigated by the finite element method (FEM). Meanwhile, the equivalent room temperature (ERT) of FEM was used for the analysis of the intrinsic stresses, and then the methods of home-made phase-shifting shadow moiré interferometer and Mohr circle were employed to analyze the anisotropic principal and shearing stresses. The results demonstrated that the residual stress of these dielectric films could get broken on the PC flexible substrate. However, only all of the SiO 2 /PC films were measured. Also, the residual stress on PET flexible substrate could change from the tensile stress to the compressive one when the thickness of the film increased. However, only all of the Ta 2 O 5 /PET films got compressed when the film thickness increased. Therefore, the anisotropic stress of the four dielectric films on the PET substrate suggests that both the maximum principal and shearing stresses should be Ta 2 O 5 >TiO 2 ≥Nb 2 O 5 >SiO 2. They are proportion to Q (elastic-energy/mole). The FEM method combined with the high-order polynomial fitting curvature could obtain the intrinsic stress and yield the error within 2.47 %. [ABSTRACT FROM AUTHOR]

• Plasma-assisted surface modification is performing to enhance the adhesion. • Surface modification is contributing to generate N–O bonds among interface. • The opening mode is the major fracture mode during mechanical-released procedure. • The adhesion of designed interface is boosted from 2.51 J/m2 to 5.23 J/m2. Interfacial adhesive strength is an important characteristic considered in multilayered active-matrix organic light-emitting diode (AMOLED) architecture as it has an impact on the mechanical reliability issue generated from complicated organic/inorganic hybrid lamination and final debonding procedure. Thus, an appropriate released layer design is needed to manage the capability and reliability of the encapsulated AMOLED structure de-bonded from the temporary carrier. Accordingly, this research utilizes the plasma-assisted surface modification to improve the interfacial adhesive strength of the polyimide (PI)/debonding layer (DBL) during mechanical debonding. In addition, a fracture-based finite element model of peeling testing architecture is constructed to analyze the adhesive behavior of the PI/DBL interface via the utilization of the modified virtual crack closure technique. The analytic results indicate that the suitable plasma-assisted surface modification significantly increased the nitrogen concentration and generated the high dissociation energy N–O bonds among the bonded interface between the PI/DBL thin films. The opening mode-fractured energy also takes the dominance proportion in the entire peeling load-induced interfacial energy release rate. The application of plasma-assisted surface modification enhanced the delamination resistance of the concerned interface and maintained the structural stability during the lamination and related release of a whole flexible AMOLED architecture. [ABSTRACT FROM AUTHOR]

Given the reduction in size of hole-containing metal-oxide-semiconductor field-effect transistors (pMOSFETs) to break Moore's law, extensive researches have been conducted to improve the performance of nano-scaled devices with the use of strained engineering. The layout patterns of devices combined with the introductions of manufacturing processes would cause recessed surfaces of shallow trench isolation (STI) and change the stress-induced mobility of the whole transistors. To address this issue, a process-oriented stress simulation with a 20 nm nano-scaled short channel device and a 100 nm gate width is presented to extract channel stress components and calculate mobility gain, subsequently. Moreover, the layout effect of dummy active of diffusion is also considered. The proposed pMOSFET is composed of STI, a source/drain lattice mismatched silicon-germanium alloy, and a compressed contact etch stop liner (CESL) stressor. The recessed height of STI is reduced from 0 nm to 15 nm in the planarization process. The results show the recessed height effects of STI on the stresses and mobility variation of device channel is not obvious. By contrast, CESL with intrinsic stress plays an important role to modulate device mobility. [ABSTRACT FROM AUTHOR]

Plasma sprayed LSGM (La 0.8 Sr 0.2 Ga 0.8 Mg 0.2 O 3 − δ ) based metal-supported solid oxide fuel cells with nanostructured LDC (Ce 0.55 La 0.45 O 2 − δ )–Ni anode and LSCM (La 0.75 Sr 0.25 Cr 0.5 Mn 0.5 O 3 − δ ) diffusion barrier layer are developed in our institute. The non-sealed single cell measurement configuration is applied to test the performance and the durability of a prepared 10 × 10 cm 2 cell. The tested cell can deliver the power densities of 543, 480, 352 and 214 mW cm − 2 at 0.6 V for the test temperatures of 800, 750, 700 and 650 °C respectively. Results obtained from long term durability test show that this cell with a porous Ni–Fe metal substrate, a porous LSCM diffusion barrier layer, a porous nano-structured LDC–Ni anode layer, a thin dense LDC isolation layer, a dense crack free LSGM electrolyte layer, a porous LSGM–LSCF (La 0.6 Sr 0.4 Co 0.2 Fe 0.8 O 3 − δ ) cathode interlayer and a porous LSCF cathode current collecting layer has a degradation rate of ~ 2.2% kh − 1 during the test period of 3700 h at conditions of 700 °C and 400 mA cm − 2 current density. The tested 18-cell stack in a sealed configuration shows that it can deliver a power of 606 W at 42.4% fuel utilization, 0.75 V and 800 °C. Each cell in the stack has an open circuit voltage larger than 1 V. [ABSTRACT FROM AUTHOR]

Abstract: Stress distributions in the In0.53Ga0.47As channel regions of the In0.4Ga0.6As source/drain (S/D) with various lengths and widths were studied with 3D ANSYS simulations. The resulting mobility improvement was analyzed. Tensile stress along the transport direction was found to dominate mobility improvement. Stress along the vertical direction perpendicular to the gate oxide was found to affect mobility the least. However, for strained InGaAs NMOSFETs with width between 0.5 and 3μm, the compressive stress along the width direction makes considerable contribution to mobility improvement and cannot be neglected. The impact of width on performance improvements such as the mobility gain was analyzed with TCAD simulations. [ABSTRACT FROM AUTHOR]

Abstract: In this study, reproducible resistance switching effects were demonstrated on a relatively thin FeO x layer in the TiN/SiO2/FeO x /FePt structure produced by oxidizing the surface of a FePt electrode during a plasma-enhanced tetraethyl orthosilicate oxide deposition process. Characteristics of the non-stoichiometric FeO x transition layer were examined by Auger electron spectroscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy analyses. In addition, characteristics of the forming process as well as the current transport characteristics after forming process in the TiN/SiO2/FeO x /FePt structure were discussed. Moreover, the role of the silicon oxide layer was also experimentally demonstrated to act as an additional supplier of oxygen ions for the switching requirement by biasing high voltage bias conditions. [ABSTRACT FROM AUTHOR]

Abstract: Stress modeling and cross-section failure analysis by focused-ion-beam have been used to investigate stress-induced voiding phenomena in Cu interconnects. The voiding mechanism and the effect of the interconnect structure on the stress migration have been studied. The results show that the most concentrated tensile stress appears and voids form at corners of vias on top surfaces of Cu M1 lines. A simple model of stress induced voiding in which vacancies arise due to the increase of the chemical potential under tensile stress and diffuse under the force of stress gradient along the main diffusing path indicates that stress gradient rather than stress itself determines the voiding rate. Cu interconnects with larger vias show less resistance to stress-induced voiding due to larger stress gradient at corners of vias. [Copyright &y& Elsevier]

Abstract: Stress distributions in the Si channel regions of silicon–carbon source/drain and stressed silicon nitride liner NMOSFETs were studied using the 3D ANSYS simulations. The mobility enhancement was found to be dominated by the tensile stress along the transport direction and compressive stress along the growth direction in wide devices. Stress along the width direction was found to have the least effect on the drain current in wide samples. Stress along the width slightly degraded the mobility gain in the narrow width regime. The compressive stress along the vertical direction, perpendicular to the gate oxide, contributes significantly to mobility enhancement and cannot be neglected in nanoscale NMOSFETs. The impact of width on performance improvements such as mobility gain was also analyzed using TCAD simulations. [Copyright &y& Elsevier]

Abstract: Textured surface un-doped zinc oxide (ZnO) and boron-doped ZnO (ZnO:B) thin films with pyramid-like grains were directly deposited by metal organic chemical vapor deposition (MOCVD) technique and hydrogenated gallium-doped ZnO (HGZO) thin films with good electrical properties were grown by pulsed direct-current magnetron sputtering. In order to obtain high quality transparent conductive oxides (TCOs) for Si-based thin film solar cells, through combining the advantages of MOCVD–ZnO and sputter-HGZO thin films, bi-layer textured surface glass/ZnO:B/HGZO and glass/HGZO/ZnO:B TCO thin films with milky surface were fabricated and investigated in detail. The main research purposes are to explore appropriate surface morphology and improve the electrical properties of TCO layers. Compared with textured surface un-doped ZnO and ZnO:B thin films, both the bi-layer ZnO/HGZO and ZnO:B/HGZO thin films exhibit high electron mobility. The ZnO:B/HGZO thin films present modified pyramid-like surface morphology with high transparencies (T >85%) and excellent electrical properties (resistivity of ~9.28×10−4 Ωcm and mobility of ~28.8cm2/Vs). Meanwhile, the HGZO/ZnO thin films exhibit large grain size (~500nm–1000nm) with preferred growth orientations along (100) and (002) crystallographic directions. Bi-layer HGZO/ZnO and HGZO/ZnO:B thin films exhibit relatively higher diffuse transmittance than that of corresponding ZnO and ZnO:B thin films. [Copyright &y& Elsevier]

Abstract: In this work, electrical characteristics of the Ge-incorporated Nickel silicide (NiSiGe) nanocrystals memory device formed by the rapidly thermal annealing in N2 and O2 ambient have been studied. The trapping layer was deposited by co-sputtering the NiSi2 and Ge, simultaneously. Transmission electron microscope results indicate that the NiSiGe nanocrystals were formed obviously in both the samples. The memory devices show obvious charge-storage ability under capacitance–voltage measurement. However, it is found that the NiSiGe nanocrystals device formed by annealing in N2 ambient has smaller memory window and better retention characteristics than in O2 ambient. Then, related material analyses were used to confirm that the oxidized Ge elements affect the charge-storage sites and the electrical performance of the NCs memory. [Copyright &y& Elsevier]

Abstract: This study investigates the temperature-dependent memory characteristics of polycrystalline silicon thin-film transistors with oxide/nitride/oxide stack gate dielectrics and N+ poly-Si gate structures for nonvolatile memory application. As the device was programmed by Fowler–Nordheim tunneling at high temperature, some electrons captured in shallow traps could obtain enough thermal energy to de-trap to the gate, resulting in low programming efficiency. As the programming time increases, the hole injection through the blocking oxide from the gate would further lead the threshold voltage to decrease. In addition, the retention characteristic of the device programmed at higher temperature exhibits better charge storage ability. Because the electrons trapped in the shallow traps of the nitride layer can be easily de-trapped when temperature rises, the memory characteristics are mainly dominated by charges stored in the deep traps. [Copyright &y& Elsevier]

Abstract: The novel process of self-aligned fluorine doped oxide (SiOF) spacers on low temperature poly-Si (LTPS) lightly doped drain (LDD) thin film transistors (TFTs) is proposed. A fluorine doped oxide spacers were provided to generate the lower dissociation Si–F bonds adjusted to the interface of the drain which is the largest lateral electric field region for lightly doped drain structure. The stronger Si–F bonds can reduce the bonds broken by impact ionization. It is found that the output characteristics of SiOF spacers TFTs show the superior immunity to kink effect. The degradations in Vth shifting, subthreshold slope, drain current and transconductance of SiOF spacers after DC stress are improved. [Copyright &y& Elsevier]

• Growth of GaAs/Si templates. • Reduced dislocation density by spaced annealing. • Performance of light-emitting diodes grown on templates. This paper describes the growth of a GaAs-based light-emitting diode (LED) on a GaAs/Si virtual substrate by metalorganic chemical vapor deposition. A GaAs/Si virtual substrate (or template) was formed by depositing a 3.5-μm-thick GaAs epilayer on a (100) Si substrate with the employment of multiple spaced thermal-cycle annealing (TCA). The number of annealing cycle was zero to five in this study to examine crystallinity variation of a GaAs/Si template. High-resolution X-ray rocking curve analysis showed that (400) GaAs crystallinity in terms of full width at half maximum (FWHM) improved significantly with the number of the spaced TCA and then reached a minimum at four annealing cycles. There seems to be no significant difference in crystallinity between the GaAs/Si templates with four and five spaced annealing cycles. The GaAs/Si template with four spaced annealing cycles demonstrated not only an excellent (400) FWHM value of 94.6 arcsec but also a reduced dislocation density of 2.4 × 107 cm−2 evaluated from plan-view transmission electron microscopic observation. Electroluminescence spectra of GaAs-based LEDs grown on GaAs/Si templates showed that emission peak intensity increased monotonically with the number of the spaced annealing cycles. Furthermore, the emission peak intensity of a LED grown on the GaAs/Si template with five spaced annealing cycles reached 80% of a reference LED grown on a GaAs substrate, indicating that the presented multiple spaced TCA method may be useful in obtaining superior crystallinity of a GaAs/Si template for the potential application of monolithic integration of optoelectronic devices with Si. [ABSTRACT FROM AUTHOR]

Abstract: Polycrystalline silicon thin film transistors (poly-Si TFTs) with the ion implantation of fluorine elements were investigated in this study. The electrical performance and reliability were reported comprehensively. Experimental work has shown the electrical characteristics of excimer laser crystallized F-ions-implanted poly-Si TFTs are improved effectively, especially for field effect mobility. It is also found that the fluorine piled up at the poly-Si interface during thermal annealing, for the TFT fabricated without a prior deposition of pad oxide. The stronger Si–F bonds replace the Si–Si/Si–H, leading to the superior electrical reliability. However, the dose of F ions is critical in poly-Si, or the electrical characteristics of TFT devices will be degraded. [Copyright &y& Elsevier]

Abstract: Metal–insulator–metal (MIM) capacitors with high-k HfO2 dielectrics were fabricated and investigated. Experimental results show low leakage current densities of ∼5×10−9 A/cm2 and high capacitance density of ∼3.4 fF/μm2 at 100 kHz in the MIM capacitors. The temperature coefficient and frequency dispersion effect for these MIM capacitors were very small. Different metal electrodes like tantalum, aluminum and copper were also investigated and compared. Finally, the mechanism of electrical transport was extracted for the HfO2 MIM capacitors to be Poole–Frenkel-type conduction mechanism. [Copyright &y& Elsevier]

Abstract: The stress distribution in the Si channel regions of process-strained Si (PSS) MOSFETs with various widths and gate lengths was studied using TCAD process simulations. We show how these geometric effects can impact the achievable transistor performance gains. In this work, high-performance MOS devices have been achieved by stressors such as stressed SiN liner and S/D stressors such as SiGe alloy material and optimal geometric structure design. Strain engineering seems to be promising when considering mobility gain, carrier injection velocity, and ballistic efficiency of nanoscale MOS devices. This work helps the future MOS device design and demonstrates that strain engineering is important for future nanoscale device technology. [Copyright &y& Elsevier]

Abstract: The stress distribution in the silicon (Si) channel regions of silicon–carbon (SiC) source/drain negative-metal-oxide semiconductor field-effect transistors (NMOSFETs) with various widths was studied using three-dimensional (3D) process simulations. The drive current enhancement in wide devices was dominated by the tensile stress along the transport and vertical directions. Stress along the width (transverse) direction has the least effect on the drain current in wide devices. Stress along the width direction in narrow devices was found to degrade the drive current gain and cannot be neglected. In addition, a reduction of device width was found to reduce the drive current gain due to the presence of less compressive stress in the vertical direction in the device channel, caused by the shrinking SiC regions. The impact of width on performance improvements such as drive current mobility gain was analyzed using Technology Computer-Aided Design (TCAD) simulations. [Copyright &y& Elsevier]