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An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) is proposed. The proposed algorithm finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance. Mathematical proof of the algorithm is presented for both rotator-based and VCO-based CDRs with finite loop delay. A 25 Gb/s transceiver IC is fabricated using a 40 nm CMOS process to validate the performance of the algorithm. The power consumptions of TX and RX are 37.8 mW and 46.8 mW, respectively and the synthesized area implementing a digital loop filter together with the proposed ALGC occupies 140 \mum \times 170 \mum. [ABSTRACT FROM AUTHOR]

Wideband (\geq10 MHz) continuous-time (CT) sigma-delta (\Sigma\Delta) modulators generally use active-RC filters. On the other hand, Gm-C-filters avoid the need of a power-hungry driving stage due to their small loading. At the moment, the major challenge for designing Gm-C-based \Sigma\Delta modulator is the narrow linear input range due to the nonlinear Gm amplifier, which leads to low SNDR. This work develops a nonlinearity compensation technique for Gm-C-based \Sigma\Delta modulator. This technique designs a nonlinear feedback DAC which has matched V-I transfer curve as the first Gm amplifier (Gm1). As a result, the distortions of Gm1 are significantly suppressed at the modulator output. This method is prototyped in a 640 MS/s Gm-C-based \Sigma\Delta modulator with 10 MHz signal bandwidth in a 0.18-\mum CMOS process. With this technique, the linear input range of the modulator is greatly enlarged. Consequently, the peak SNDR of the modulator is improved by about 8 dB to 75 dB. This >12-bit ENOB is achieved for the first time for wide-band Gm-C-based \Sigma\Delta modulators. [ABSTRACT FROM AUTHOR]

The conventional switched-capacitor amplifier faces design tradeoffs between settling accuracy and noise, in that high settling accuracy demands wide bandwidth but at the sacrifice of noise performance. In fact settling accuracy and noise exhibit different time dependence, which can be exploited to optimize the overall performance. Settling accuracy is determined by average bandwidth in the whole amplification phase, whereas the output noise of interest is determined by the bandwidth near the end of the phase. The proposed amplifier divides the amplification phase into two sub-phases. The first sub-phase starts with high bandwidth and high slew rate to approach the final value quickly. In the second sub-phase, the bandwidth can be significantly reduced, achieving the target settling accuracy but with much lower noise. This division allows the settling accuracy, noise, slew rate, and DC gain to be designed independently. A test chip is fabricated in a 65 nm CMOS process and operates at 90 MS/s. Measurements demonstrate that the proposed amplifier achieves 45% noise power reduction in the amplification phase along with improved linearity and lower power consumption, when compared with the conventional amplifier. [ABSTRACT FROM AUTHOR]

A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented. The procedure is focused on the development of ultra-low-power amplifiers requiring low silicon area but being able to drive high capacitive loads. Indeed, by following the presented methodology we designed a CMOS OTA in a 0.35-\mum technology that occupies only 4.4\cdot 10^-3\ mm^2, is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF. Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered. Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 mV/\mus with the 200 pF load. Comparison with prior art shows an improvement factor in the figures of merit higher than 5. [ABSTRACT FROM AUTHOR]

The Bode-Fano bounds on the integral over all frequency of the logarithm of the reflection coefficient between a source and a load, connected to each other through a passive matching network, are well-known measures of the bandwidth of the matching network and load. When there are multiple coupled loads being driven by multiple independent sources, the notion of a single reflection coefficient is not obvious since energy delivered to one load port may reflect, in part, out another port. Establishing the maximum possible bandwidth of the matching network and loads requires the development of a broadband matching theory that applies to coupled systems. We define a bandwidth measure for coupled loads based on the integral logarithm of their collective power reflection, and develop upper bounds on this measure. These upper bounds can be used to examine the effects of coupling on bandwidth, and to evaluate the broadband performance of matching networks for an arbitrary number of coupled loads. [ABSTRACT FROM AUTHOR]

If present, nonlinear effects in a six-port modulator cause distortion and degradation of the quality of the modulated output waveform. How nonlinear effects occur and their impact on system performance were derived in a mathematical model. The model shows that non-ideal performance of the passive six-port correlator is the main contributor to nonlinear distortion. Simulations and measurements on two manufactured six-port modulators were used to validate the theory and to give deeper insight on system performance. It is shown that by using a differentially signaled six-port modulator instead of a single-ended six-port modulator, better performance is achieved over a wide bandwidth. For an error vector magnitude of less than 10%, the relative bandwidth was measured to 12% for the single-ended but 30% for the differentially signaled modulator [ABSTRACT FROM AUTHOR]

An ultra-low-power wake-up receiver is proposed to reduce the energy consumption through adoption of two wake-up modes of operation with different power dissipations and detection bandwidths. During the Monitoring (MO) mode, the start frame bits are received at a data rate of 10 kbps, while during the Identifier (ID) mode the remaining wake-up pattern is transmitted at 200 kbps. By lowering the gain of the front-end amplifier in the MO mode the power dissipation is reduced, which in turn causes an increase in the overall noise figure of the receiver. However, adequate sensitivity is maintained by intentionally lowering the data rate as well as the detection bandwidth of the receiver. The proposed wake-up receiver is designed and fabricated in IBM 130 nm technology with a core size of about 0.2 mm^2 for the target frequency range of 902–928 MHz. The measured results show that the proposed dual-mode receiver achieves a sensitivity of -78.5 dBm and -75 dBm while dissipating an average power of 16.4 \muW and 22.9 \muW during MO and ID modes, respectively. [ABSTRACT FROM AUTHOR]

A hybrid baseband chain for Long-Term Evolution (LTE) was implemented in a TSMC 65-nm CMOS process. It has an active area of 0.75 mm^2 and a power consumption of 10.8 mW at a supply of 1.8 V. The proposed baseband chain consists of a continuous-time (CT) lowpass filter and a charge-domain discrete-time (DT) filter with a variable gain amplifier (VGA) and a DC-offset canceller (DCOC). The passband distortion of the DT filter is calibrated by varying the quality (Q)-factor of the CT filter, which is easily tuned by switched-resistors. The charge-domain DT filter is adopted for anti-aliasing filtering and efficient interferer rejection with small size and low power consumption. By combining the CT and the DT filters, the baseband chain acquires improved passband flatness with an in-band ripple of less than 1 dB from 0.7 MHz to 10 MHz. It also has a gain of 50.8 dB, input-referred noise of 22.8 nV/\surdHz, and an out-of-band IIP3 of 29 dBm. [ABSTRACT FROM AUTHOR]

This article presents a bandwidth extended digital predistortion system suitable for LTE-advanced applications. The proposed predistortion system uses a two-box architecture based on the cascade of a memory polynomial followed by a memoryless predistortion function. The memoryless predistorter is identified offline and used to perform a coarse linearization which cancels out most of the static nonlinearity of the device under test allowing for a reduced observation bandwidth for the synthesis of the memory polynomial predistortion sub-function. The proposed predistorter was experimentally validated and its performance benchmarked against a predistorter having the same structure but identified using the conventional approach. The measurement results demonstrate that the proposed predistorter requires 30% less sampling speed for the analog to digital converter of the feedback path. [ABSTRACT FROM AUTHOR]

A signal- and transient-current boosting (STCB) circuit is proposed and applied to a single-stage amplifier driving large capacitive loads. The proposed STCB circuit provides gain-bandwidth product (GBW) extension, slew-rate (SR) improvement and gain enhancement to the amplifier, with only slight alterations to the frequency response and transient response of the single-stage amplifier driving large capacitive loads. No on-chip capacitor or resistor is required. The STCB amplifier is fabricated in a commercial 0.18-\mum CMOS technology. The active chip area is 0.00705 mm^2. The supply is 1.8 V, and the current consumption is 20.3 \muA. The capacitive load (CO) ranges from about 4.4 nF to 19 nF. The measured results with a \sim19-nF load show the small-signal figure-of-merit (FOMS=\rm GBW\cdot CO/{\rm power}) and the large-signal figure-of-merit (FOML=\rm SR\cdot CO/{\rm power}) are 150345 MHz \cdot pF/mW and 31213 V/\mus\cdotpF/mW, respectively, which correspond to improvements of 1.52 times and 1.36 times, respectively, to the prior art. The achieved phase margin and gain margin are 80.8^\circ and 36.3 dB, respectively. [ABSTRACT FROM AUTHOR]

A 6-bit 1 GS/s single-channel pipeline ADC using an incomplete settling concept is presented. A background sampling-point calibration is proposed to adjust MDAC sampling point so that low gain and low bandwidth opamp can be utilized to conserve power. The prototype ADC in 65-nm CMOS process exhibits an INL of +0.76/-0.68 LSB and a DNL of +0.72/-0.68 LSB. Its ENOB is 5.25 bits at Nyquist input frequency with the conversion rate of 1 GS/s. It consumes 62 mW including calibration circuit power at 1 V supply and occupies an active chip area of 0.3 mm^2. [ABSTRACT FROM AUTHOR]

The all-pass filter method is proposed to approximately realize time-delayed chaotic electronic circuits. The amplitude-frequency characteristic and group time delay of the all-pass filter are analyzed and compared with the known low-pass filter. The number of filters in cascade is evaluated. Using the all-pass filter method, the infinite-dimensional time-delayed nonlinear system is reduced to finite-dimensional ordinary differential equations. The corresponding time-delayed chaotic electric circuits with all-pass filters are constructed, which are experimentally proven to be effective in the range of precision. The obtained experimental results well confirm the theoretical and numerical results. The proposed method is specifically suitable for the implementation of chaotic circuits with long time delay. [ABSTRACT FROM AUTHOR]

A lossless multi-way outphasing and power combining system for microwave power amplification is presented. The architecture addresses one of the primary drawbacks of Chireix outphasing; namely, the sub-optimal loading conditions for the branch power amplifiers. In the proposed system, four saturated power amplifiers interact through a lossless power combining network to produce nearly resistive load modulation over a 10:1 range of output powers. This work focuses on two microstrip-based power combiner implementations: a hybrid microstrip/discrete implementation using a combination of microstrip transmission line sections with discrete shunt elements, and an all-microstrip implementation incorporating open-circuited radial stubs. We demonstrate and compare these techniques in a 2.14 GHz power amplifier system. With the all-microstrip implementation, the system demonstrates a peak CW drain efficiency of 70% and drain efficiency of over 60% over a 6.5-dB outphasing output power range with a peak power of over 100 W. We demonstrate W-CDMA modulation with 55.6% average modulated efficiency at 14.1 W average output power for a 9.15-dB peak to average power ratio (PAPR) signal. The performance of this all-microstrip system is compared to that of the proposed hybrid microstrip/discrete version and a previously reported implementation in discrete lumped-element form. [ABSTRACT FROM AUTHOR]

A reconfigurable 65-nm continuous-time low-pass delta-sigma modulator operates with a sampling frequency from 491 MHz to 1536 MHz, a signal bandwidth from 10 MHz to 100 MHz, and a dynamic range of 75.4 dB to 62.8 dB, respectively. Flash ADC calibration and reference shuffling with zipper rotation are used to improve the linearity of the flash, while also increasing the highest sampling rate and bandwidth of the modulator. Dynamic element matching using a randomized incremented pointer improves the linearity of the DAC. [ABSTRACT FROM AUTHOR]

Bench characterization of wide band oversampled converters is a challenge due to the high data rate at the output of the modulator. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feedthrough effects. Experimental results from a test chip in 90 nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing single-bit CTDSM from 3.6 GHz to 4.4 GHz. [ABSTRACT FROM AUTHOR]

An intelligent Reinforcement Learning (RL) Network-on-Chip (NoC) is proposed as a communication architecture of a heterogeneous many-core processor for portable HD object recognition. The proposed RL NoC automatically learns bandwidth adjustment and resource allocation in the heterogeneous many-core processor without explicit modeling. By regulating the bandwidth and reallocating cores, the throughput performances of feature detection and description are increased by 20.4% and 11.5%, respectively. As a result, the overall execution time of the object recognition is reduced by 38%. The proposed processor with RL NoC is implemented in a 65 nm CMOS process, and it successfully demonstrates the real-time object recognition for a 720 p HD video stream while consuming 235 mW peak power at 200 MHz, 1.2 V. [ABSTRACT FROM AUTHOR]

A comparative design study of ultra-low-power discrete-time \Delta \Sigma modulators (DT \Delta \SigmaMs) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive filter. Two design variants of 2nd-order \Delta \SigmaMs are analyzed and compared to a power-optimized standard active modulator (\Delta \Sigma MAA). The first variant (\Delta \Sigma MAP) employs an active filter in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less \Delta \Sigma MPP) makes use of passive filters in both stages. For practical verification, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the \Delta \Sigma MAA, \Delta \Sigma MAP, and \Delta \Sigma MPP achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 \muW, 1.27 \muW, and 0.92 \muW, respectively, from a 0.9 V supply. Furthermore, the \Delta \Sigma MPP can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step. [ABSTRACT FROM AUTHOR]

A new paradigm for the analysis of super-regenerative (SR) receivers is proposed. Unlike the methodology used in the past where alternately stable and unstable modes of operation are considered, this approach models the system as a stable filter with modulators at the input and output. Consequently, the behavior of SR systems can be viewed using steady state techniques as opposed to time-varying transient analysis. The basic mathematical result derived using this paradigm is compared to the currently accepted solution in the literature and is found to be essentially the same. Then, using state space techniques this solution is modified to obtain newly derived results for the envelope solution, where the resulting down-conversion enables an extremely efficient simulation approach. Finally, the paradigm is extended to show that with the addition of frequency modulation, an even more accurate closed form solution to the problem is available. Simulation results are offered which validate the analysis. [ABSTRACT FROM PUBLISHER]

A scaled 40 Gb/s optical receiver incorporating a transimpedance amplifier (TIA), a limiting amplifier (LA), a clock and data recovery (CDR), and a 1:4 demultiplexer was proposed in 65 nm CMOS technology. The TIA employs a regulated cascode structure to achieve low input resistance and a stable dc operating point, whereas the LA adopts the third-order interleaving active feedback technique to obtain greater bandwidth and flatter frequency response. A 10 GHz LC-based voltage controlled oscillator with a ring structure that generates eight phases is presented. A quarter-rate phase detector in the CDR samples the 40 Gb/s input data, which are retimed and demultiplexed into four sets of 10 Gb/s output data. Experimental results show that the recovered clock exhibits a phase noise of -112.39 dBc/Hz@10 MHz from a carrier frequency of 10 GHz, in response to 2^31-1 PRBS input. The retimed and demultiplexed data exhibit a peak-peak jitter of 4.46 ps and an RMS jitter of 1.18 ps. The core circuit of the receiver consumes 160 mW from a 1.2 V supply. [ABSTRACT FROM PUBLISHER]

We propose a new information theoretic approach to understanding analog-to-digital (A/D) conversion principles. An A/D converter is characterized as a communication system that transmits information from an analog source to the digital domain for processing, storage, transmission, and analysis. Accordingly, an A/D conversion system consists of an analog source of information, a means to sample and encode the analog signal for transmission through the comparator, and a means to decode the digital output from the comparator and provide a digital representation of the analog signal. The comparator acts as a channel since it “injects” uncertainty in the form of quantization noise. We provide an upper bound (conversion capacity) on the amount of information that can be transmitted from the analog to digital domain for a specific A/D converter and we describe a necessary and sufficient condition that, if satisfied, allows an A/D converter to achieve capacity. The conversion capacity defines a fundamental upper limit on the performance of an A/D converter in terms of resolution-bandwidth product for a given technology. It is shown how the conversion capacity may be utilized to yield performance limitations in terms of mean square error and SNR. The capacity is, thus, a useful metric for the comparison of ADC designs and may also provide hints to improving existing and conceiving new A/D conversion methods. [ABSTRACT FROM PUBLISHER]

The linear amplification using non-linear components (LINC) power amplifier architecture uses saturated amplifiers to achieve high efficiency and linearity. However, the non-linear operations for LINC separation lead to bandwidth expansion. The expanded bandwidth causes problems for the analog circuitry and effectively places a limit on the modulation bandwidth of the transmitted signal. We show that for multi-carrier signals, it is the phase component of the transmitted modulation that dominates the spectrum of the LINC components. A novel bandwidth reduction scheme is then proposed for these components. The scheme repetitively limits the bandwidth of the LINC components while inhibiting envelope variations. Measurements show a 46% bandwidth reduction while still meeting the WLAN spectrum mask. This implies an increase of 85% in the modulation bandwidth of the transmitted signal. [ABSTRACT FROM PUBLISHER]

A transimpedance amplifier (TIA) based on an inverting voltage amplifier with a shunt feedback resistor using a noise cancelling technique is presented. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50 \Omega differential output driver to provide an interface to the measurement setup. The TIA shows a measured optical sensitivity of -20.7 dBm for a BER of 10^-9 using an external photodiode (PD). Another chip with the same TIA and an integrated N+/Psub PD is also introduced. The optical receiver achieves a measured transimpedance gain of 78 dB\Omega, 1.5 GHz bandwidth and a measured input referred noise current density of 7.2 pA/\surdHz up to 1.5 GHz. The power consumption of the TIA is only 4.1 mW and the complete chip dissipates 12 mW for a single 1 V supply voltage. [ABSTRACT FROM PUBLISHER]

Realizations of voltage-mode and current-mode complex filters based on transconductance, transresistance, and current amplifiers for intermediate frequency (IF) applications are systematically developed. Various amplifiers are realized utilizing the second generation current conveyor (CCII) to promote comparisons at device levels. The adopted approach shows that the most efficient designs in terms of the number of active components are current-mode filters based on the transconductance and current amplifiers. As an application example, a 4th-order complex filter based on the CA is designed for low-IF Bluetooth receiver. Fabricated in a standard 0.18 \mum CMOS technology, experimental results show that the proposed design offers improved characteristics over the available solutions in terms of power consumption and spurious-free dynamic range (SFDR). The filter exhibits in-band SFDR of 65.8 dB while consuming 1 mW. [ABSTRACT FROM PUBLISHER]

The ANSI S1.11 1/3-octave filter bank is suitable for digital hearing aids, but its large group delay and high computational complexity complicate matters considerably. This study presents a 10-ms 18-band quasi-ANSI S1.11 1/3-octave filter bank for processing 24 kHz audio signals. We first discuss a filter order optimization algorithm to define the quasi-ANSI filters. The group delay constraint of filters is limited to 10 ms. The proposed design adopts an efficient prescription-fitting algorithm to reduce inter-band interference, enabling the proposed quasi-ANSI filter bank to compensate any type of hearing loss (HL) using the NAL-NL1 or HSE prescription formulas. Simulation results reveal that the maximum matching error in the prescriptions of the mild HL, moderate HL, and severe-to-profound HL is less than 1.5 dB. This study also investigates the complexity-effective multirate IFIR quasi-ANSI filter bank. For an 18-band digital hearing aid with a 24 kHz sampling rate, the proposed architecture eliminates approximately 93% of the multiplications and up to 74% of the storage elements, compared with a parallel FIR filters architecture. The proposed analysis filter bank (AFB) was designed in UMC 90 nm CMOS high-VT technology, and on the basis of post-layout simulations, it consumes 73 \muW (@VDD=1 V). By voltage scaling (to 0.6 V), the simulation results show that the power consumption decreases to 27 \muW, which is approximately 30% of that consumed by the most energy-efficient AFB available in the literature for use in hearing aids. [ABSTRACT FROM AUTHOR]

An integrate-and-dump receiver based on an active feedback integrator is demonstrated in a 45-nm SOI CMOS process. The integrate-and-dump receiver provides matched filtering for non-return-to-zero, return-to-zero, and pulse amplitude modulation digital modulation formats, resulting in high SINAD as well as inherent anti-aliasing/low-pass filtering for a 2 GS/s high linearity/high-dynamic-range optical sampling receiver. The measured SINAD is greater than 28 dBc with a sinusoidal input up to 1 GHz; the SNR is greater than 29 dBc. The 2-GS/s integrate-and-dump receiver consumes less than 100 mW. The chip area is 0.980x0.762 mm^2 including the pads. [ABSTRACT FROM AUTHOR]

A low-noise, high-gain, wide-linear-dynamic-range, wide-band receiver for a pulsed, direct, three-dimensional ranging LADAR system has been designed and implemented in a 0.13 \mum CMOS technology. Specific design techniques, including gain control scheme to widen linear dynamic range, gain allocating between blocks and noise minimization to improve SNR, frequency response compensation to extend bandwidth and ensure system stability, and output voltage swing boosting, have been proposed to achieve challenging design goals with linear dynamic range of 1:1600, equivalent input-referred current noise of less than 5.6 pA/\surdHz, high gain of 78 dB\Omega, maximum output swing of at least 500 mV, bandwidth of at least 500 MHz, and low sensitivity to temperature variation over the range from -10^\circC to 60^\circC, in the presence of 2 pF photodiode parasitic capacitance. [ABSTRACT FROM AUTHOR]

A pipelined ADC, reconfigurable over bandwidths of 0.2–22 MHz (sampling frequencies of 0.4–44 MS/s) and resolutions of 10–12 bits, is described for applications in multi-standard wireless terminals. Fabricated in a 1.2-V 90-nm digital CMOS technology, this ADC achieves low power (figure-of-merit of FOM=0.35 to 0.5 pJ per A/D conversion step) over its full bandwidth-resolution range. Accordingly, compared to state-of-the-art power-efficient reconfigurable pipelined ADCs, this ADC provides a larger bandwidth-resolution reconfigurability space, while maintaining a highly competitive FOM over this entire space. To achieve such low-power performance in a low-voltage nanometer CMOS process, this work utilizes: 1) a current-scalable frequency-compensation technique to design low-power current-scalable two-stage opamps; 2) a switched-capacitor technique to design dynamic comparators with low input capacitance (input-loading effect); and 3) a low-power digital background gain-calibration technique. The large bandwidth and resolution reconfigurability ranges are achieved using current-scaling and stage-bypass techniques, respectively. [ABSTRACT FROM PUBLISHER]

A current feedback driver with double zeros compensation is proposed for medium to large AMOLED displays. The zeros for lead compensation are implemented with switched-capacitor circuits to reduce chip area. The selection rules for compensation capacitors and zero capacitors are described to obtain wide bandwidth and high speed. The proposed driver has a settling time of 7∼\mus for the panel load of 10∼k\Omega/100∼pF. De-multiplexing operation is realized to drive two channels using one proposed driver. The chip area is 120 \times 183∼\mum^2 per two channels in a 0.35∼\mum CMOS process. [ABSTRACT FROM AUTHOR]

A low-power variable-gain amplifier (VGA) based on transconductance (gm)-ratioed amplification is analyzed and designed with improved linearity. The VGA has the merits of continuous gain tuning, low power consumption and small chip area. However, the linearity performance of the gm-ratioed amplifier is usually poor. We analyze distortion in gm-ratioed amplifiers and propose to improve the output linearity by applying load degeneration technique. It is found that theoretically the output linearity can be improved by 8.5 dB at the same power consumption. We also analyze gain, bandwidth and noise performance of the gm-ratioed amplifiers. Two VGAs based on gm-ratioed amplification are designed and fabricated in a 0.18-\mu\ m CMOS process—one with load degeneration only and the other with both input and load degeneration. The VGA with load degeneration only achieves gain of -20 to 41 dB, bandwidth of 121 to 211 MHz, and input and output P1dB up to - 17∼\ dBm and 0.65 dBm, respectively. The VGA with both input and load degeneration achieves gain of -37 to 28 dB, bandwidth of 76 to 809 MHz, and input and output P1dB up to - 2.63∼\ dBm and 2.29 dBm, respectively. The two VGAs consume a similar amount of power, which is about 3 to 5 mW from a 1.8-V supply. For the same bias condition, the proposed load degeneration improves the output linearity by more than 15 dB. [ABSTRACT FROM AUTHOR]

We have developed a low-power VLSI chip for 60-kWord real-time continuous speech recognition based on a context-dependent hidden Markov model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian mixture model (GMM) computation based on the mixture level, a variable-frame look-ahead scheme, and elastic pipeline operation between the Viterbi transition and GMM processing. The accuracy degradation of the important parameters in Viterbi computation is strictly discussed. Results show that our implementation achieves 95% bandwidth reduction (70.86 MB/s) and 78% required frequency reduction (126.5 MHz) comparing to the referential Julius refid="ref1"/ system. The test chip, fabricated using 40 nm CMOS technology, contains 1.9 M transistors for logic and 7.8 Mbit on-chip memory. It dissipates 144 mW at 126.5 MHz and 1.1 V for 60-kWord real-time continuous speech recognition. [ABSTRACT FROM PUBLISHER]

A fully integrated dual-channel reconfigurable GNSS receiver supporting Compass/GPS/GLONASS/Galileo systems is implemented in 65 nm CMOS. The receiver incorporates two independent channels to receive dual-frequency signals simultaneously. GNSS signals located at the 1.2 GHz or 1.6 GHz bands are supported, with their bandwidths programmable among 2.2 MHz, 4.2 MHz, 8 MHz, 10 MHz, and 18 MHz. By implementing a flexible frequency plan with a low/zero-IF architecture and reconfigurable analog baseband circuits, only one frequency synthesizer is required to provide the local oscillator (LO) frequency for two channels, thereby avoiding any LO crosstalk. Analog baseband circuits employ operational amplifiers that are capable of power scaling, in order to minimize power consumption across different operating modes. An I/Q mismatch calibration module placed prior to the complex-IF bandpass filter is implemented to improve the image rejection ratio. The receiver achieves a minimum 1.88 dB noise figure, an average 50 dB image rejection ratio, and a 64 dB dynamic range with 1 dB steps of gain-adjustment, with a total power consumption of 31–44 mW. Finally, experimental verification combining both the receiver and a digital baseband shows a positioning result comparable to commercial chips. [ABSTRACT FROM PUBLISHER]

Online adaptive equalization is proposed to calibrate channel mismatch errors in time-interleaved (TI) analog-to-digital converter (ADC) arrays with a linear reference path. Code-domain filters are shown to be effective in removing interchannel as well as intrachannel nonlinearity and mismatch errors, including offset, gain, and differential nonlinearity (DNL) and integral nonlinearity (INL) mismatches. An 8-bit, 600-MS/s, 0.13- μm CMOS prototype measured a signal-to-noise plus distortion ratio (SNDR) of 31.0/47.4 dB, a spurious-free dynamic range (SFDR) of 32.8/63.6 dB, a DNL of 1.30/0.30 LSBs, and an INL of 1.70/0.23 LSBs in lab testing without/with equalization, respectively. [ABSTRACT FROM PUBLISHER]

Cascode loads are commonly assumed to be frequency independent nevertheless: it is shown that cascode loads introduce a pole-zero pair into the amplifier's frequency response. Unfortunately, when designing high-gain high-speed amplifiers based on “all NMOS signal path” concepts, the pole-zero pair introduced by the PMOS cascode is likely to be located near the amplifier's closed-loop bandwidth. Unlike pole-zero pairs located far from the amplifier's closed-loop bandwidth, the effect of pole-zero pairs located near the amplifier's closed-loop bandwidth is highly dependent on the exact configuration of the amplifier. While not always possible, minimizing the capacitance on the cascode node minimizes the effects of this undesirable pole-zero pair. [ABSTRACT FROM PUBLISHER]

A 25 Gb/s laser diode (LD) driver has been developed on the basis of standard 65 nm CMOS technology for optical interconnects. The LD driver consists of a main driver capable of providing an average current of 30 mA and a predriver providing a gain of 20 dB. The main driver uses mutually coupled inductors to adjust the inductive peaking to improve eye patterns under various packaging conditions. The predriver uses CMOS active feedback to achieve a wide bandwidth and high gain, despite its small size and low power consumption. The fabricated circuit achieves data rates of 25 Gb/s, consumes 156 mW (6.3 mW/Gb/s) and occupies an area of 0.011 \mm^2. [ABSTRACT FROM PUBLISHER]

A 12b 50 MS/s 0.18 \mum CMOS pipeline ADC is described. The proposed capacitor and operational amplifier (op-amp) sharing techniques merge the front-end sample-and-hold amplifier (SHA) and the first multiplying digital-to-analog converter (MDAC1) to achieve low power without an additional reset timing and a memory effect. The second and third MDACs share a single op-amp to reduce power consumption further. A shared op-amp of the merged SHA and MDAC1 controls properly the input trans-conductance for stability at each clock phase of holding and amplifying. The prototype ADC in a 0.18 \mum CMOS process demonstrates the measured differential and integral nonlinearities within 0.53 LSB and 2.09 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 60.6 dB and a maximum spurious-free dynamic range of 69.4 dB at 50 MS/s. The ADC with an active die area of 0.93 mm^2 consumes 21.6 mW at 50 MS/s and 1.8 V. [ABSTRACT FROM PUBLISHER]

Architectural and circuit techniques to integrate the RF front end passive components, namely the SAW filters and duplexers that are traditionally implemented off chip, are presented. Intended for software-defined and cognitive radio platforms, tunable high-Q filters realized by CMOS switches and linear or MOS capacitors allow the integration of highly reconfigurable transceiver front ends that are robust to in-band and out-of-band blockers. Furthermore, duplexer techniques based on electrical balance concepts are introduced to enable highly integrated and programmable radios for full-duplex applications such as 3/4G transceivers. Several case studies are presented that offer highly linear and low-noise transceiver front ends that satisfy the challenging requirements of cellular standards, yet offer considerably lower cost and size compared to the state-of-the-art transceivers available today. [ABSTRACT FROM PUBLISHER]

An adaptive resolution (AR) asynchronous analog-to-digital converter (ADC) architecture is presented. Data compression is achieved by the inherent signal dependent sampling rate of the asynchronous architecture. An AR algorithm automatically varies the ADC quantizer resolution based on the rate of change of the input. This overcomes the trade-off between dynamic range and input bandwidth typically seen in asynchronous ADCs. A prototype ADC fabricated in a 0.18 \mum CMOS technology, and utilizing the subthreshold region of operation, achieves an equivalent maximum sampling rate of 50 kS/s, an SNDR of 43.2 dB, and consumes 25 \muW from a 0.7 V supply. The ADC is also shown to provide data compression for accelerometer applications as a proof of concept demonstration. [ABSTRACT FROM PUBLISHER]

An 11.75-Gb/s combined decision feedback equalizer (DFE) and clock data recovery circuit in a 0.18-\mu\m CMOS is presented. Various techniques are applied to reduce the chip power consumption. In particular, the feedback path of the DFE is merged with an Alexander phase detector (PD). An analysis on the speed requirements of various blocks in the PD and DFE circuits is performed to determine the optimum power dissipation of each one. It is shown that the chip power consumption is reduced by 31% compared to a conventional design. The chip is capable of equalizing copper cable channels with up to 12-dB loss at the 5.875-GHz Nyquist frequency and consumes 101 mW (not including output buffers) with a 1.8-V supply voltage. [ABSTRACT FROM PUBLISHER]

A 40-Gb/s transimpedance amplifier (TIA) is proposed using multistage inductive-series peaking for low group-delay variation. A transimpedance limit for multistage TIAs is derived, and a bandwidth-enhancement technique using inductive-series \pi-networks is analyzed. A design method for low group delay constrained to 3-dB bandwidth enhancement is suggested. The TIA is implemented in a 0.13-\mu\ m CMOS process and achieves a 3-dB bandwidth of 29 GHz. The transimpedance gain is 50 \ dB\cdot\Omega, and the transimpedance group-delay variation is less than 16 ps over the 3-dB bandwidth. The chip occupies an area of 0.4 \ mm^2, including the pads, and consumes 45.7 mW from a 1.5-V supply. The measured TIA demonstrates a transimpedance figure of merit of 200.7 \Omega/\pJ. [ABSTRACT FROM PUBLISHER]

A polar modulator for wireless RF transmitters nonlinearly transforms complex-valued Cartesian baseband modulating signal into amplitude and phase components of the polar coordinate representation before they are recombined in a power amplifier. The resulting explosion in the bandwidth requirements of the polar components can so far be only tolerated for narrowband transmitters, such as EDGE of the 2G cellular. To enable polar topology for wideband transmitters, we propose a technique that alters the signal trajectory such that it avoids crossing (and proximity) of the constellation origin. The resulting substantial decrease of the polar modulator bandwidth is traded off against slight increase of in-band modulation distortion and adjacent channel leakage. We illustrate effectiveness of this method using wideband CDMA (WCDMA) of the 3G cellular. The technique is first mathematically analyzed for various tradeoffs followed by high-level modeling and simulation results. Since the technique is fully contained in the digital domain, its performance effects on the entire RF transmitter can be accurately simulated. A digital architecture to implement the proposed technique is also presented. [ABSTRACT FROM PUBLISHER]

The transimpedance limit describes the maximum transimpedance that a transimpedance amplifier (TIA) can attain for a given bandwidth and technology. We analyze and compare this limit for a wide variety of TIA topologies thus exposing their relative merits. The topologies considered are the shunt-feedback TIA with single and multistage amplifier, the shunt-feedback TIA with feedback capacitor, the shunt-feedback TIA followed by a post amplifier, the shunt-feedback TIA with a current amplifier, the common-base/gate feedforward TIA, the shunt-feedback TIA with a common-base/gate input stage, and the shunt-feedback TIA with a regulated-cascode input stage. The analysis includes a discussion of the conditions under which the limit is realizable. [ABSTRACT FROM PUBLISHER]

In this comment, the previous work on bandwidth enhancement of finite gain amplifiers using two or more opamps is brought to the attention of the reader. An analogy between finite gain amplifiers using opamps and current feedback operational amplifiers is also presented. [ABSTRACT FROM PUBLISHER]

A response by Salvatore Pennisi, Giuseppe Scotti and Alessandro Trifiletti to a letter to the editor about their article "Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers" in the September 9, 2011 issue is presented.