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A new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL) is presented. ADCPL is a dual-rail logic with relatively low gate complexity. It operates from a two-phase nonoverlapping supply clock. Power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50%-70% can be achieved over the static complimentary metal oxide semiconductor case within a practical operation frequency range. The results also show that the lower the operating frequency, the larger the energy savings for an ADCPL circuit. Index Terms--Adiabatic circuit, differential cascode voltage logic, low-power circuit, low-power digital system.

Gas identification represents a big challenge for pattern recognition systems due to several particular problems such as nonselectivity and drift. The purpose of this paper is twofold: 1) to compare the accuracy of a range of advanced and classical pattern recognition algorithms for gas identification for the in. house sensor array signals and 2) to propose a gas identification ensemble machine (GIEM), which combines various gas identification algorithms, to obtain a unified decision with improved accuracy. An integrated sensor array has been designed with the aim of identifying combustion gases. The classification accuracy of different density models is compared with several neural network architectures. On the gas sensors data used in this paper, Gaussian mixture models achieved the best performance with higher than 94% accuracy. A committee machine is implemented by assembling the outputs of these gas identification algorithms through advanced voting machines using a weighting and classification confidence function. Experiments on real sensors' data proved the effectiveness of the system with an improved accuracy over the individual classifiers. An average performance of 97% was achieved using the proposed committee machine. [ABSTRACT FROM AUTHOR]

In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized. [ABSTRACT FROM AUTHOR]

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG-S) and bottom gate shift to drain side (DG-D). At the same gate misalignment value, DG-S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG-D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG-S, with 20% gate misalignment length (Lmis) is over gate length (Lg), or Lmis/Lg = 20%, was faster than that of two-gate aligned DG-SOI. [ABSTRACT FROM AUTHOR]

The effects of nonrectangular fin cross section of double-gate FinFETs are studied. For a given top-fin width, which is defined by the photolithography step, the short-channel effect immunity is degraded by the inclination of the sidewalls. The nonrectangular fin geometry also leads to nonuniform current flow and current crowding in the vertical direction. Together with the nonuniform series resistance along the height of the fin, a non-linear dependence of on-current with fin heights (which have been regarded as the Ws in planar MOSFET) is observed. The impacts of nonvertical sidewall have been characterized according to the inclination angle in this work. Under different inclination angles as dictated by the processing technology, the device performances at various fin heights are characterized. A new design constraint that limits the choice of fin height for a given technology is also discussed. [ABSTRACT FROM AUTHOR]

Provides information on a study which fabricated thin-film transistors using the nickel-seeded metal-induced lateral crystallization (MILC) technique. Overview of the nickel-seeded MILC; Device fabrication process; Experimental results and discussion; Design guideline to reduce the grain boundary effect.

Provides information on a study which fabricated thin-film transistors using the nickel-seeded metal-induced lateral crystallization (MILC) in which an amorphous silicon is crystallized to form a large grain polysilicon film. Description of the MILC process; Mobility models of solid phase crystallization and MILC devices; Experimental results and discussion.

Proposes a three-dimensional (3-D) complementary metal oxide semiconductor (CMOS) integrated circuit based on the conventional CMOS silicon-on-insulator technology. Discussion on the 3-D thin film transistor CMOS technology and design issues; Description on the fabrication process; Device characteristics; Inverter characteristics and circuit performance.

Proposes a physically-based noise model which predicts that the excess low-frequency noise shows a Lorentzian-like spectrum. Information on silicon-on-insulator (SOI); Noise sources in an SOI metal-oxide-silicon field-effect transistor; Results and discussions; Conclusions.