51. Optimization of RTA process for PVD-TiN gate FinFETs
- Author
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Yuki Ishikawa, M. Masahara, Kunihiro Sakamoto, Shin-ichi O'uchi, Kazuhiko Endo, Hiromi Yamauchi, T. Kamei, Takashi Matsukawa, Junichi Tsukada, Y. X. Liu, T. Hayashida, and Atsushi Ogura
- Subjects
Electron mobility ,Materials science ,business.industry ,chemistry.chemical_element ,Vapour deposition ,chemistry ,Scientific method ,MOSFET ,Electronic engineering ,Optoelectronics ,Degradation (geology) ,Rapid thermal annealing ,business ,Tin - Abstract
T R dependence of the electrical characteristics have systematically been investigated by fabricating PVD-TiN gate FinFETs. It was found that optimal T R is 915 °C for setting symmetrical V th with a higher I ON and the smallest σV th . It was also confirmed that carrier mobilities are independet of T R and comparable to those in the case of n+-poly-Si gate. The n+-poly-Si capping on PVD-TiN gate is very useful to set symmetrical V th for undoped FinFETs without mobility degradation.
- Published
- 2010
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