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For decades, Moore's Law has been approaching its limits, posing a huge challenge for further downsizing to nanometer dimensions. A promising avenue to replace Moore's Law lies in three-dimensional integrated circuits, where Cu–Cu bonding plays a critical role. However, the atomic diffusion rate is notably low at temperatures below 300 °C, resulting in a distinct weak bonding interface, which leads to reliability issues. In this study, a quenching treatment of the Cu film surface was investigated. During the quenching treatment, strain energy was induced due to the variation in thermal expansion coefficients between the Si substrate and the Cu film, resulting in a wrinkled surface morphology on the Cu film. Grain growth was observed at the Cu–Cu bonding interface following bonding at 300 °C for 2 and 4 h. Remarkably, these procedures effectively eliminated the bonding interface. [ABSTRACT FROM AUTHOR]

For decades, Moore's Law has neared its limits, posing significant challenges to further scaling it down. A promising avenue for extending Moore's Law lies in three-dimensional integrated circuits (3D ICs), wherein multiple interconnected device layers are vertically bonded using Cu–Cu bonding. The primary bonding mechanism involves Cu solid diffusion bonding. However, the atomic diffusion rate is notably low at temperatures below 300 °C, maintaining a clear and distinct weak bonding interface, which, in turn, gives rise to reliability issues. In this study, a new method of surface modification using epoxy resin to form fine grains on a nanotwinned Cu film was proposed. When bonded at 250 °C, the interfacial grains grew significantly into both sides of the Cu film. When bonded at 300 °C, the interfacial grains extended extensively, eventually eliminating the original bonding interface. [ABSTRACT FROM AUTHOR]

X-ray nanotomography is a powerful tool for the characterization of nanoscale materials and structures, but it is difficult to implement due to the competing requirements of X-ray flux and spot size. Due to this constraint, state-of-the-art nanotomography is predominantly performed at large synchrotron facilities. We present a laboratory-scale nanotomography instrument that achieves nanoscale spatial resolution while addressing the limitations of conventional tomography tools. The instrument combines the electron beam of a scanning electron microscope (SEM) with the precise, broadband X-ray detection of a superconducting transition-edge sensor (TES) microcalorimeter. The electron beam generates a highly focused X-ray spot on a metal target held micrometers away from the sample of interest, while the TES spectrometer isolates target photons with a high signal-to-noise ratio. This combination of a focused X-ray spot, energy-resolved X-ray detection, and unique system geometry enables nanoscale, element-specific X-ray imaging in a compact footprint. The proof of concept for this approach to X-ray nanotomography is demonstrated by imaging 160 nm features in three dimensions in six layers of a Cu-SiO2 integrated circuit, and a path toward finer resolution and enhanced imaging capabilities is discussed. [ABSTRACT FROM AUTHOR]

In this study, we developed a shallow defect layer formation process using moderate-pressure H2 plasma at 3.3 kPa for an extrinsic gettering layer of ultra-thin Si chips aimed at three-dimensional integrated circuits. This process can be conducted in the presence of trivial amounts of air impurities (∼0.01 vol. %), thereby avoiding the use of high-vacuum equipment. We investigated the dependence of defect formation behavior on various processing parameters such as H2 flow rate, processing time, substrate temperature, and input power. It was determined that the absence of H2 gas flow was favorable for the defect layer formation because Si etching by hydrogen atoms was suppressed. A low Si temperature and high input power are desirable for a high defect density in the shallow surface region of the extrinsic gettering layer. When pulse-modulated plasma irradiation was attempted, the defect layer that formed became thinner and had a higher defect density than that obtained by continuous plasma, demonstrating good Cu gettering performance. Without using harmless chemicals, or high-cost equipment, a shallow gettering layer can be formed using inexpensive H2 gas. [ABSTRACT FROM AUTHOR]

In soft electronics, anisotropic conductive adhesive films (ACFs) are the trending interconnecting approach due to their substantial softness and superior bondability to flexible substrates. However, low bonding pressure (≤1 MPa) and fine-pitch interconnections of ACFs become challenging while being extended in advanced device developments such as wafer-level packaging and three-dimensional multi-layer integrated circuit board assembly. To overcome these difficulties, we studied two types of ACFs with distinct conductive filler sizes (ACF-1: ~20 μm and ACF-2: ~5 μm). We demonstrated a low-pressure thermo-compression bonding technique and investigated the size effect of conductive particles on ACF's mechanical properties in a customized testing device, which consists of flexible printing circuits and Flex on Flex assemblies. A consistency of low interconnection resistance (<1 Ω) after mechanical stress (cycling bending test up to 600 cycles) verifies the assembly's outstanding electrical reliability and mechanical stability and thus validates the great effectiveness of the ACF bonding technique. Additionally, in numerical studies using the finite element method, we developed a generic model to disclose the size effect of Au/Ni-coated polymer fillers in ACF on device reliability under mechanical stress. For the first time, we confirmed that ACFs with smaller filler particles are more prone to coating fracture, leading to deteriorated electrical interconnections, and are more likely to peel off from substrate electrode pads resulting in electrical faults. This study provides guides for ACF design and manufacturing and would facilitate the advancement of soft wearable electronic devices. [ABSTRACT FROM AUTHOR]

In this article, we propose a fast three‐dimensional integrated circuit (3D‐IC) floorplanning method for hard macroblocks that includes a thermal management scheme. It applies a genetic algorithm constituted by an optimal combination of crossover and mutation operations to identify the optimal solution for design variables, namely, total wire length, number of through‐silicon vias (TSVs), and maximum average layer power density. The proposed method additionally makes use of a unique TSV placement scheme that arranges TSVs next to their respective functional blocks. To enable efficient heat transmission to the ambient environment, layers with higher power densities are placed closer to the heat sink. The proposed 3D‐IC floorplanning approach provides the fewest TSVs, the lowest peak temperature, and promising values of wire length within the least amount of computation time. Compared to the recent fast thermal analysis for fixed‐outline 3D‐floorplanning, it generates 13.14% shorter wire length, 39.27% lower peak temperature, and 34.35% lesser number of TSVs on average with significant improvement in computation time, while analyzing GSRC thermal benchmark circuits. [ABSTRACT FROM AUTHOR]

Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper–copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process. [ABSTRACT FROM AUTHOR]

A high-resolution frontside fault isolation methodology for the analysis of wafer-to-wafer (W2W) hybrid bonding interconnects in three-dimensional integration is reported. The approach utilizes the visible light optical beam induced resistance change (VL-OBIRCH) method and incorporates a localized substrate removal technique, eliminating the need for a costly backside approach that requires a solid immersion lens. The top silicon substrate is removed using laser lithography and selective etching techniques, enabling the utilization of 405 nm excitation light for the VL-OBIRCH analysis. The validity of the methodology is demonstrated on W2W interconnect test structures with varying interconnect pitch and pad dimensions. The effectiveness of the proposed approach is confirmed through cross-sectional analysis. [ABSTRACT FROM AUTHOR]

Considering the manufacturing and packaging process, 3-D integrated circuits design often requires irregular chip structures. The 3-D integrated circuits with irregular structures can facilitate differentiated chip design and reduce manufacturing costs. Highly complex through-silicon vias have not been considered in past thermal modelling and analysis of irregularly structured 3-D integrated circuits. Thus, a detailed model of a three-layer irregularly structured 3-D integrated circuit with through-silicon vias and microbumps is developed, and an analytical method based on the thermal resistance network model is proposed to extract the equivalent thermal conductivity of through-silicon vias and microbumps, the accuracy of which is verified by a 3-D finite element simulation method. The results show that the maximum temperature and temperature gradient obtained by the equivalent model simulations agree well with the detailed model results, proving the validity of the equivalent model. To save the computational cost, the effects of heat source area, power setting and through-silicon vias structure parameters on the maximum temperature are studied by numerical simulation method based on the equivalent model. Heat source area equal to the overlap between chip layers, high power chips close to the heat sink, and reducing through-silicon vias pitch can better reduce the maximum temperature. The results provide a reference value for thermal design and optimization of 3-D integrated circuits with irregular structures. [ABSTRACT FROM AUTHOR]

In the past few years, thermal through silicon via (TTSV) has been experimentally investigated as an effective heat dissipation path. Although a lot of heat dissipation- related issues have been solved in 3-D integrated circuit (3-D-IC), there are neglections in TTSV placement with non-uniform heat sources so far. In this study, a unique optimization is proposed to locate TTSV while effectively alleviating hot spots in 3-D-IC. The thermal dissipation of non-uniform heat sources are studied using the finite element method. The simulation results show that the minimum temperature is reduced by 2.1% compared with peak temperature in the single-layer chip, and by 1.9% in the three-layer chip. [ABSTRACT FROM AUTHOR]

The results of a theoretical study of the behavior of a system of nanophotonic devices, consisting of receiving and transmitting plasmonic metal antennas, are presented. Based on the finite element method, the main parameters of antennas located in the TSV channel and receiving a signal in the terahertz frequency range are calculated. The limiting range of signal transmission and the coefficient of its amplification are determined. Conclusions are drawn on the suitability of the presented configuration as a system for wireless data transmission and reception in three-dimensional integrated circuits. [ABSTRACT FROM AUTHOR]

The development of big data and artificial intelligence technology is increasing the need for electronic devices to become smaller, cheaper, and more energy efficient, while also having enhanced functionalities. However, the miniaturization of silicon chip technology is approaching its Moore's law (i.e., physical) limits. Thus, the application of three-dimensional integrated circuits (3D ICs), in which multiple chips are stacked vertically, provides the most achievable approach for the advancement of post-Moore electronics. In the recent decade, various key techniques have been developed for stacking chips vertically such as through-silicon vias, micro-bumps, low melting point tin–bismuth solders, redistribution layers, and copper-to-copper direct bonding. However, the need for high current densities in these structures results in severe Joule heating, making electromigration (EM) an increasingly challenging problem. This paper reviews studies on EM failures, mechanisms, and potential solutions for the key components of 3D IC packaging. [ABSTRACT FROM AUTHOR]

Through silicon via technology is a promising and preferred way to realize the reliable interconnection for 3-D integrated circuit (3-D IC), which can transfer heat from multiple dies to the heat sink in vertical direction. In this paper, a new general model of the through-silicon via (TSV) is proposed to investigate the thermal performance of the 3-D IC. The heat transfer characteristics of conical-annular TSV are studied for the first time. The impacts of different sidewall inclination angles and insulating layer thicknesses of TSV on the heat dissipation of 3-D IC were compared and analyzed in detail. As expected, our proposed model is in good agreement with the results of the existing models, which shows that the proposed model considering the lateral heat transfer and TSV structures can predict the distribution of temperature more efficiently and accurately. Furthermore, it is found that conical-annular TSV has more excellent heat dissipation performance. [ABSTRACT FROM AUTHOR]

This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integrated circuits, transistors in the bottom tier were exposed to subsequent processes; therefore, selective annealing, such as laser-spike annealing (LSA), should be applied. However, the application of the LSA process to NSFETs significantly decreased the on-state current (Ion) owing to diffusionless S/D dopants. Furthermore, the barrier height below the inner spacer was not lowered even under on-state bias conditions because ultra-shallow junctions between the NS and S/D were formed far from the gate metal. However, the proposed S/D extension scheme overcame these Ion reduction issues by adding an NS-channel-etching process before S/D formation. A larger S/D volume induced a larger stress in the NS channels; thus, the stress was boosted by over 25%. Additionally, an increase in carrier concentrations in the NS channels improved Ion. Therefore, Ion increased by approximately 21.7% (37.4%) in NFETs (PFETs) compared with NSFETs without the proposed scheme. Additionally, the RC delay was improved by 2.03% (9.27%) in NFETs (PFETs) compared with NSFETs using rapid thermal annealing. Therefore, the S/D extension scheme overcame the Ion reduction issues encountered in LSA and significantly enhanced the AC/DC performance. [ABSTRACT FROM AUTHOR]

This paper introduces a new method to reduce the crosstalk effects in copper-multiwalled carbon nanotube (Cu-MWCNT) based heterogeneous coaxial through-silicon vias (HCTSVs) for three-dimensional integrated circuits (3D ICs). The proposed HCTSV structure utilizes Cu-MWCNT bundles as a conducting material and polymer liners such as polyimide, polypropylene carbonate (PPC) and benzo cyclobutene (BCB) as dielectric materials. The crosstalk effects such as functional and dynamic crosstalks are evaluated for the coupled HCTSVs by using an electrical equivalent model implemented in synopsis based HSPICE simulator. Moreover, the other performance parameters such as power consumption, power delay product (PDP) and energy delay product (EDP) are analyzed. From the analysis, it is noticed a significant improvement in crosstalk effects, power consumption, PDP, and EDP for polymer liners over the conventional silicon dioxide liner. Moreover, the performance is also evaluated by changing the different heights of HCTSVs from 50 to 200 μm, respectively. It is observed that the performance of the coupled HCTSVs are increased as the TSV height is reduced. [ABSTRACT FROM AUTHOR]

Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling—the decrease of component sizes—with each new process node continues today, albeit at a slower pace compared with historical rates of scaling. Transistor scaling has resulted in exponential gain in performance and energy efficiency of integrated circuits, which transformed computing from mainframes to personal computers and from mobile computing to cloud computing. Innovations in new materials, transistor structures, and lithographic technologies will enable further scaling. Monolithic 3D integration, design technology co-optimization, alternative switching mechanisms, and cryogenic operation could enable further transistor scaling and improved energy efficiency in the foreseeable future. [ABSTRACT FROM AUTHOR]

Cu-to-Cu direct bonding plays an important role in three-dimensional integrated circuits (3D IC). However, the bonding process always requires high temperature, high pressure, and a high degree of consistency in height. In this study, Sn is passivated over electroplated copper. Because Sn is a soft material and has a low melting point, a successful bond can be achieved under low temperature and low pressure (1 MPa) without any planarization process. In this experiment, Sn thickness, bonding temperature, and bonding pressure are variables. Three values of thicknesses of Sn, i.e., 1 μm, 800 nm, and 600 nm were used to calculate the minimum value of Sn thickness required to compensate for the height difference. Additionally, the bonding process was conducted at two temperatures, 220 °C and 250 °C, and their optimized parameters with required pressure were found. Moreover, the optimized parameters after the Cu planarization were also investigated, and it was observed that the bonding can succeed under severe conditions as well. Finally, transmission electron microscopy (TEM) was used to observe the adhesion property between different metals and intermetallic compounds (IMCs). [ABSTRACT FROM AUTHOR]

In this work, an ultra-thin cobalt film is used as a passivation layer to achieve a Cu–Cu quasi-direct bonding process, and successful bonding was achieved at the bonding temperature of 230 °C with the bonding pressure of 0.5 MPa in non-vacuum conditions. A tensile bonding strength of over 12.8 MPa can be achieved. With the cobalt layer, the total film roughness is greatly reduced to around 1 nm, and the cross-sectional transmission electron microscope images reveal the presence of a void-free bonding interface. Time-of-flight secondary ion mass spectrometry depth analysis is carried out using a PVD deposited multilayer sample, which simulates the bonding process without pressure. It is found that a Cu–Co intermixing layer formed between the Cu and Co interfaces during annealing, and Cu has diffused into the Co layer. Due to the nanocrystalline structure of the Co film and the low roughness of the system, a low bonding temperature can be achieved. These results demonstrate that Co, which can be selectively grown on the Cu surface, can be used as a passivation layer to achieve low-cost and high-quality interconnect for the three-dimensional integrated circuits. [ABSTRACT FROM AUTHOR]

Tier partitioning is one of the most critical stages in monolithic 3-D (M3D) integrated circuits (ICs) implementation flows. It transforms 2-D netlists into 3-D by performing tier assignment for each design instance, which directly impacts the power, performance, and area (PPA) metrics of final 3-D full-chip designs. However, the current state-of-the-art tier partitioning approach named bin-based min-cut algorithm has fundamental flaws that lead to severe drawbacks, such as timing degradation, 3-D routing overhead, and redundant monolithic intertier vias (MIVs) insertion. To overcome these issues, in this article, we propose TP-GNN, an unsupervised graph learning-based tier partitioning framework that utilizes graph neural networks (GNNs) and advanced machine learning (ML) techniques to perform tier partitioning. The proposed framework comprehends design- and technology-related parameters properly so that it is generalizable to various netlists and technologies. In addition, it can be integrated with any style of M3D design flows that require tier assignments of standard cells. In the experiments, we validate the proposed framework on seven industrial designs with two different fashions of M3D implementation flows: 1) partitioning-first (Snap3D) and 2) partitioning-last (Shrunk2D and Compact2D) flows. We demonstrate that our framework, TP-GNN, significantly improves the 3-D quality of results (QoR) across most testing designs in a large margin compared with the bin-based min-cut tier partitioning algorithm. Specifically, in OpenPiton, an RISC-V-based multicore system, we observe 27.4%, 7.7%, and 20.3% improvements in performance, wirelength, and energy-per-cycle, respectively. Finally, we perform a case study by applying the proposed framework to a heterogeneous M3D design flow, Pin3D, on a commercial CPU design and observe that TP-GNN reaches better partitioning solutions than the existing partitioning approaches for heterogeneous 3-D ICs. [ABSTRACT FROM AUTHOR]

In three-dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, yield is one of the key obstacles to adopt the TSV-based 3D-ICs technology in the industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in the literature for yield and reliability enhancement. However, the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this article, we propose an effective TSV repair strategy for the router-based TSV redundancy architecture, taking into account the delay overhead. First, we prove that the router-based fault-tolerance structure configuration (RFSC) with the delay constraint is equivalent to the length-bounded multicommodity flow (LBMCF) problem. Then, an integer linear programming (ILP) formulation with acceptable scalability is presented to solve the LBMCF problem. The experimental results demonstrate that, compared with state-of-the-art fault-tolerance designs, the proposed ILP model can provide higher yield and lower delay overhead. [ABSTRACT FROM AUTHOR]

During the manufacturing process of three-dimensional integrated circuits (3-D ICs), many defects may occur in through-silicon vias (TSVs). These defects affect the integrity of the signal passing through TSVs, therefore detecting these defects in the early production stage is crucial. This article proposed a built-in-self-test (BIST) method with a simple test structure and easily implemented fault detection process. Due to the fact that the defects in TSVs influence the charge/discharge speed of TSVs’ equivalent capacitance, a weak current source is designed as the central part of the proposed test structure, which can measure the TSVs’ charge/discharge speed and quantify it using digital values. The effectiveness and robustness of the proposed method is validated by HSPICE simulation. The minimum measurable fault, test time, and test circuit area are also assessed in this article. The simulation results show that the method this article proposed can detect weaker faults, compared with the traditional test methods. [ABSTRACT FROM AUTHOR]

In this article, an efficient approach based on the parallel alternating direction implicit (ADI) method is presented for the transient thermal simulation of liquid-cooled 3-D integrated circuits (ICs). To accurately characterize the thermal behaviors, a compact thermal model based on finite-difference approximation is established. The ADI method with linear time complexity is utilized to reduce computational cost, which can easily deal with large-scale problems. To suppress the oscillations of transient results in the case of large time steps, an effective technique using the exponentially expanding subtime steps is introduced, which improves the accuracy of results significantly. In addition, taking the advantage of parallel computing, the transient simulation is further accelerated by the parallel cyclic reduction (PCR) algorithm implemented on graphics processing units (GPUs). The accuracy and efficiency of the proposed method are demonstrated by several numerical examples. [ABSTRACT FROM AUTHOR]

In this article, a discontinuous Galerkin time-domain (DGTD) method hybridized with Robin transmission condition (RTC-DGTD) is proposed for the transient thermal analysis of 3-D integrated circuits (ICs). As a kind of domain decomposition method (DDM), the DGTD method employs a term named numerical flux for the information exchange of solutions between neighboring subdomains. The numerical flux is a function of both temperature $T$ and heat flux q, and thus for the heat equation, apart from $T$ , the variable q has to be solved as well. To reach this, the traditional DGTD method decomposes the second-order partial-differential thermal equation into two first-order ones, which results that both $T$ and q need to be solved in the whole computational domain, thereby the computational cost is extremely expensive. In this work, to get this trouble-treated, the proposed DGTD method is directly applied to discretize the second-order heat equation. An RTC is established at the interfaces of subdomains, which serves as the second governing equation and meanwhile bridges another connection of solutions in adjacent subdomains. In this way, the new variable q is now only present at the interfaces of subdomains. Consequently, the total number of unknowns is significantly reduced compared with that in the traditional DGTD method. To further speed up the time-marching scheme, an adaptive time-stepping method in terms of the proportional–integral–derivative (PID) control algorithm is employed. Besides, by introducing a restriction operator, the globally coupled matrix equation is torn into a number of small matrix equations pertinent to each subdomain, which is later solved via a finite-element tearing and interconnecting (FETI)-like method. To validate and verify the accuracy and efficiency of the proposed algorithm, several representative examples are studied and compared with COMSOL simulations. [ABSTRACT FROM AUTHOR]

Through silicon via (TSV) is the key technology for 3-D integrated circuits (3-DICs) which could vertically stack homogeneous or heterogeneous dies with the high performance and density. To evaluate the electrical characteristics of TSV at the high-frequency transmission, the skin effect and surface roughness effect are necessary to be considered. However, these effects would significantly result in the TSV equivalent resistance under the high operating frequency. Thus, it is important to investigate the carbon nano tubes (CNTs) TSV which has less skin effect intrinsically. In this work, we analyze the advantage of CNTs as TSV compared to the conventional filling materials such as copper (Cu). Furtherly, we also propose the equivalent circuit model of TSV and its multi-layer structure to simulate the electrical behaviors with different TSV pitch, height, diameter, and stacking layers by using ANSYS designer and high-frequency structure simulator (HFSS). Based on the frequency-domain analysis, it can be found that CNTs TSV has the lower frequency-dependent loss than Cu due to the lower equivalent resistance. In a summary, CNTs could be a promising TSV filling material at the high-speed transmission frequency based on our study. [ABSTRACT FROM AUTHOR]

In this paper, the equivalent circuit model of interconnect channels in silicon interposer is developed for three-dimensional integrated circuit (3-D IC) based on the theory of multi-conductor transmission line (MTL). The deep neural network (DNN) is employed to learn the nonlinear mapping relationship between the geometric parameters and the distributed parameters, and it is demonstrated that the DNN has a high prediction accuracy. In the implementation, a coarse model is firstly developed by solving the scattering parameters of the model using the chain parameter matrix. The model is optimized using a knowledge-based neural network (KBNN), and a fine model is then established. The numerical examples demonstrate that the optimized model can achieve high accuracy. Finally, the inner contour of the worst-case eye diagrams of the channel is generated using the peak distortion algorithm (PDA), with the worst eye width and height obtained. [ABSTRACT FROM AUTHOR]

Three-dimensional integrated circuit (3D-IC) technology, which involves the vertical integration of multiple chips, has effectively reduced the size of electronic devices and mitigated chip interconnection delays. However, the high integration of 3D-IC brings serious thermal management challenges, especially the heat dissipation of middle-layer or bottom-layer chips. In this study, a 3D-IC thermal management scheme named SLHP based on loop heat pipe is proposed. An SLHP featuring micropillar arrays wick is designed and manufactured, and the feasibility of the SLHP for 3D-IC thermal management is verified through visual experiment, and the influence of changing the location of hotspots and introducing a composite wick on improving the performance of the SLHP is explored. The results indicate that the SLHP operates effectively, demonstrating the capability to adapt to abrupt changes in heat flux. Moreover, the micropillar arrays wick not only provides powerful capillary force, but also larger heat exchange area in limited space. Thoughtful placement of hotspots is profitable to supply liquid fluid and minimize heat leakage from evaporator to compensation chamber. Most significantly, the thermal conductivity of composite wick SLHP reaches 852.1 W/(m·K), surpassing the 810.0 W/(m·K) achieved by the single-size wick SLHP. • A 3D-IC thermal management scheme based on LHP is proposed. • The application of micropillars array wick in SLHP has been effective. • The impact of hotspots position on the fluid replenishment ability is explored. • SLHP with composite wick reaches the higher thermal conductivity of 852.1 W/(m∙K). [ABSTRACT FROM AUTHOR]

Sn-rich solder joints in three-dimensional integrated circuits and their reliability issues, such as the electromigration (EM), thermomigration (TM), and thermomechanical fatigue (TMF), have drawn attention related to their use in electronic packaging. The Sn grain orientation is recognized as playing an important role in reliability issues due to its anisotropic diffusivity, mechanical properties, and coefficient of thermal expansion. This study reviews the effects of the Sn grain orientation on the EM, TM, and TMF in Sn-rich solder joints. The findings indicate that in spite of the failure modes dominated by the Sn grain orientation, the size and shape of the solder joint, as well as the Sn microstructures, such as the cycling twining boundary (CTB), single crystals, and misorientations of the Sn grain boundary, should be considered in more detail. In addition, we show that two methods, involving a strong magnetic field and seed crystal layers, can control the Sn grain orientations during the solidification of Sn-rich solder joints. [ABSTRACT FROM AUTHOR]

In the past decade, monolithic three dimensional integrated circuits (M3D-ICs) advance fast and demonstrate several important breakthroughs in the fabrication process and circuit level design. This article surveys recent research works on M3D technology from the computer system perspective with several case studies, and presents the opportunities as well as the challenges brought by this emerging technology. We also discuss possible applications of M3D based computer architectures. As the M3D technology is attracting enormous attention from both industry and academia, we expect that this article can be a good reference for the researchers and industrial partners who are interested in this fast evolving field, and promote the research activities of computer system/architecture design with this emerging technology. [ABSTRACT FROM AUTHOR]

In this work, an analytical model of strain and stress of symmetrical multilayer medium is proposed to solve the thermal problem that occurs in silicon-core coaxial through-silicon vias (S-CTSV). Based on the 3-D Kane–Mindlin theory, the proposed analytical model of strain considers both elastic strain and thermal strain. In addition, the stress is discussed in segments using planar stress and Hooke’s law in the model of S-CTSVs to improve the accuracy. The results indicate that the average relative errors in terms of strain and stress between the results of the proposed analytical model and the finite-element method (FEM) were 4.06% and 0.17%, respectively. Compared with the back propagation (BP) neural network-based prediction algorithm, the average relative errors in strain and stress between the proposed model and the FEM were decreased by 3.97% and 3.23%, respectively. Moreover, the stress of three different CTSVs was also compared. The stress of the proposed S-CTSVs model was lower than those of the two traditional CTSVs, which ensure higher reliability. The results in this article would provide some design guides for S-CTSVs in 3-D integration. [ABSTRACT FROM AUTHOR]

Rectangular-shaped and disk-shaped heat pipes, as innovative heat sinks, are investigated to optimize the thermal performance of three-dimensional integrated circuits (3D ICs) in this work. Finite volume numerical analysis is employed to carry out the simulation of the thermal performance of 3D ICs. Both rectangular-shaped and disk-shaped heat pipes substantially improved the overall thermal performance and reduced the hotspot temperatures by 7 K and 11 K on average, respectively. Furthermore, utilizing the rectangular-shaped or the disk-shaped heat pipe as the heat spreader in place of a solid copper heat spreader further optimizes the thermal performance by reduction of the junction temperatures 14 K and 16 K on average, respectively. These reductions are achieved while the weight of the setup is also significantly reduced. The results indicate that the innovative flat-shaped heat pipes significantly optimize the thermal performance of 3D ICs. The model and results presented in this work aim to pave the way to markedly alleviate the thermal issues of the 3D ICs. [ABSTRACT FROM AUTHOR]

In 3-D integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield is one of the key obstacles to adopt the TSV-based 3D-ICs technology in industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement. But the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this article, we propose an effective TSV repair strategy for the cellular TSV redundancy architecture, with taking account of the delay overhead. First, we prove that the cellular structure-based fault-tolerance TSV configuration with the delay constraint (CSFTC) is equivalent to the length-bounded multicommodity flow (LBMCF) problem. Next, an integer linear programming formulation is presented to solve the LBMCF problem. Finally, to speed-up the fault-tolerance structure configuration process, an efficient Lagrangian relaxation-based heuristic method is further proposed. Experimental results demonstrate that, compared with the state-of-the-art fault-tolerance structures, the proposed method can provide high yield and low delay overhead. [ABSTRACT FROM AUTHOR]

Three-dimensional integrated circuit (3D IC) technologies have been receiving much attention recently due to the near-ending of Moore's law of minimization in 2D IC. However, the reliability of 3D IC, which is greatly influenced by voids and failure in interconnects during the fabrication processes, typically requires slow testing and relies on human's judgement. Thus, the growing demand for 3D IC has generated considerable attention on the importance of reliability analysis and failure prediction. This research conducts 3D X-ray tomographic images combining with AI deep learning based on a convolutional neural network (CNN) for non-destructive analysis of solder interconnects. By training the AI machine using a reliable database of collected images, the AI can quickly detect and predict the interconnect operational faults of solder joints with an accuracy of up to 89.9% based on non-destructive 3D X-ray tomographic images. The important features which determine the "Good" or "Failure" condition for a reflowed microbump, such as area loss percentage at the middle cross-section, are also revealed. [ABSTRACT FROM AUTHOR]

Three-dimensional integrated circuits (3D-ICs) is a cutting-edge design methodology of placing the circuitry vertically aiming for a high-speed and energy-efficient system with the smallest design area. In this article, a novel 3-D neuromorphic system is proposed and analyzed, which utilizes the fabricated two-layer memristor as the electronic synapses in a spiking neural network (SNN). The two-layer structure of the memristors leads to a significant improvement in the design area ($2\times $), power consumption ($1.48 \times $), and latency ($2.58 \times $), compared to the traditional one-layer configuration. Meanwhile, the heat dissipation layers are added to our memristors reducing 30% cycle-to-cycle switching variation. Our memristive synapses are utilized for storing the exported weights of the SNNs that have threshold function as the activation function. The proposed neuromorphic system is evaluated using a hardware–software co-design approach importing the weights of SNNs into NeuroSIM. The simulation results demonstrate the significant improvement of memristive synapses on design area, power consumption, and latency, compared with the static random-access memory (SRAM) and other state-of-the-art memristive synapses (10%–66%). [ABSTRACT FROM AUTHOR]

Microchannel heat sinks can remove a large amount of heat in the three-dimensional integrated circuits (3-D ICs), thereby effectively solving the heat accumulation problem of chips. Despite improving the heat dissipation performance of chips, unreasonable microchannel design will increase waste and cost. In this article, a model of equivalent thermal conductivity for microchannels is constructed based on the equivalent circuit method, and the temperature response of 3-D IC can be quickly solved. Furthermore, a power adaptive microchannel (PAMC) model based on the collaborative optimization of power distribution and structural parameters is proposed. The results show that the cooling efficiency of the PAMC model is increased by 12.6% compared with the conventional model, which can effectively solve the problem of excessively high peak temperature in the layer and save more space for other circuit designs. [ABSTRACT FROM AUTHOR]

In this article, a new efficient unconditionally stable time-domain modeling algorithm based on the weighted Laguerre polynomial finite-difference time-domain (WLP-FDTD) method is proposed for noise analysis of complex three-dimensional (3-D) power distribution networks (PDNs) including interposers, chips, through-silicon via (TSV) arrays, bumps, and metal–insulator–metal (MIM) capacitors. Combined with weighted Laguerre polynomials (WLPs) as basis functions and Galerkin’s testing procedure, the time variables in the differential equations can be eliminated. Complex structures composed of different ON-chip/interposer PDNs and TSV/bump arrays are modeled and assembled. Subsequently, the differential equations of the 3-D PDN are derived and solved based on WLP-FDTD. Thus, the proposed algorithm can obtain the transient response and analyze noise coupling in a complex 3-D integrated circuit (IC) for the first time. Meanwhile, based on three reasonable test cases, the algorithm can save at least 99.3% and 77.0% computational time compared with the conventional FDTD and SPICE methods, respectively. In addition, the simultaneous switching noise (SSN) in a popular 3-D PDN structure is modeled, calculated, and optimized. An optimal decoupling capacitor selection scheme is discussed, and efficient SSN suppression is achieved. [ABSTRACT FROM AUTHOR]

This article presents prime results on process development and optimization of dry etching of silicon carbide (SiC) for via formation and deep etching for SiC-based microsystems. The investigations and corresponding results of the process developments enable the first realization of a full SiC-based technological demonstrator composed of a SiC-interposer with a flip chip mounted deep etched micro electromechanical system (MEMS) SiC Device. By optimizing the process, etch depth of 200 $\mu \text{m}$ with an etch rate of up to 2 $\mu \text{m}$ /min can be achieved for via etching. In addition, a design of experiments (DoEs) with a total of 29 experiments with seven factors was done to characterize the deep etching of large areas into the SiC. Hereby, vertical sidewalls with low micromasking, low microtrenching and an etch rate of up to 4 $\mu \text{m}$ /min could be achieved. The findings and optimized processes were implemented to develop on the one hand a 200- $\mu \text{m}$ -thick SiC interposer with copper metallization. On the other hand, a SiC-MEMS Device was manufactured with a deep etched cavity in SiC bulk wafer forming by the end a 50- $\mu \text{m}$ thin membrane. The results demonstrate the ability of etching monocrystalline SiC with a high etch rate, enabling new fundamental topologies/structures and packaging concepts for harsh environments MEMSs and high-power electronics. The developed etching technologies demonstrate and enable various applications for 3-D Integration with wide bandgap substrates taking advantage of the superior electrical and mechanical properties of SiC. [ABSTRACT FROM AUTHOR]

In this study, hysteresis-free double-layer gate-all-around stacked poly-Si nanosheet channel ferroelectric HfxZr1-xO2 negative capacitance field-effect transistors (DL GAA NS FE-HZO NC-FETs) with an internal metal gate (IMG) and NH3 plasma nitridation were experimentally investigated and comprehensively discussed for the first time. The results revealed that NH3 plasma nitridation at both the ZrO2/TiN and TiN/HZO interfaces can effectively enhance the HZO ferroelectricity and quality by suppressing the generation of oxygen vacancies (${V}_{o}{)}$. Furthermore, the SiON interfacial layer quality can be enhanced by passivating bulk defects within the SiON interfacial layer through NH3 plasma nitridation at the ZrO2/TiN interface. When NH3 plasma nitridation is performed at both the ZrO2/TiN and TiN/HZO interfaces, the devices exhibit excellent electrical characteristics: 1) an extremely low subthreshold swing (SS) of 45.77 mV/decade; 2) an ultrasteep average SS (ASS) of 61.39 mV/decade; 3) a relatively high ON/OFF current ratio (${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}{)}$ of $ > 5\,\,\times \,\,10^{{7}}$ ; and 4) a quite high effective breakdown voltage (${V}_{\text {EBD}}$) of 6.7 V at ${V}_{D}$ = 0.1 V. Thus, these devices are promising candidates for low-power-consumption monolithic 3-D integrated circuit (IC) applications. [ABSTRACT FROM AUTHOR]

Miniaturized microwave cavities constructed by the parallel-plate waveguide (PPW) becomes one of the main propagation pathways of the radio-frequency interference (RFI) in 3-D integrated circuits. It is still challenging to suppress RFI in the practical cavities, where the space is extremely constrained. In this work, the working mechanism and design method of the noise suppression sheet (NSS) is quantitatively studied, serving as an efficient approach to suppress RFI within an electrically small size in these microwave cavities. The analysis is based on the dispersion relationship derivation of the NSS-loaded PPW structure. Both the derived formulas and the numerical study reveal that the imaginary part of the permeability, that is, $\mu _{i}$ , of the NSS plays a key role in increasing the reflection and attenuation loss, and thus obtaining a high RFI suppression level. Further study indicates even when the NSS’s profile is lower than 10% of the cavity’s height and the length is lower than $0.1\lambda _{0}$ , its suppression level up to 10 dB can be well accomplished, which is deemed difficult to achieve by using conventional methods. Moreover, this method is, respectively, applied in three practical engineering scenarios for the RFI suppression, that is, heatsink package above a chip, power distributed network (PDN), and flexible circuit. Good agreement is observed between the measurement results and the simulated ones, which confirmed the efficacy of our quantitatively developed NSS. The proposed method is promising for broad industrial applications, such as tiny chip packages, multi-channel systems, and flexible electronics. [ABSTRACT FROM AUTHOR]

The 5G and beyond (B5G) networks are expected to provide significantly increased capacity for diverse services with limited spectrum resources. However, new aspects of B5G networks particularly the ultra‐dense network deployment and the heterogeneous network structure, make spectrum resources highly distributed in three‐dimension (3D), which brings unprecedented challenges for highly efficient spectrum utilization, especially in an indoor environment. To tackle the challenges on dynamic spectrum utilization and improving the volume capacity of indoor 3D networks, a collaborated crowdsensing approach is proposed for the coordinated 3D spectrum utilization through integrating the crowdsensing, data analytics, and software defined network (SDN) techniques. The integration of sensing, learning, and intelligent control provides critical capabilities for timely observing 3D radio resources and enabling the coordinated radio resource utilization among co‐existing indoor heterogeneous networks (HetNets). Case study confirms the superiority of the proposed coordinating method on achieved volume capacity. [ABSTRACT FROM AUTHOR]

In this work, we report the experimental demonstration of In2O3 3-D transistors coated on fin structures and integrated circuits by a back-end-of-line (BEOL) compatible atomic layer deposition (ALD) process. High-performance planar back-gate In2O3 transistors with high mobility of 113 cm2/ $\text{V}\cdot \text{s}$ and high maximum drain current (${I}_{\rm D}$) of 2.5 mA/ $\mu \text{m}$ are achieved by channel thickness engineering and postdeposition annealing. The high-performance ALD In2O3-based zero- ${V}_{\rm GS}$ -load inverter is demonstrated with a maximum voltage gain of 38 V/V and a minimum supply voltage (${V}_{\rm DD}$) down to 0.5 V. Top-gate indium oxide (In2O3) transistors by low-temperature ALD of both gate insulator and channel semiconductor are also demonstrated with ${I}_{\rm D}$ of $570~\mu \text{A}/\mu \text{m}$ and low subthreshold slope (SS) down to 84.6 mV/decade. ALD In2O3 3-D Fin transistors with the top-gate structure are then demonstrated, benefiting from the conformal deposition capability of ALD. These results suggest that ALD oxide semiconductors and devices have unique advantages and are promising toward BEOL-compatible monolithic 3-D integration for 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

B Abstract b Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. In the year 2004 she received her M.Sc. Degree in Electrical Engineering at Pontifical Catholic University of Rio Grande do Sul (Brazil) and in 2008 her Ph.D. in Computer Engineering from the Politecnico di Torino (Italy). Graph B Tiago Roberto Balen b received the Electrical Engineering degree, MSc and PhD degrees from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 2004, 2006, and 2010, respectively. [Extracted from the article]

3-D integration is now considered a new paradigm for the semiconductor packaging industry to sustain Moore’s law. Vertical stacking of semiconductor chips provides high power density in a given footprint area. However, owing to increased integration, 3-D ICs having multiple core areas (hotspots) on each stack layer can often be prone to thermal interaction between the stack layers (Interlayer) and within the stack layers (Intralayer). In this work, three layers with three core hotspot areas on each layer are considered. This article proposes an optimization methodology to optimally arrange the hotspot active core areas in three layers of 3-D IC. The optimization methodology aims to minimize the maximum core temperatures and maximize the temperature uniformity in the stack. The optimal placement of hotspot core areas in each layer not only aids in reducing the thermal interaction but also aids in improving the temperature uniformity by thermal spreading. A sampling algorithm based on Latin Hypercube Sampling that incorporates the “nonoverlap” constraint is demonstrated in this study. A Genetic algorithm coupled with supervised machine-learning-based artificial neural network is employed as an optimization methodology. The article introduces a unique arrangement parameter for the multiple numbers of hotspots in various layers that could well represent the problem under consideration. The methods and results from this article could be efficiently used to perform a thermal aware core hotspot arrangement of multilayer multihotspot 3-D integrated circuits for any operating conditions. [ABSTRACT FROM AUTHOR]

This investigation is aimed at the design and optimization of boron arsenide insert structures embedded in the heat spreader of a 3-D Integrated Circuit (IC). The inserts are distributed in three main configurations: radial, one level of pairing, and two levels of pairing. The considered heat spreader is constituted of a composite of copper and highly conductive blades made of boron arsenide with high thermal conductivity. The structures corresponding to the lowest maximum temperature of the 3-D IC while the ratio of the boron arsenide volume to the whole heat spreader volume is fixed, are established. Four different boundary conditions are examined to seek their impact on the optimal configuration of the inserts. The results show that for the constant temperature, variable temperature, convection heat transfer boundary conditions at optimal conditions, the maximum temperature of the whole structure (the structures have not been defined) can be reduced by 13.7%, 11.9%, and 13.9%, respectively; while the size of the plain heat spreader (without HCI) was 200% larger than the recommended HCI embedded one. [ABSTRACT FROM AUTHOR]

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the through-silicon vias (TSVs) defect tend to be clustered, reducing the yield of 3-D integrated circuit significantly. To tackle this fault clustering problem, the existing TSV repair methods adopt the TSV redundancy idea, which brings a major cost to 3-D integration. In this brief, a honeycomb-TDMA TSV design is proposed to mitigate the impact of multiple clustered faults without the need of redundant TSVs (RTSVs), thereby decreasing the area overhead and enhances the yield. The yield of the honeycomb-TDMA architecture can achieve 91.38%–99.67% for different benchmark circuits from IWLS 2005, which has the highest yield. Furthermore, our design achieves total additional hardware (timing delay overhead) reduction by 83.70%–86.85% (46.01%–55.96%), 66.89%–73.25% (29.41%–38.49%), 68.02%–74.20% (41.40%–52.20%), 60.60%–68.18% (18.09%–33.18%), and 75.86%–80.52% (3.05%–20.91%), respectively, compared with router-based, ring-based, group-based, cellular-based, and honeycomb-based methods. Therefore, the proposed architecture is the best choice in terms of yields, hardware overhead, and timing delay. [ABSTRACT FROM AUTHOR]

Through silicon via (TSV)-based 3-D integrated circuit (3-D IC) has several advantages like high density, high bandwidth, and low-power consumption. However, many defects in TSV are evolved during the fabrication and bonding process. In practice, faulty TSVs tend to be clustered. Employing spare TSVs (s-TSVs) is an acceptable method for repairing faulty TSVs. This article introduces a tree-based TSV repair framework to utilize hardware resources more efficiently for a higher repair rate. The proposed architecture partitions the s-TSVs for a different level of redundancy sharing. Experimental results show that the proposed design consumes 11.01 μ m2 area per signal TSV to achieve 99.99% yield for 0.05% failure rate. The proposed architecture also exhibits a higher repair rate of 73.33% for heavily clustered faults. Moreover, for the same number of functional and s-TSVs, the proposed approach reduces the delay overhead efficiently compared to the prior works. [ABSTRACT FROM AUTHOR]

A novel way to implement integrated metal–insulator–metal (MIM) capacitor with ultrahigh capacitance density of up to 5.621.8 nF/mm2 has been proposed earlier. This technology embeds 3-D MIM capacitor into the existing trench of through-silicon via (TSV) prior to Cu filling to achieve >90% planar surface area reduction. However, the previous study was on the early-stage test vehicles without Cu filling. In this work, complete test vehicles with fully filled Cu TSVs have been successfully fabricated whose trench diameters are 0 (D00), 10 (D10), 20 (D20), and 30 μm (D30), respectively. First, the design layout and the process flow are disclosed in detail. Then under scanning electron microscope (SEM) and transmission electron microscope (TEM), it is found that the peak of the Si scallop on the sidewall is deformed for the D30 test vehicle. For the first time, the damage is found in Si substrate, instead of TSV SiO2 liner, due to the thermomechanical stress between the TSV Cu core and the surrounding structures. In addition, the Al2O3 dielectric layer is also impaired at the damaged Si peaks. Finally, the leakage current density is measured and normalized at a bias of 1.5 V: 4 × 10−9 A/cm2 for D00, 4.1 × 10−8 A/cm2 for D10, 1.1 ×10−6 A/cm2for D20, and 7.4 × 10−1 A/cm2 for D30, respectively. Therefore, the structural integrity of the D10 and D20 test vehicles with fully filled Cu TSVs is preserved, but the D30 test vehicle is not intact due to higher stress. The capacitance density of 6.547.1 and 7.091.7 nF/mm2 is recorded for the D10 and D20 test vehicles, respectively. [ABSTRACT FROM AUTHOR]

In this study, p-type Pi-gate (PG) poly-Si nanowire channel junctionless accumulation-mode (JAM) field-effect transistors (FETs) were successfully fabricated and their reliability was investigated. The reliability of these PG JAM FETs was found to be dependent on the effective channel doping concentration (Nch,eff). Through a negative gate bias stress (NGBS) test, we found that degradation in the average subthreshold swing (A.S.S.) and shift in the threshold voltage (VTH) increases as the Nch,eff of the PG JAM FETs decreases. Furthermore, the PG JAM FETs with a lower Nch,eff show the more severe rate of deterioration in the transconductance (Gm) and ON current (ION). By increasing Nch,eff to reduce the electric field (E-field) on the gate oxide and tune the carrier transport mechanism in the poly-Si nanowire channel, a better immunity against the NGBS test in the p-type PG JAM FETs can be achieved under a gate overdrive voltage (VGOD = VG – VTH = −3.5 V) to perform the NGBS test. [ABSTRACT FROM AUTHOR]

This article presents a 3-D reconfigurable memory I/O transceiver using a quad-band interconnect (QBI). The 3-D QBI provides I/O data reconfigurability, decreases latency, and reduces pin count for future compact mobile memory interfaces. The 3-D integrated circuit (3-D IC) technique is utilized to reduce signal latency and improve signal integrity. A novel quad-band transformer is proposed to achieve reconfigurable four-band data communication and reduce the I/O pin count by four times. A two-tier QBI die-stack is implemented to verify the QBI design. Face-to-face configuration with μ bump interconnects is used to save cost. The QBI chips are designed and fabricated in a 180-nm CMOS process. The chip areas of the top and bottom dies are 1.77 and 1.4 mm2, respectively. The measured data rates, with bit error rate (BER) < 10−15, are up to 2 Gb/s in the baseband (BB) and 2.3, 2.5, and 3 Gb/s in RF-bands. The QBI energy efficiencies, with a 1.8-V supply voltage, are 5.9 pJ/b in the BB and 6.2, 7.4, and 8 pJ/b in the RF-bands. [ABSTRACT FROM AUTHOR]

Three-dimensional integrated circuits (3-D IC) technology has emerged in the past few decades, driven in part by the techno-economic difficulties of dimensional scaling and the increasing interconnect delay in microelectronics. In a 3-D IC, vertical integration of multiple transistor planes, either through monolithic integration or through bonding of multiple strata, offers reduced interconnect delay and enhanced design flexibility. However, vertical integration in a 3-D IC also results in severe thermal management challenges. Thermal management of a 3-D IC is exacerbated by the multilayer nature of the 3-D IC. Furthermore, new components such as through-silicon vias (TSVs) offer opportunities for novel thermal management. This article presents a critical review of research literature related to heat transfer in 3-D ICs, focusing specifically on thermal modeling, thermal–electrical codesign, and thermal management of a 3-D IC. Key literature from recent years is categorized and summarized. A discussion on the future outlook for research in these areas is presented. It is expected that this review article will be helpful for researchers in academia and industry for understanding the state-of-the-art in various areas related to heat transfer in 3-D ICs. [ABSTRACT FROM AUTHOR]